SiC device capable of improving reverse voltage endurance capability of device

Abstract

The utility model discloses a SiC device for improving the reverse voltage endurance capability of the device, and relates to the technical field of semiconductors. A layout design of ohmic contacts arranged at intervals is adopted on the top surface of a Pwell main junction in a terminal region of the SiC MOSFET device, and the size of drain-source stray capacitance Cds depends on the area of the ohmic contacts, so that the ohmic contacts arranged at intervals can greatly reduce the contact area, the drain-source stray capacitance Cds caused by grounding of the Pwell main junction in the terminal region of the device can be reduced, and the reliability of the device is improved. And the reverse voltage endurance capability of the device is improved, and meanwhile, the influence of drain-source parasitic capacitance Cds on the switching performance is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC device capable of improving the reverse withstand voltage capability of the device. Background Art

[0002] Third-generation wide-bandgap semiconductor materials are primarily silicon carbide (SiC) and gallium nitride (GaN). GaN power devices offer excellent switching performance, with switching frequencies reaching megahertz. However, due to the industry's horizontal structure, high voltage is difficult to achieve, and current GaN power devices are primarily low-voltage. While SiC power devices cannot achieve the same switching frequencies as GaN, SiC MOSFETs offer excellent overall performance, including high withstand voltage, low conduction losses, and high switching frequency. Particularly in the high-voltage segment, they have begun to gradually replace Si IGBT devices.

[0003] The SiC MOSFET device structure consists of a source region and a terminal region, where the source region serves as the current path for the device, while the terminal region serves to improve the reverse voltage withstand capability of the device during the blocking process, ensuring that the device will not be damaged during system applications. Currently, in order to further improve the reverse voltage withstand capability of SiCMOSFET devices, an ohmic contact is prepared on the top surface of the Pwell main junction in the terminal region of the device to achieve grounding of the Pwell main junction. However, grounding the Pwell main junction can also have adverse effects. It will increase the drain-source parasitic capacitance Cds of the device. The increase in Cds will affect the switching performance of the device. Therefore, how to achieve grounding of the Pwell main junction in the terminal region of the device while reducing the drain-source parasitic capacitance Cds, so that the SiC MOSFET device can achieve better performance, is a technical problem that continues to be solved. Utility Model Content

[0004] In response to the above problems, the present invention provides a SiC device that reduces the drain-source parasitic capacitance Cds caused by the grounding of the main junction Pwell in the device terminal area, thereby improving the reverse withstand voltage capability of the device.

[0005] The technical solution of the utility model is:

[0006] A SiC device with improved reverse voltage withstand capability includes a SiC Sub layer and a SiCDrift layer arranged sequentially from bottom to top;

[0007] The SiC Drift layer is provided with:

[0008] There are several Pwell areas, each extending downward from the top surface of the SiC Drift layer and having a distance from the bottom surface of the SiCDrift layer (2);

[0009] An NP region extending downward from a top surface of the Pwell region of the source region and spaced apart from a bottom surface of the Pwell region;

[0010] There are several PP regions, each extending downward from the top surface of the Pwell region; the PP region in the source region is connected to the NP region;

[0011] A JTE region, located in the terminal region, extending downward from the top surface of the SiC Drift layer and connected to the PP region;

[0012] There are several gate oxide layers, wherein the gate oxide layer of the source region is connected to the NP region, the Pwell region and the SiC Drift layer respectively; the gate oxide layer of the terminal region is connected to the PP region and the Pwell region respectively;

[0013] A field oxide layer is connected to the side of the gate oxide layer in the terminal region, and the bottom surface of the field oxide layer is connected to the JTE region and the SiCDrift layer respectively;

[0014] Poly layer, provided with a plurality of, the Poly layer of the source region is arranged on the top surface of the gate oxide layer, the Poly layer of the terminal region is arranged on the top surface of the gate oxide layer and the field oxide layer;

[0015] An isolation dielectric layer is provided on the top surface of the Poly layer, with its side extending downward and connected to the NP region, the Pwell region of the source region, the PP region of the source region and the SiC Drift layer respectively;

[0016] The ohmic contact alloy layer is provided with a plurality of layers, which are spaced apart and arranged on the top surfaces of the PP region and the NP region of the terminal and the top surface of the PP region of the source region;

[0017] The front electrode metal layer is provided on the top of the device.

[0018] Specifically, the bottom surface of the front electrode metal layer at the terminal area is connected to the ohmic contact alloy layer and the isolation dielectric layer respectively;

[0019] The bottom surface of the front electrode metal layer at the terminal area is connected to the Poly layer through the isolation dielectric layer.

[0020] Specifically, the bottom surface depth of the Pwell area is 1 um-1.2 um.

[0021] Specifically, the bottom surface depth of the NP region is 0.3um-0.6um.

[0022] Specifically, the bottom surface depth of the PP region is 0.5um-1um.

[0023] Specifically, the bottom surface depth of the JTE region is 0.5um-1um.

[0024] This utility model utilizes a spaced-apart ohmic contact layout design on the top surface of the Pwell main junction in the SiC MOSFET device's terminal region. Since the drain-source parasitic capacitance (Cds) depends on the ohmic contact area, the spaced-apart ohmic contacts significantly reduce the contact area, thereby reducing the drain-source parasitic capacitance (Cds) caused by grounding the Pwell main junction in the device's terminal region. This improves the device's reverse withstand voltage capability while also minimizing the impact of the drain-source parasitic capacitance (Cds) on switching performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 1 is a top view of the SiC MOSFET device of the present invention (the figure hides the Pwell region 3, NP region 4, PP region 5, JTE region 6, gate oxide layer 7, field oxide layer 8, Poly layer 9, and front electrode metal layer 12);

[0026] Figure 2 yes Figure 1 Structural diagram of the AA section along the X direction;

[0027] Figure 3 yes Figure 1 Structural diagram of BB section along the X direction;

[0028] In the figure, 1 is the SiC Sub layer, 2 is the SiCDrift layer, 3 is the Pwell region, 4 is the NP region, 5 is the PP region, 6 is the JTE region, 7 is the gate oxide layer, 8 is the field oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0029] The present invention will be described in detail below with reference to specific practical cases. Examples of the embodiments are shown in the accompanying drawings. The schematic implementations of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0030] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this utility model. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting this utility model. In the description of this utility model, unless otherwise specified, "plurality" means two or more.

[0031] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0032] A method for preparing a SiC device for improving the reverse withstand voltage capability of the device comprises the following steps:

[0033] S100, epitaxially growing a SiC Drift layer 2 on the SiC Sub layer 1;

[0034] The doping concentration of the SiC Sub layer 1 in step S100 is 1E19 cm -2 The doping concentration of SiC Drift layer 2 is 5E16-1.2E16cm -2 .

[0035] S200 , forming a plurality of spaced Pwell regions 3 on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0036] The bottom depth of the Pwell region 3 in step S200 is 1um-1.2um, and the doping concentration is 1E17-3E18cm -2 .

[0037] S300 , forming an NP region 4 by N ion implantation on the top surface of the Pwell region 3 at the source region position;

[0038] The bottom depth of the NP region 4 in step S300 is 0.3um-0.6um, and the doping concentration is 1E18-1E19cm -2 .

[0039] S400, forming a PP region 5 on the top surface of the Pwell region 3 by Al ion implantation; the PP region 5 at the source region position is connected to the NP region 4;

[0040] The bottom depth of the PP region 5 in step S400 is 0.5um-1um, and the doping concentration is 1E18-1E19cm -2 .

[0041] S500, forming a JTE region 6 on the top surface of the SiC Drift layer 2 by Al ion implantation. The JTE region 6 is connected to the Pwell region 3 at the terminal region. The JTE region 6 serves as a protection structure for the device terminal and improves the reverse withstand voltage capability of the device.

[0042] The bottom depth of the JTE region 6 in step S500 is 0.5um-1um, and the doping concentration is 1E17-1E18cm -2 .

[0043] S600, the Pwell region 3, the NP region 4, the PP region 5 and the JTE region 6 are activated and formed by high temperature ion activation;

[0044] The high temperature ion activation temperature in step S600 is in the range of 1600°C to 1700°C.

[0045] S700, forming a gate oxide layer 7 on the top surface of the SiC Drift layer 2 by dry oxygen oxidation;

[0046] The thickness of the gate oxide layer 7 in step S700 is 40 nm to 60 nm.

[0047] S800, forming a field oxide layer 8 on the top surface of the SiC Drift layer 2 by oxide deposition;

[0048] The thickness of the field oxide layer 8 in step S800 is 0.8 um-1.2 um.

[0049] S900, forming a Poly layer 9 on top of the gate oxide layer 7 and the field oxide layer 8 by polysilicon Poly deposition. The Poly layer 9 serves as a gate electrode path of the device.

[0050] The thickness of the deposited Poly layer 9 in step S900 is 0.5 μm-1 μm.

[0051] S1000: forming an isolation dielectric layer 10 on the top surfaces of the SiC Drift layer 2, the NP region 4, and the Poly layer 9 by oxide deposition. The isolation dielectric layer 10 is used to isolate the gate electrode and the source electrode of the device to prevent short circuit between the two.

[0052] S1100, forming an ohmic contact alloy layer 11 on the top surfaces of the NP region 4 and the PP region 5 by sputtering Ni metal and then performing rapid thermal annealing;

[0053] The Ni metal sputtering thickness in step S1100 is 0.1um-0.3um.

[0054] S1200, forming a front electrode metal layer 12 above the device by sputtering Ti and AlCu metals, the front electrode metal layer 12 functions as a source electrode and a gate electrode of the device;

[0055] In step S1200 , the thickness of the Ti metal is 0.1 um-0.3 um, and the thickness of the AlCu metal is 3 um-5 um.

[0056] A SiC device for improving reverse withstand voltage capability of the device includes a SiC sub layer 1 and a SiCDrift layer 2 arranged sequentially from bottom to top;

[0057] The SiC Drift layer 2 is provided with:

[0058] There are several Pwell areas 3, each extending downward from the top surface of the SiC Drift layer 2 and spaced apart from the bottom surface of the SiC Drift layer 2;

[0059] The NP region 4 extends downward from the top surface of the Pwell region 3 of the source region and is spaced apart from the bottom surface of the Pwell region 3;

[0060] There are several PP regions 5, each extending downward from the top surface of the Pwell region 3; the PP region 5 in the source region is connected to the NP region 4;

[0061] A JTE region 6, located in the terminal region, extends downward from the top surface of the SiC Drift layer 2 and is connected to the PP region 5;

[0062] The gate oxide layer 7 is provided with several gate oxide layers. The gate oxide layer 7 in the source region is respectively connected to the NP region 4, the Pwell region 3 and the SiC Drift layer 2; the gate oxide layer 7 in the terminal region is respectively connected to the PP region 5 and the Pwell region 3;

[0063] A field oxide layer 8 is connected to the side of the gate oxide layer 7 in the terminal region, and the bottom surface of the field oxide layer 8 is connected to the JTE region 6 and the SiC Drift layer 2 respectively;

[0064] Poly layer 9, provided with a plurality of, the Poly layer 9 of the source region is arranged on the top surface of the gate oxide layer 7, the Poly layer 9 of the terminal region is arranged on the top surface of the gate oxide layer 7 and the field oxide layer 8;

[0065] An isolation dielectric layer 10 is provided on the top surface of the Poly layer 9, with its side extending downward and connected to the NP region 4, the Pwell region 3 of the source region, the PP region 5 of the source region, and the SiC Drift layer 2 respectively;

[0066] The ohmic contact alloy layer 11 is provided with a plurality of layers, which are spaced apart and arranged on the top surfaces of the PP region 5 and the NP region 4 of the terminal and the top surface of the PP region 5 of the source region;

[0067] The front electrode metal layer 12 is disposed on the top of the device.

[0068] The bottom surface of the front electrode metal layer 12 at the terminal area is connected to the ohmic contact alloy layer 11 and the isolation dielectric layer 10 respectively;

[0069] The bottom surface of the front electrode metal layer 12 at the terminal area passes through the isolation dielectric layer 10 and is connected to the Poly layer 9 .

[0070] Currently, the industry prepares ohmic contacts on the top surface of the Pwell main junction in the terminal area of ​​SiC MOSFET devices to achieve Pwell main junction grounding, which can further improve the reverse voltage withstand capability of the device during the blocking process. However, the negative impact of Pwell main junction grounding is that it increases the drain-source parasitic capacitance Cds of the device. The increase in Cds will reduce the switching performance of the device. Therefore, the present invention is to achieve this goal by Figure 1 The structure shown in FIG. 1 significantly reduces the area of ​​the ohmic contacts by staggering the ohmic contacts on the top surface of the Pwell main junction in the terminal region. This not only improves the withstand voltage by grounding the Pwell main junction, but also reduces the drain-source parasitic capacitance Cds, minimizing the impact of Cds on the switching performance of the device.

Claims

1. A SiC device with improved reverse withstand voltage capability, characterized in that: It includes a SiC Sub layer (1) and a SiC Drift layer (2) arranged sequentially from bottom to top; The SiC Drift layer (2) is provided with: A Pwell region (3) is provided, each extending downward from the top surface of the SiC Drift layer (2); An NP region (4) extending downward from the top surface of the Pwell region (3) of the source region; There are several PP regions (5) extending downward from the top surface of the Pwell region (3); the PP region (5) in the source region is connected to the NP region (4); A JTE region (6), located in the terminal region, extends downward from the top surface of the SiC Drift layer (2) and is connected to the PP region (5); The gate oxide layer (7) is provided with a plurality of gate oxide layers, wherein the gate oxide layer (7) in the source region is respectively connected to the NP region (4), the Pwell region (3) and the SiCDrift layer (2); and the gate oxide layer (7) in the terminal region is respectively connected to the PP region (5) and the Pwell region (3); A field oxide layer (8) is connected to the side of the gate oxide layer (7) in the terminal region, and the bottom surface of the field oxide layer (8) is respectively connected to the JTE region (6) and the SiC Drift layer (2); A plurality of Poly layers (9) are provided, wherein the Poly layer (9) in the source region is provided on the top surface of the gate oxide layer (7), and the Poly layer (9) in the terminal region is provided on the top surfaces of the gate oxide layer (7) and the field oxide layer (8); An isolation dielectric layer (10) is provided on the top surface of the Poly layer (9), with its side portion extending downward and connected to the NP region (4), the Pwell region (3) of the source region, the PP region (5) of the source region, and the SiC Drift layer (2); The ohmic contact alloy layer (11) is provided with a plurality of layers, which are spaced apart and arranged on the top surfaces of the PP region (5) and the NP region (4) at the terminal and the top surface of the PP region (5) in the source region; A front electrode metal layer (12) is provided on the top of the device.

2. The SiC device for improving reverse withstand voltage capability of the device according to claim 1, characterized in that: The bottom surface of the front electrode metal layer (12) at the terminal area is connected to the ohmic contact alloy layer (11) and the isolation dielectric layer (10) respectively; The bottom surface of the front electrode metal layer (12) at the terminal area passes through the isolation dielectric layer (10) and is connected to the Poly layer (9).

3. The SiC device for improving reverse withstand voltage capability of the device according to claim 1, characterized in that: The bottom surface depth of the Pwell area (3) is 1um-1.2um.

4. The SiC device for improving reverse withstand voltage capability of the device according to claim 1, characterized in that: The bottom surface depth of the NP region (4) is 0.3um-0.6um.

5. The SiC device for improving reverse withstand voltage capability of the device according to claim 1, characterized in that: The bottom surface depth of the PP region (5) is 0.5um-1um.

6. The SiC device for improving reverse withstand voltage capability of the device according to claim 1, characterized in that: The bottom surface depth of the JTE region (6) is 0.5um-1um.

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