SiC device with improved safety and stability

Abstract

A SiC device with improved safety and stability relates to the technical field of semiconductors. A P region is formed at the bottom of a JFET of a SiC Drift layer in a SiC MOSFET device, and when the device works in a saturation region, the P region is connected with a depletion layer formed by a Pwell region and the SiC Drift layer, so that short-circuit current is better shielded, and temperature rise of the device during short circuit is reduced. And meanwhile, when the device works in a linear region, the drain voltage is relatively small, and a depletion layer formed by the P region and the SiC Drift layer is not connected with a depletion layer formed by the Pwell region, so that the outflow capacity of the device working in the linear region is not excessively influenced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a SiC device with improved safety and stability. Background Art

[0002] As a representative of third-generation wide-bandgap semiconductor materials, SiC possesses numerous significant physical advantages, such as a wide bandgap, high critical breakdown electric field, low intrinsic carrier concentration, fast saturation drift velocity, high melting point, and high thermal conductivity. These material properties enable SiC-based power devices to achieve high breakdown voltage, low conduction losses, and high switching frequency in a compact and thin form factor. This provides significant advantages in applications involving high voltage, high temperature, high frequency, and high radiation exposure. Currently, SiC MOSFETs are widely used in the market, replacing Si IGBTs and other devices.

[0003] When the gate is open and operating normally, SiC MOSFET devices are divided into two regions: the linear region and the saturation region. When the device is short-circuited, it is operating in the saturation region. Compared with SiIGBT, SiC MOSFET devices have very poor short-circuit capability, and their short-circuit withstand time is only about 3us. During a short circuit, the device temperature rises rapidly, which can easily burn the device. Therefore, the short-circuit characteristics of SiC MOSFETs must always be fully considered in the early stages of design to avoid failures on the system side. Therefore, developing a method to reduce the short-circuit current of SiC MOSFET devices in the saturation region, achieve higher short-circuit capability of the device, and improve the safe and stable use of the device is a technical problem that needs to be solved urgently. Utility Model Content

[0004] In response to the above problems, the present invention provides a SiC device that reduces the temperature rise of the device during a short circuit while avoiding excessive impact on the current output capability of the device when operating in the linear region, thereby improving safety and stability.

[0005] The technical solution of the utility model is:

[0006] SiC devices with improved safety and stability include a SiC Sub layer, a SiC Drift layer, a SiCEpi layer, a gate oxide layer, a Poly layer, an isolation dielectric layer, and a front electrode metal layer, which are arranged in sequence from bottom to top;

[0007] The top surface of the SiC Drift layer is provided with a P region extending downward;

[0008] The SiC Epi layer is provided with:

[0009] A pair of Pwell regions are provided, each extending downward from the top surface of the SiC Epi layer; the pair of Pwell regions are spaced apart and have a distance from the bottom surface of the SiC Epi layer;

[0010] A pair of NP areas are provided, each extending downward from the top surface of the Pwell area; a gap is set between the NP area and the bottom surface of the Pwell area; a gap is set between the side of the NP area and the side of the Pwell area;

[0011] A pair of PP zones are provided, each extending downward from the top surface of the Pwell zone and located on the side of the NP zone;

[0012] The bottom surface of the gate oxide layer is connected to the top surfaces of the NP region, the Pwell region and the SiC Epi layer respectively;

[0013] The isolation dielectric layer is wrapped around the gate oxide layer and the Poly layer, with the side portion extending downward and connected to the NP region;

[0014] The side of the isolation dielectric layer is provided with an ohmic contact alloy layer connected to the PP region and the NP region respectively.

[0015] Specifically, the bottom surface of the front electrode metal layer is connected to the isolation dielectric layer and the ohmic contact alloy layer respectively.

[0016] Specifically, the bottom surface of the front electrode metal layer (12) is connected to the isolation dielectric layer (10) and the ohmic contact alloy layer (11) respectively.

[0017] Specifically, the SiC Drift layer has a thickness of 5 μm to 20 μm.

[0018] Specifically, the depth between the bottom surface of the P region and the top surface of the SiC Drift layer is 0.3 μm-0.5 μm.

[0019] Specifically, the thickness of the SiC Epi layer is 1.5um-3um.

[0020] Specifically, the depth between the bottom surface of the Pwell region and the top surface of the SiC Epi layer is 0.4 μm-1.5 μm.

[0021] In this SiC MOSFET device, a P region is formed at the bottom of the JFET in the SiC Drift layer. When the device operates in the saturation region, the P region, the Pwell region, and the depletion layer formed by the SiC Drift layer are interconnected, thereby effectively shielding the short-circuit current and reducing the temperature rise of the device during a short circuit. At the same time, when the device operates in the linear region, because the drain voltage is relatively low, the depletion layer formed by the P region and the SiC Drift layer will not connect with the depletion layer formed by the Pwell region, thereby not significantly affecting the device's current output capability when operating in the linear region. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1This is a schematic diagram of the SiC MOSFET of the utility model operating in the linear region;

[0023] Figure 2 This is a schematic diagram of the SiC MOSFET of the utility model operating in the saturation region;

[0024] Figure 3 It is a structural diagram of step S100 of the present utility model;

[0025] Figure 4 It is a structural diagram of step S200 of the present utility model;

[0026] Figure 5 It is a structural diagram of step S300 of the present utility model;

[0027] Figure 6 It is a structural diagram of step S400 of the present utility model;

[0028] Figure 7 It is a structural diagram of step S500 of the present utility model;

[0029] Figure 8 It is a structural diagram of step S600 of the present utility model;

[0030] Figure 9 It is a structural diagram of step S700 of the present utility model;

[0031] Figure 10 It is a structural diagram of step S800 of the present utility model;

[0032] Figure 11 It is a structural diagram of step S900 of the present utility model;

[0033] Figure 12 It is a structural diagram of step S1000 of the present utility model;

[0034] Figure 13 It is a structural diagram of step S1100 of the present utility model;

[0035] In the figure, 1 is the SiC Sub layer, 2 is the SiCDrift layer, 3 is the P region, 4 is the SiC Epi layer, 5 is the Pwell region, 6 is the NP region, 7 is the PP region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0036] The present invention will be described in detail below with reference to specific practical cases. Examples of the embodiments are shown in the accompanying drawings. The schematic implementations of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0037] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this utility model. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting this utility model. In the description of this utility model, unless otherwise specified, "plurality" means two or more.

[0038] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0039] Improving the safety and stability of SiC devices includes the following steps:

[0040] S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition;

[0041] In step S100, the thickness of SiC Sub layer 1 is 100um-400um, and the doping concentration is 1E19-3E19cm -2 ; SiCDrift layer 2 thickness is 5um-20um, and the doping concentration is 1E15-5E16cm -2 .

[0042] S200 , forming a P region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0043] The depth of the bottom surface of the P region 3 from the top surface of the SiC Drift layer 2 in step S200 is 0.3um-0.5um, and the doping concentration is 1E17-3E18cm -2 .

[0044] S300 , forming a SiC Epi layer 4 on the top surface of the SiC Drift layer 2 again by epitaxial deposition;

[0045] The thickness of the SiC Epi layer 4 in step S300 is 1.5um-3um, and the doping concentration is 1E15-1E17cm -2 .

[0046] S400 , forming a pair of spaced-apart Pwell regions 5 on the top surface of the SiC Epi layer 4 by Al ion implantation;

[0047] The depth of the bottom surface of the Pwell region 5 from the top surface of the SiC Epi layer 4 in step S400 is 0.4um-1.5um, and the doping concentration is 1E17-3E18cm -2 .

[0048] S500 , forming an NP region 6 on the top surface of the Pwell region 5 by N ion implantation;

[0049] The depth of the bottom surface of the NP region 6 from the top surface of the SiC Epi layer 4 in step S500 is 0.2um-1um, and the doping concentration is 1E18-1E19cm -2 .

[0050] S600, forming a PP region 7 on the top surface of the Pwell region 5 by Al ion implantation, and then activating all implanted regions by high temperature ion annealing;

[0051] The depth of the bottom surface of the PP region 7 from the top surface of the SiC Epi layer 4 in step S600 is 0.2um-1.2um, and the doping concentration is 5E18-1E19cm -2 .

[0052] S700 , performing high-temperature dry oxygen oxidation on the top surface of the SiC Epi layer 4 by introducing oxygen to form a gate oxide layer 8 ;

[0053] The thickness of the gate oxide layer 8 in step S700 is 30 nm to 70 nm.

[0054] S800 , forming a Poly layer 9 on the top surface of the gate oxide layer 8 by polysilicon deposition;

[0055] S900 , forming an isolation dielectric layer 10 on the top surfaces of the NP region 6 and the Poly layer 9 by oxide deposition;

[0056] S1000, forming an ohmic contact alloy layer 11 on the top surfaces of the NP region 6 and the PP region 7 by sputtering Ni metal and then thermal annealing;

[0057] The thickness of the Ni metal in step S1000 is 0.3um-1um.

[0058] S1100, forming a front electrode metal layer 12 on the top of the device by sputtering Ti and AlCu metals;

[0059] In step S1100 , the thickness of the Ti metal is 0.1 um to 0.6 um, and the thickness of the AlCu metal is 2 um to 5 um.

[0060] A SiC device with improved safety and stability includes, arranged from bottom to top, a SiC sub-layer 1, a SiC drift layer 2, a SiC epi-layer 4, a gate oxide layer 8, a poly layer 9, an isolation dielectric layer 10, and a front electrode metal layer 12;

[0061] The top surface of the SiC Drift layer 2 is provided with a P region 3 extending downward;

[0062] The SiC Epi layer 4 is provided with:

[0063] A pair of Pwell regions 5 are provided, each extending downward from the top surface of the SiC Epi layer 4; the pair of Pwell regions 5 are spaced apart and have a distance from the bottom surface of the SiC Epi layer 4;

[0064] A pair of NP areas 6 are provided, each extending downward from the top surface of the Pwell area 5; a gap is set between the NP area 6 and the bottom surface of the Pwell area 5; and a gap is set between the side of the NP area 6 and the side of the Pwell area 5;

[0065] A pair of PP zones 7 are provided, each extending downward from the top surface of the Pwell zone 5 and located on the side of the NP zone 6;

[0066] The bottom surface of the gate oxide layer 8 is connected to the top surfaces of the NP region 6, the Pwell region 5 and the SiC Epi layer 4 respectively;

[0067] The isolation dielectric layer 10 is wrapped around the gate oxide layer 8 and the Poly layer 9, with its side extending downward and connected to the NP region 6;

[0068] An ohmic contact alloy layer 11 is provided on the side of the isolation dielectric layer 10 and is connected to the PP region 7 and the NP region 6 respectively.

[0069] The bottom surface of the front electrode metal layer 12 is connected to the isolation dielectric layer 10 and the ohmic contact alloy layer 11 respectively.

[0070] When the gate of SiC MOSFET is open and the device is working normally, it is divided into two regions: linear region and saturation region. When the device is short-circuited, it is working in the saturation region. Compared with SiIGBT, the short-circuit capability of SiC MOSFET devices is very poor, and its short-circuit withstand time is only about 3us. When short-circuited, the temperature rise of the device will increase rapidly, which can easily burn the device. Therefore, if the short-circuit current of SiC MOSFET devices in the saturation region can be reduced, a higher short-circuit capability of the device can be achieved, and the safe and stable use of the device can be improved. In the present invention, a P region 3 is formed at the bottom of the JFET in the SiC Drift layer in the SiC MOSFET device. When the device is working in the saturation region (such as Figure 2As shown in the figure, the depletion layer formed by the P region 3, the Pwell region 5 and the SiC Drift layer 2 will be connected to each other, thereby better shielding the short-circuit current and reducing the temperature rise of the device during short circuit. At the same time, when the device is working in the linear region (as shown in the figure), the depletion layer formed by the P region 3, the Pwell region 5 and the SiC Drift layer 2 will be connected to each other, thereby better shielding the short-circuit current and reducing the temperature rise of the device during short circuit. Figure 1 As shown in FIG, because the drain voltage is small, the depletion layer formed by the P region 3 and the SiC Drift layer 2 will not be connected to the depletion layer formed by the Pwell region 5, thereby not significantly affecting the outflow capability of the ID current when the device operates in the linear region.

Claims

1. A SiC device with improved safety and stability, characterized in that: It comprises a SiC Sub layer (1), a SiC Drift layer (2), a SiC Epi layer (4), a gate oxide layer (8), a Poly layer (9), an isolation dielectric layer (10) and a front electrode metal layer (12) which are arranged in sequence from bottom to top; The top surface of the SiC Drift layer (2) is provided with a P region (3) extending downward; The SiC Epi layer (4) is provided with: A pair of Pwell regions (5) are provided, each extending downward from the top surface of the SiC Epi layer (4); A pair of NP regions (6) are provided, each extending downward from the top surface of the Pwell region (5); A pair of PP zones (7) are provided, each extending downward from the top surface of the Pwell zone (5) and located on the side of the NP zone (6); The bottom surface of the gate oxide layer (8) is respectively connected to the top surfaces of the NP region (6), the Pwell region (5) and the SiC Epi layer (4); The isolation dielectric layer (10) is wrapped on the gate oxide layer (8) and the Poly layer (9), with the side portion extending downward and connected to the NP region (6); The side of the isolation dielectric layer (10) is provided with an ohmic contact alloy layer (11) connected to the PP region (7) and the NP region (6) respectively.

2. The SiC device with improved safety and stability according to claim 1, characterized in that: The bottom surface of the front electrode metal layer (12) is respectively connected to the isolation dielectric layer (10) and the ohmic contact alloy layer (11).

3. The SiC device with improved safety and stability according to claim 1, characterized in that: The SiC Drift layer (2) has a thickness of 5um-20um.

4. The SiC device with improved safety and stability according to claim 1, characterized in that: The depth between the bottom surface of the P region (3) and the top surface of the SiC Drift layer (2) is 0.3um-0.5um.

5. The SiC device with improved safety and stability according to claim 1, characterized in that: The SiC Epi layer (4) has a thickness of 1.5 μm to 3 μm.

6. The SiC device with improved safety and stability according to claim 1, characterized in that: The depth between the bottom surface of the Pwell region (5) and the top surface of the SiC Epi layer (4) is 0.4um-1.5um.

Images