Frequency-adjustable DDS and PLL phase-locked loop circuit
By introducing frequency control, DA conversion, amplification, limiting and filtering modules into the frequency synthesizer, the problem of unadjustable frequency in the phase-locked loop circuit is solved, and the flexible adjustment of the output signal frequency of the voltage-controlled oscillator is achieved to meet various frequency requirements.
Patent Information
- Application Number
- CN202422776442.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2034-11-14
AI Technical Summary
In the prior art, the phase-locked loop circuit cannot adjust the frequency of the first specified frequency signal output by the frequency synthesizer, resulting in the frequency of the voltage-controlled oscillator output signal being constant and unable to be adjusted as needed.
A frequency control module, a DA conversion module, an amplification module, a limiting module and a filtering module are introduced into the frequency synthesizer. The frequency adjustment is achieved through the combination of these modules. The frequency control module outputs a digital signal, the DA conversion module converts it into an analog signal, the amplification module amplifies it, the limiting module forms a square wave signal, and the filtering module performs filtering, ultimately providing an adjustable frequency signal for the phase detector.
The flexible adjustment of the output signal frequency of the voltage-controlled oscillator is realized to meet different frequency requirements and improve the frequency adjustability of the phase-locked loop circuit.
Smart Images
Figure CN223322069U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a phase-locked loop circuit, in particular to a frequency-adjustable DDS and PLL phase-locked loop circuit. Background Art
[0002] The output of the phase-locked loop circuit is a specified frequency signal, and the phase-locked loop circuit is of great significance in signal transmission.
[0003] In the prior art, a phase-locked loop circuit includes: a voltage regulator, a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency synthesizer. The output of the voltage regulator is used to receive a signal to be processed. The output of the voltage regulator is connected to the first input of the phase detector, the output of the phase detector is connected to the input of the loop filter, the output of the loop filter is connected to the input of the voltage-controlled oscillator, the output of the voltage-controlled oscillator is connected to the input of the frequency synthesizer, and the output of the frequency synthesizer is connected to the second input of the phase detector. The frequency synthesizer synthesizes a first specified frequency signal based on the frequency of the signal to be processed. The first specified frequency signal and the signal to be processed are converted into a second specified frequency signal at the phase detector. The frequency of the first specified frequency signal processed by the frequency synthesizer directly affects the frequency of the final output signal of the voltage-controlled oscillator. However, in the prior art, the frequency of the first specified frequency signal output by the frequency synthesizer cannot be adjusted, resulting in a constant frequency of the final output signal of the voltage-controlled oscillator, making it impossible to adjust the frequency of the final output signal of the voltage-controlled oscillator as needed. Utility Model Content
[0004] The utility model provides a frequency adjustable DDS and PLL phase-locked loop circuit to solve the problem in the prior art that the frequency of a first specified frequency signal output by a frequency synthesizer cannot be adjusted.
[0005] In order to achieve the above purpose, the present invention adopts the following technical solutions:
[0006] The utility model discloses a frequency-adjustable DDS and PLL phase-locked loop circuit, comprising: a voltage stabilizer, a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency synthesizer. The output end of the voltage stabilizer is used to access a signal to be processed, the output end of the voltage stabilizer is connected to a first input end of the phase detector, the output end of the phase detector is connected to an input end of the loop filter, the output end of the loop filter is connected to an input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to an input end of the frequency synthesizer, and the output end of the frequency synthesizer is connected to a second input end of the phase detector. The frequency synthesizer comprises: a frequency control module, a DA conversion module, an amplification module, a limiter module, a filtering module, and a human-computer interaction module. The input end of the frequency control module is the input end of the frequency synthesizer, the first output end of the frequency control module is connected to the input end of the DA conversion module, the output end of the DA conversion module is connected to the input end of the amplification module, the output end of the amplification module is connected to the input end of the limiter module, the output end of the limiter module is connected to the input end of the filtering module, the output end of the filtering module is the output end of the frequency synthesizer, and the output end of the human-computer interaction module is connected to the input end of the frequency control module.
[0007] Preferably, the amplification module includes: an amplifier U3, a resistor R4 and a feedback resistor group unit, the first end of the resistor R4 is the input end of the amplification module, the second end of the resistor R4 is connected to the inverting input end of the amplifier U3 and the first end of the feedback resistor group unit, the second end of the feedback resistor group unit is connected to the output end of the amplifier U3, the output end of the amplifier U3 is the output end of the amplification module, and the non-inverting input end of the amplifier U3 is grounded.
[0008] Preferably, the limiting module includes: a limiting main circuit unit, an upper limiting unit, an upper resistor group unit, a lower limiting unit and a lower resistor group unit, the input end of the limiting main circuit unit is used to connect to the output end of the amplification module, the output end of the limiting main circuit unit is the output end of the limiting module, the high voltage end of the upper resistor group unit and the high voltage end of the lower resistor group unit are both connected to the first DC power supply output end, the low voltage end of the upper resistor group unit and the low voltage end of the lower resistor group unit are both connected to the second DC power supply output end, the voltage output end of the upper resistor group unit is connected to the reference voltage input end of the upper limiting unit, and the output end of the upper limiting unit is connected to the output end of the limiting main circuit unit; the voltage output end of the lower resistor group unit is connected to the reference voltage input end of the lower limiting unit, and the output end of the lower limiting unit is connected to the output end of the limiting main circuit unit.
[0009] Preferably, controllable switches are provided in the feedback resistor group unit, the upper resistor group unit and the lower resistor group unit, and all controllable switches in the feedback resistor group unit, the upper resistor group unit and the lower resistor group unit operate under one controlled device, and the control end of the controlled device is connected to the second output end of the frequency control module.
[0010] Preferably, all controllable switches and controlled devices are in one relay, and the controllable switches include: a first single-pole double-throw switch SW1, a second single-pole double-throw switch SW2, and a third single-pole double-throw switch SW3, the first single-pole double-throw switch SW1 is arranged in the feedback resistor group unit, the second single-pole double-throw switch SW2 is arranged in the upper resistor group unit, and the third single-pole double-throw switch SW3 is arranged in the lower resistor group unit.
[0011] Preferably, the feedback resistor group unit includes: a resistor R1, a resistor R2, and a resistor R3, wherein the first end of the resistor R1, the first end of the resistor R2, and the first end of the resistor R3 are connected to form a first end of the feedback resistor group unit, the second end of the resistor R2 is connected to a first movable end of the first single-pole double-throw switch SW1, the second end of the resistor R3 is connected to a second movable end of the first single-pole double-throw switch SW1, and the fixed end of the first single-pole double-throw switch SW1 is connected to the second end of the resistor R1 to form a second end of the feedback resistor group unit.
[0012] Preferably, the upper resistor group unit includes: resistor R6, resistor R7, resistor R8 and resistor R9, the first end of resistor R6 is the high-voltage end of the upper resistor group unit, the second end of resistor R6 is connected to the first end of resistor R8 through resistor R7, the second end of resistor R8 is connected to one end of resistor R9, the other end of resistor R9 is the low-voltage end of the upper resistor group unit, the second end of resistor R6 is connected to the first moving end of the second single-pole double-throw switch SW2, the first end of resistor R8 is connected to the second moving end of the second single-pole double-throw switch SW2, and the fixed end of the second single-pole double-throw switch SW2 is the voltage output end of the upper resistor group unit.
[0013] Preferably, the lower resistor group unit includes: resistor R10, resistor R11, resistor R12 and resistor R13, the first end of resistor R10 is the high-voltage end of the lower resistor group unit, the second end of resistor R10 is connected to the first end of resistor R12 through resistor R11, the second end of resistor R12 is connected to the first end of resistor R13, the second end of resistor R13 is the low-voltage end of the lower resistor group unit, the second end of resistor R10 is connected to the first moving end of the third single-pole double-throw switch SW3, the first end of resistor R12 is connected to the second moving end of the third single-pole double-throw switch SW3, and the fixed end of the third single-pole double-throw switch SW3 is the voltage output end of the lower resistor group unit.
[0014] Preferably, the limiting main circuit unit includes: an amplifier U4 and a resistor R5, the non-inverting input end of the amplifier U4 is the input end of the limiting main circuit unit, the inverting input end of the amplifier U4 is connected to the output end of the amplifier U4, the output end of the amplifier U4 is connected to one end of the resistor R5, and the other end of the resistor R5 is the output end of the limiting main circuit unit.
[0015] Preferably, the upper limit amplitude unit includes: an amplifier U5 and a diode D1, the non-inverting input terminal of the amplifier U5 is the reference voltage input terminal of the upper limit amplitude unit, the inverting output terminal of the amplifier U5 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the output terminal of the amplifier U5, and the anode of the diode D1 is the output terminal of the upper limit amplitude unit;
[0016] The lower limiter unit includes: an amplifier U6 and a diode D2. The non-inverting input terminal of the amplifier U6 is the reference voltage input terminal of the lower limiter unit. The inverting output terminal of the amplifier U6 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the output terminal of the amplifier U6. The anode of the diode D2 is the output terminal of the lower limiter unit.
[0017] Compared with the prior art, the present invention has the following beneficial effects:
[0018] In this application, a frequency control module is used to output a digital signal with a specified frequency, a DA conversion module converts the digital signal with a specified frequency into an analog signal with a specified frequency, and then the amplification module amplifies the analog signal with a specified frequency. The limiting module then converts the analog signal with a specified frequency into a square wave signal with a specified frequency, and finally the filtering module filters the square wave signal. As long as the digital signal with a specified frequency output by the frequency control module is controlled to change, different square wave signals with specified frequencies can be output to provide the phase detector with a square wave signal with a specified frequency, thereby realizing frequency control and adjustment to meet different frequency requirements.
[0019] Other advantages, objectives and features of the present invention will be reflected in part through the following description, and in part will be understood by those skilled in the art through research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is the circuit block diagram of the frequency-adjustable DDS and PLL phase-locked loop circuit.
[0021] Figure 2 This is the circuit diagram of the DA conversion module and the amplification module.
[0022] Figure 3 This is the circuit diagram of the limiting module. DETAILED DESCRIPTION
[0023] In order to make the technical means, creative features, objectives and functions of the present invention clearer and easier to understand, the present invention is further described below with reference to the accompanying drawings and specific embodiments:
[0024] like Figures 1 to 3As shown, the utility model discloses a frequency-adjustable DDS and PLL phase-locked loop circuit, comprising: a voltage stabilizer, a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency synthesizer. The output end of the voltage stabilizer is used to receive a signal to be processed, the output end of the voltage stabilizer is connected to the first input end of the phase detector, the output end of the phase detector is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected to the input end of the frequency synthesizer, and the output end of the frequency synthesizer is connected to the second input end of the phase detector; the frequency synthesizer comprises: a frequency control module, a DA conversion module, an amplification module, a limiting module, a filtering module, and a human-computer interaction module. The input end of the frequency control module is the input end of the frequency synthesizer, the first output end of the frequency control module is connected to the input end of the DA conversion module, the output end IOUT1 of the DA conversion module is connected to the input end of the amplification module, the output end of the amplification module is connected to the input end of the limiting module, the output end of the limiting module is connected to the input end of the filtering module, the output end of the filtering module is the output end of the frequency synthesizer, and the output end of the human-computer interaction module is connected to the input end of the frequency control module.
[0025] The amplification module includes an amplifier U3, a resistor R4, and a feedback resistor group unit. The first end of resistor R4 serves as the input of the amplification module. The second end of resistor R4 is connected to the inverting input of amplifier U3 and the first end of the feedback resistor group unit. The second end of the feedback resistor group unit is connected to the output of amplifier U3. The output of amplifier U3 serves as the output of the amplification module. The non-inverting input of amplifier U3 is grounded. This amplifies an analog signal with a specified frequency to a specified amplitude.
[0026] The amplitude limiting module includes: an amplitude limiting main circuit unit, an upper amplitude limiting unit, an upper resistor group unit, a lower amplitude limiting unit, and a lower resistor group unit. The input end of the amplitude limiting main circuit unit is used to connect to the output end of the amplification module, and the output end of the amplitude limiting main circuit unit is the output end of the amplitude limiting module. The high voltage end of the upper resistor group unit and the high voltage end of the lower resistor group unit are both connected to the output end of the first DC power supply, and the low voltage end of the upper resistor group unit and the low voltage end of the lower resistor group unit are both connected to the output end of the second DC power supply. The voltage output end of the upper resistor group unit is connected to the reference voltage input end of the upper amplitude limiting unit, and the output end of the upper amplitude limiting unit is connected to the output end of the amplitude limiting main circuit unit; the voltage output end of the lower resistor group unit is connected to the reference voltage input end of the lower amplitude limiting unit, and the output end of the lower amplitude limiting unit is connected to the output end of the amplitude limiting main circuit unit. The upper amplitude limiting unit realizes the formation of the analog signal after the specified frequency passes through the limiting band, and limits the upper amplitude of the square wave signal according to the upper voltage output of the upper resistor group unit, and limits the lower amplitude of the square wave signal according to the lower voltage output of the lower resistor group unit.
[0027] The feedback resistor group unit, the upper resistor group unit, and the lower resistor group unit are each provided with a controllable switch. All controllable switches within the feedback resistor group unit, the upper resistor group unit, and the lower resistor group unit operate under a single controlled control, the control end of which is connected to the second output end of the frequency control module. This achieves control over the amplification ratio of the amplifier module by controlling the resistance connected to the feedback resistor group unit. Controlling the output position of the upper resistor group unit controls the upper voltage, and thus the upper amplitude of the square wave signal. Controlling the output position of the lower resistor group unit controls the lower voltage, and thus the lower amplitude of the square wave signal, thereby enabling selection of a square wave signal with a desired amplitude as needed. All controllable switches operate under a single controlled control, and during control, the outputs of the feedback resistor group unit, the upper resistor group unit, and the lower resistor group unit are specified in two situations.
[0028] All controllable switches and controlled devices are in a relay. The controllable switches include: a first single-pole double-throw switch SW1, a second single-pole double-throw switch SW2, and a third single-pole double-throw switch SW3. The first single-pole double-throw switch SW1 is set in the feedback resistor group unit, the second single-pole double-throw switch SW2 is set in the upper resistor group unit, and the third single-pole double-throw switch SW3 is set in the lower resistor group unit.
[0029] The feedback resistor group unit includes resistors R1, R2, and R3. The first ends of resistors R1, R2, and R3 are connected to form the first end of the feedback resistor group unit. The second end of resistor R2 is connected to the first movable end of a first single-pole double-throw switch SW1. The second end of resistor R3 is connected to the second movable end of the first single-pole double-throw switch SW1. The fixed end of the first single-pole double-throw switch SW1 and the second end of resistor R1 are connected to form the second end of the feedback resistor group unit. Switching the first single-pole double-throw switch SW1 allows resistor R2 or R3 to be connected to the feedback resistor group unit, connecting resistor R1 in parallel with resistor R2 or R3, thereby adjusting the resistance value of the feedback resistor group unit and thus adjusting the amplification ratio.
[0030] The upper resistor group unit includes resistors R6, R7, R8, and R9. The first end of resistor R6 serves as the high-voltage terminal VDD1 of the upper resistor group unit. The second end of resistor R6 is connected to the first end of resistor R8 via resistor R7. The second end of resistor R8 is connected to one end of resistor R9. The other end of resistor R9 serves as the low-voltage terminal -VDD1 of the upper resistor group unit. The second end of resistor R6 is connected to the first movable terminal of a second single-pole double-throw switch SW2. The first end of resistor R8 is connected to the second movable terminal of the second single-pole double-throw switch SW2. The fixed terminal of the second single-pole double-throw switch SW2 serves as the voltage output terminal of the upper resistor group unit. The second single-pole double-throw switch SW2 can be used to adjust the connection to different contacts, thereby adjusting the upper voltage. The upper voltage corresponds to the upper amplitude of the square wave signal.
[0031] The lower resistor group unit includes resistors R10, R11, R12, and R13. The first end of resistor R10 serves as the high-voltage terminal VDD1 of the lower resistor group unit. The second end of resistor R10 is connected to the first end of resistor R12 via resistor R11. The second end of resistor R12 is connected to the first end of resistor R13. The second end of resistor R13 serves as the low-voltage terminal -VDD1 of the lower resistor group unit. The second end of resistor R10 is connected to the first movable terminal of a third single-pole double-throw switch SW3. The first end of resistor R12 is connected to the second movable terminal of the third single-pole double-throw switch SW3. The fixed terminal of the third single-pole double-throw switch SW3 serves as the voltage output terminal of the lower resistor group unit. The third single-pole double-throw switch SW3 can be used to adjust the connection to different contacts, thereby adjusting the lower voltage. The lower voltage corresponds to the lower amplitude of the square wave signal.
[0032] The limiting main circuit unit includes: an amplifier U4 and a resistor R5. The non-inverting input end of the amplifier U4 is the input end of the limiting main circuit unit, the inverting input end of the amplifier U4 is connected to the output end of the amplifier U4, the output end of the amplifier U4 is connected to one end of the resistor R5, and the other end of the resistor R5 is the output end of the limiting main circuit unit.
[0033] The upper limit amplitude unit includes: an amplifier U5 and a diode D1, the non-inverting input terminal of the amplifier U5 is the reference voltage input terminal of the upper limit amplitude unit, the inverting output terminal of the amplifier U5 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the output terminal of the amplifier U5, and the anode of the diode D1 is the output terminal of the upper limit amplitude unit;
[0034] The lower limiter unit includes: an amplifier U6 and a diode D2. The non-inverting input terminal of the amplifier U6 is the reference voltage input terminal of the lower limiter unit. The inverting output terminal of the amplifier U6 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the output terminal of the amplifier U6. The anode of the diode D2 is the output terminal of the lower limiter unit.
[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model and are not limiting. Although the utility model is described in detail with reference to the preferred embodiments, ordinary technicians in this field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.
Claims
1. Frequency adjustable DDS and PLL phase-locked loop circuit, including: A voltage stabilizer, a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency synthesizer, wherein the output of the voltage stabilizer is used to receive a signal to be processed, the output of the voltage stabilizer is connected to a first input of the phase detector, the output of the phase detector is connected to an input of the loop filter, the output of the loop filter is connected to an input of the voltage-controlled oscillator, the output of the voltage-controlled oscillator is connected to an input of the frequency synthesizer, and the output of the frequency synthesizer is connected to a second input of the phase detector; characterized in that The frequency synthesizer includes: a frequency control module, a DA conversion module, an amplifying module, a limiting module, a filtering module and a human-computer interaction module. The input end of the frequency control module is the input end of the frequency synthesizer, the first output end group of the frequency control module is connected to the input end of the DA conversion module, the output end of the DA conversion module is connected to the input end of the amplifying module, the output end of the amplifying module is connected to the input end of the limiting module, the output end of the limiting module is connected to the input end of the filtering module, the output end of the filtering module is the output end of the frequency synthesizer, and the output end of the human-computer interaction module is connected to the input end of the frequency control module.
2. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 1, characterized in that: The amplification module includes: an amplifier U3, a resistor R4 and a feedback resistor group unit. The first end of the resistor R4 is the input end of the amplification module, the second end of the resistor R4 is connected to the inverting input end of the amplifier U3 and the first end of the feedback resistor group unit, the second end of the feedback resistor group unit is connected to the output end of the amplifier U3, the output end of the amplifier U3 is the output end of the amplification module, and the non-inverting input end of the amplifier U3 is grounded.
3. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 2, characterized in that: The limiting module includes: a limiting main circuit unit, an upper limiting unit, an upper resistor group unit, a lower limiting unit and a lower resistor group unit. The input end of the limiting main circuit unit is used to connect to the output end of the amplification module. The output end of the limiting main circuit unit is the output end of the limiting module. The high-voltage end of the upper resistor group unit and the high-voltage end of the lower resistor group unit are both connected to the output end of the first DC power supply. The low-voltage end of the upper resistor group unit and the low-voltage end of the lower resistor group unit are both connected to the output end of the second DC power supply. The voltage output end of the upper resistor group unit is connected to the reference voltage input end of the upper limiting unit, and the output end of the upper limiting unit is connected to the output end of the limiting main circuit unit; the voltage output end of the lower resistor group unit is connected to the reference voltage input end of the lower limiting unit, and the output end of the lower limiting unit is connected to the output end of the limiting main circuit unit.
4. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 3, characterized in that: The feedback resistor group unit, the upper resistor group unit and the lower resistor group unit are each provided with a controllable switch. All controllable switches in the feedback resistor group unit, the upper resistor group unit and the lower resistor group unit operate under a controlled device, and the control end of the controlled device is connected to the second output end of the frequency control module.
5. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 4, characterized in that: All controllable switches and controlled devices are in a relay. The controllable switches include: a first single-pole double-throw switch SW1, a second single-pole double-throw switch SW2, and a third single-pole double-throw switch SW3. The first single-pole double-throw switch SW1 is set in the feedback resistor group unit, the second single-pole double-throw switch SW2 is set in the upper resistor group unit, and the third single-pole double-throw switch SW3 is set in the lower resistor group unit.
6. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 5, characterized in that: The feedback resistor group unit includes: a resistor R1, a resistor R2, and a resistor R3. The first end of the resistor R1, the first end of the resistor R2, and the first end of the resistor R3 are connected to form a first end of the feedback resistor group unit. The second end of the resistor R2 is connected to the first movable end of the first single-pole double-throw switch SW1. The second end of the resistor R3 is connected to the second movable end of the first single-pole double-throw switch SW1. The fixed end of the first single-pole double-throw switch SW1 and the second end of the resistor R1 are connected to form the second end of the feedback resistor group unit.
7. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 6, characterized in that: The upper resistor group unit includes: resistor R6, resistor R7, resistor R8 and resistor R9. The first end of resistor R6 is the high-voltage end of the upper resistor group unit, the second end of resistor R6 is connected to the first end of resistor R8 through resistor R7, the second end of resistor R8 is connected to one end of resistor R9, and the other end of resistor R9 is the low-voltage end of the upper resistor group unit. The second end of resistor R6 is connected to the first moving end of the second single-pole double-throw switch SW2, the first end of resistor R8 is connected to the second moving end of the second single-pole double-throw switch SW2, and the fixed end of the second single-pole double-throw switch SW2 is the voltage output end of the upper resistor group unit.
8. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 7, characterized in that: The lower resistor group unit includes: resistor R10, resistor R11, resistor R12 and resistor R13. The first end of resistor R10 is the high-voltage end of the lower resistor group unit, the second end of resistor R10 is connected to the first end of resistor R12 through resistor R11, the second end of resistor R12 is connected to the first end of resistor R13, the second end of resistor R13 is the low-voltage end of the lower resistor group unit, the second end of resistor R10 is connected to the first moving end of the third single-pole double-throw switch SW3, the first end of resistor R12 is connected to the second moving end of the third single-pole double-throw switch SW3, and the fixed end of the third single-pole double-throw switch SW3 is the voltage output end of the lower resistor group unit.
9. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 8, characterized in that: The limiting main circuit unit includes: an amplifier U4 and a resistor R5. The non-inverting input end of the amplifier U4 is the input end of the limiting main circuit unit, the inverting input end of the amplifier U4 is connected to the output end of the amplifier U4, the output end of the amplifier U4 is connected to one end of the resistor R5, and the other end of the resistor R5 is the output end of the limiting main circuit unit.
10. The frequency adjustable DDS and PLL phase-locked loop circuit according to claim 9, characterized in that: The upper limit amplitude unit includes: an amplifier U5 and a diode D1, the non-inverting input terminal of the amplifier U5 is the reference voltage input terminal of the upper limit amplitude unit, the inverting output terminal of the amplifier U5 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the output terminal of the amplifier U5, and the anode of the diode D1 is the output terminal of the upper limit amplitude unit; The lower limiter unit includes: an amplifier U6 and a diode D2. The non-inverting input terminal of the amplifier U6 is the reference voltage input terminal of the lower limiter unit. The inverting output terminal of the amplifier U6 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the output terminal of the amplifier U6. The anode of the diode D2 is the output terminal of the lower limiter unit.