Lateral bipolar junction transistor and circuit thereof

Abstract

A lateral bipolar junction transistor (BJT) includes a semiconductor substrate, an insulator region disposed on the semiconductor substrate, and a well region including a well semiconductor of a first conductivity type disposed over the insulator region. An emitter region having a second conductivity type is disposed in the well region, and at least one collector region having the second conductivity type is disposed in the well region. A T-shaped, Pi-shaped, or H-shaped gate and a gate oxide layer include a gate portion extending between the emitter region and one or more collector regions, with a base region disposed below the gate portion. In other embodiments, a metal oxide semiconductor (MOS) transistor-based circuit is similar to employing a compact Pi-shaped or H-shaped gate and a gate oxide layer.

Description

Technical Field

[0001] The embodiment of the utility model relates to a lateral bipolar junction transistor element and a circuit thereof. Background Art

[0002] The following relates to semiconductors, devices, lateral bipolar junction transistor (BJT) devices, metal oxide semiconductor (MOS) devices, methods of forming the aforementioned devices, and circuits such as thermal sensors and bandgap reference circuits using the same. Utility Model Content

[0003] An embodiment of the present invention provides a lateral bipolar junction transistor comprising: a semiconductor substrate; an insulator region arranged on the semiconductor substrate; a well region comprising a well semiconductor of a first conductivity type arranged above the insulator region; an emitter region of a second conductivity type arranged in the well region; a first collector region of the second conductivity type and a second collector region of the second conductivity type arranged in the well region; a Pi-shaped or H-shaped gate and a gate oxide layer, the Pi-shaped or H-shaped gate comprising a first gate portion extending between the emitter region and the first collector region, a second gate portion parallel to the first gate portion and extending between the emitter region and the second collector region, and a first connecting gate portion transverse to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion; and a first base region arranged below the first gate portion, and a second base region arranged below the second gate portion.

[0004] An embodiment of the present invention provides a circuit including: a plurality of metal oxide semiconductor (MOS) transistors, each MOS transistor including: a drain region; a first source region and a second source region; and a Pi or H-shaped gate and a gate oxide layer, the Pi or H-shaped gate including a first gate portion extending between the drain region and the first source region, a second gate portion parallel to the first gate portion and extending between the drain region and the second source region, and a first connecting gate portion transverse to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 The figure schematically shows a side cross-sectional view of a lateral bipolar junction transistor device according to an embodiment.

[0007] Figures 2A-2DVarious aspects of a lateral bipolar junction transistor device including a Pi-shaped gate are schematically shown. Figure 2A shows a top view, Figure 2B Shown Figure 2A Sectional view AA, Figure 2C Shown Figure 2A The cross-sectional view BB of Figure 2D Shown according to Figure 2A Another cross-sectional view BB of another embodiment of a lateral bipolar junction transistor device is shown.

[0008] Figure 3A-3C A top view of a lateral bipolar junction transistor component according to various embodiments is schematically shown. Figure 3A A lateral bipolar junction transistor element including a T-shaped gate and a gate oxide layer is shown; Figure 3B A lateral bipolar junction transistor element including a Pi-shaped gate is shown; Figure 3C A lateral bipolar junction transistor element including an H-shaped gate is shown.

[0009] Figure 4 A lateral bipolar junction transistor element comprising a Pi-shaped gate and a trench gate contact arrangement is shown.

[0010] Figure 5A and Figure 5B An example circuit (BJT thermal sensor) comprising a compact BJT layout with a common base connection is schematically shown.

[0011] Figure 6A and Figure 6B An example circuit (1:8 BJT bandgap reference) including a compact BJT layout with Pi- and H-shaped gates and gate oxide layers and a common base is schematically shown.

[0012] Figure 7A and Figure 7B An example circuit comprising a compact MOS layout with a Pi-shaped gate and gate oxide layer and a common base is schematically shown (flipped gate bandgap reference). DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the disclosure may reuse component numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] Bipolar junction transistors (BJTs) are widely used in analog, digital, and mixed analog / digital integrated circuits. BJTs can be categorized as NPN BJTs (NBJTs) and PNP BJTs (PBJTs). An NPN BJT is an NPN transistor consisting of doped regions: an n-type emitter E, a p-type base B, and an n-type collector C. Conversely, a PNP BJT is a PNP transistor with a p-type emitter E, an n-type base B, and a p-type collector. To improve emitter-emitter efficiency, in some designs, the emitter E is surrounded by the base B and collector C.

[0016] The traditional BJT layout is a vertical design. A vertical BJT uses a vertical structure, such as that formed by double diffusion. This type of transistor is sometimes called a substrate transistor.

[0017] Traditional methods for forming vertical BJT devices are limited by the thickness of the thin silicon body of silicon-on-insulator (SOI) wafers. For example, in some SOI wafers, the silicon layer is less than 300 nanometers thick, which can make vertical BJT fabrication difficult or impossible. In such cases, a lateral BJT design can be employed, in which the base material (e.g., the silicon layer of an SOI wafer for an NPN BJT design) is p-type, while the emitter and collector regions are formed by diffusion or implantation of n-type dopants into the p-type base layer. In a lateral BJT design, the emitter and collector regions of the BJT are laterally spaced apart. However, fabricating compact lateral BJTs is challenging. Lateral designs inherently occupy a larger area. Furthermore, there can be misalignment between the N and P implants, which leads to variations in defining the BJT base dimensions, limiting the practically achievable critical dimensions of these device features and / or requiring the use of more complex processes, such as self-aligned techniques. In addition, the alignment of emitter and collector regions as well as shallow trench isolation (STI) and resist protection oxide (RPO) processes pose further challenges to miniaturization.

[0018] In various embodiments disclosed herein, a lateral BJT fabrication method is disclosed that facilitates compact lateral BJT devices and compact BJT arrays, and provides reduced gate resistance (Rg) and base resistance (Rb). For example, in one configuration, the base of the BJT is located below the gate, rather than laterally offset from the gate. In this method, a portion of the depletion region below the gate constitutes the base region of the BJT.

[0019] In another approach, the layout of the BJT is designed to be symmetrical to reduce Rg and Rb and reduce variability between BJT elements. For example, the gate of the BJT may have a T-shape, a Pi-shape, or an H-shape. As an example, the BJT may have collector regions symmetrically arranged on opposite sides of a central emitter region. The Pi-shaped gate has a first gate portion extending between the emitter region and the first collector region, a second gate portion parallel to the first gate portion and extending between the emitter region and the second collector region, and a first connecting gate portion transverse to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion. The gate connection made by the connecting gate portion provides a reduced gate resistance (Rg). In addition, in combination with the state of the base located below the gate, the base line connected to the base below the first gate portion and the second gate portion similarly provides a reduced base resistance (Rb).

[0020] In the H-shaped gate variant, the Pi-shaped gate is modified to further include a second connecting gate portion that is arranged parallel to the first connecting gate portion and further connects the first gate portion and the second gate portion, and the emitter region and the first and second collector regions are disposed between the first and second connecting gate portions. This provides further symmetry and increases the contact area between the gate (thus further reducing Rg) and the base (thus further reducing Rb).

[0021] In BJT-based circuits, these compact BTJ layouts can be synergistically combined to reduce circuit layout area. For example, connecting gate portions can be used to provide compact BJT-BJT interconnects for common sub-circuit elements, such as a BJT with a common base-collector connection or a pair of BJTs with a common base. In this case, the first (and optionally second) connecting gate portions and the corresponding underlying base regions can facilitate the compact formation of these interconnects, for example by butting the bases of mirrored BJT elements.

[0022] Although primarily described with respect to lateral BJT devices, in further embodiments disclosed herein, metal oxide semiconductor (MOS) field effect transistor (FET) devices employ similar compact layout designs, for example, including T-shaped, Pi-shaped, or H-shaped gates, and such MOSFET layouts may be similarly utilized to reduce circuit layout area and / or lower device resistance.

[0023] Another issue associated with conventional BJT circuits (e.g., bandgap reference circuits and thermal sensor circuits) is sensitivity to mismatch. According to some aspects of the present disclosure, mismatch sensitivity is improved by, for example, symmetrically arranging Pi or H-shaped gates. Furthermore, using a multi-cross-coupling layout arrangement allows for reduced device size and increased operating current, thereby averaging process variations. Furthermore, butted bases of mirrored devices can reduce overall layout area.

[0024] A lateral bipolar junction transistor (BJT) is disclosed herein, including one or more T-shaped, Pi-shaped, and / or H-shaped gates, using materials such as polysilicon or high-k metals such as titanium nitride (TiN) or tantalum nitride (TaN). Furthermore, circuits including common base / body and mixed cross-coupled topology arrangements for flipped-gate MOS circuits are disclosed.

[0025] Further advantages / benefits of the present disclosure and embodiments described herein include, but are not limited to, providing tunable n-factor (ideality factor) of the BJT through additional gate terminals and flipped gate processing. Compact layout area reduces mismatch between paired components.

[0026] Reference Figure 1, shows a state of a lateral bipolar junction transistor device, which includes a base arranged below the gate to provide a more compact device.

[0027] As shown in the figure, the lateral bipolar junction transistor element is a gate lateral bipolar junction transistor, including a Si substrate 110, a buried oxide (i.e., BOX, such as SiO2) 120, an emitter region 130, a collector region 140, and a base region 150. The base region 150 is formed as a non-depleted or partially depleted portion of a body 151 including a depletion region. Optionally, a drain implant 152 is also included. The conductive gate region 160 is made of a high-K metal material such as polysilicon or titanium nitride (TiN) or tantalum nitride (TaN). Optional spacers 162, such as Si, can be used to form the gate 160. A gate oxide layer 161 is disposed below the gate region 160 and above the base region 150 and the body 151.

[0028] In a suitable manufacturing process, Figure 1 The BJT is an NPN BJT formed on a starting SOI wafer having a p-type silicon layer. The emitter and collector regions 130 and 140 are formed by dopant diffusion or dopant implantation of n-type dopants sufficient to convert the p-type silicon material in these regions 130 and 140 to n-type. Through appropriate design of the device's doping profile, the p-type material beneath gate 160 and gate oxide 161 is depleted, thereby forming body 151, except for a central region of undepleted or partially depleted p-type material. This central region forms the p-type base 150 of the NPN BJT beneath gate 160 and gate oxide 161. Notably, base 150 is undepleted or partially depleted in the unbiased or quiescent state of the NPN BJT. During operation of the NPN BJT, base 150 can become more fully depleted or even accumulated in response to an appropriate electrical bias on gate 160. Gate oxide 161 can be deposited by any suitable technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Gate oxide 161 can be, for example, silicon dioxide (SiO2) or a high-k dielectric material. Gate 160 is formed on gate oxide 161 by any suitable deposition technique for polysilicon, TiN, TaN, or other selected gate materials (e.g., CVD, etc.).

[0029] Figure 1 The fabrication of the BJT is similar to that of the PNP BJT, except that the starting SOI wafer suitably has an n-type silicon layer, and the emitter and collector regions 130 and 140 are formed by dopant diffusion or dopant implantation of p-type dopants sufficient to convert the n-type silicon material in these regions 130 and 140 to p-type.

[0030] Advantageously, placing base 150 below gate 160 and gate oxide 161 provides a more compact BJT and can also reduce device resistance. Forming base 150 below gate 160 can generally be combined with any lateral BJT design to achieve these advantages. In some illustrative embodiments, this aspect is combined with the compact BJT layout disclosed herein to achieve synergistic advantages.

[0031] As further described below, the lateral BJT base 150 formed by the non-depleted body portion 150 below the polysilicon gate 160 is used in conjunction with a T-gate, a Pi-gate, or an H-gate.

[0032] In addition to adjusting the implantation process, applying a negative Vg bias to the polysilicon gate (accumulated in NMOS) can be used as a knob to adjust the device's n-factor (real factor). Alternatively, by swapping the N / PMOS polysilicon gate pre-dopants or the flipped gate process of the metal gate stack, the surface potential of the bulk Si (labeled Tbody) can be changed, affecting the n-factor when a negative Vg bias is applied. According to one embodiment, the thickness of Tbody (Si) is 50nm to 200nm; the thickness of Tbox is 1μm to 3μm.

[0033] It should be understood that reference Figure 1 The gate lateral BJT shown and described is provided to illustrate a cross-sectional view of a gate BJT according to the present disclosure, and may, in some embodiments, incorporate a T-shaped polysilicon gate BJT, a Pi-shaped polysilicon gate BJT, and / or an H-shaped polysilicon gate BJT, as further described below. ( FIG. 2 shows a Pi-shaped gate BJT, Figure 3A-3C A T-gate BJT, a Pi-gate BJT, and an H-gate BJT are further shown).

[0034] Reference Figures 2A-2D , showing various aspects of a lateral bipolar junction transistor device including a Pi-shaped gate and a gate oxide layer. Figure 2A shows a top view, Figure 2B Shown Figure 2A Sectional view AA.

[0035] like Figure 2A As shown, the lateral bipolar junction transistor element includes a Pi-shaped gate 260 (while the gate oxide layer below is not visible in the top view) and includes a dual BJT configuration. The Pi-shaped gate can reduce Rb (base resistance) and the resistance of the emitter and collector pickup metal wiring. It can also reduce the impact of process non-uniformity by providing a compact and symmetrical layout. The lateral bipolar junction transistor includes a single emitter region 130, a first collector region 140 and a second collector region 240, which use a metallization layer ( Figures 2A-2DThe base region 150 / 151 is disposed between the emitter region 130 and the first collector region 140, while the base region 250 / 251 (see FIG. Figure 2B ) is arranged between the emitter region 130 and the second collector region 240. The pickup of the base region for the electrical contacts 153 and 253 is realized as a p+ doped region 154 (also as Figure 2C and Figure 2D Other electrical contacts include collector contacts 143A, 143B, emitter contacts 133A, 133B, collector contacts 243A, 243B, and gate contacts 163A, 163B. Polysilicon or high-K metal isolation regions 180 and 190 are also provided (formed together with the polysilicon or high-K gate).

[0036] like Figure 2B As shown, it shows Figure 2A The cross-sectional view AA shown in FIG. 1 shows an NPN BJT, wherein the collector regions 140 and 240 are N+ doped, the emitter region 130 is N+ doped, the well is a P-type doped well, and also includes a P+ / PW base region, while the semiconductor substrate 110 in the example herein is a bulk P-type silicon substrate of an SOI wafer. Alternatively, the disclosed gate lateral BJT element can be configured as a PNP BJT, wherein the collector regions 140 and 240 are P+ doped, the emitter region 130 is P+ doped, and the well is an N-type doped well. A buried oxide (SiO2) 120 (BOX) layer of the SOI wafer is disposed below the P-type well layer. Gate oxide layers 161 and 261 are disposed below the Pi-shaped gate portion 260 / 261 between the gate regions 260A / 260B and the respective base regions 150 / 151 and 250 / 251. In some non-limiting illustrative examples, the thickness of gate oxide layers 161 and 261 is in a range of 2 nm to 10 nm. Gate oxide layer 181 is disposed between polysilicon member 180 and shallow trench isolation (STI) region 182, while gate oxide layer 191 is disposed between polysilicon member 190 and shallow trench isolation (STI) region 182.

[0037] Regarding the base regions 150 / 151 and 250 / 251, the base regions 150 / 151 include a non-depleted or partially depleted base region 150 and a bulk depleted region 151 (see Figure 1 ). The base 150 and the body 151 comprise the same material (silicon), but the base 150 is partially depleted. The body region 151 is partially or completely depleted in the unbiased or static state, but can be partially depleted or accumulated by applying a suitable Vg bias on the gate G.

[0038] According to one embodiment, layer 170 ( Figure 1 As shown in FIG. 1 , the silicide layer 170 is a metal (e.g., Co, Ti) and silicon silicide layer. In some embodiments, the silicide layer 170 is formed in a self-aligned manner to contact the emitter 130 and collector 140 below, for example, using a self-aligned silicide process. The drain implant 152 (e.g., Figure 1 shown) is a lightly doped drain (LDD) implant and is not necessary for an optimized BJT.

[0039] Reference Figure 2C , showing Figure 2A The cross-sectional view BB, and Figure 2D Shown according to Figure 2A Another alternative cross-sectional view BB of another embodiment of the lateral bipolar junction device is shown.

[0040] like Figure 2C As shown, in addition to the previous reference Figure 2A and Figure 2B In addition to the depicted area, a base extension region is also shown for providing a connection for the base contact 153 / 253. The base extension region includes a P+ region 154 within the P-well, which connects the base contact 153 / 253 to the corresponding base region 151 / 251. Figure 2D As shown, the base extension region includes a P-type region 155 and a P+ type region 154 within the P-well, which connects the base contacts 153 / 253 in series to the corresponding base regions 151 / 251.

[0041] As described above, a gate-lateral bipolar junction transistor (BJT) is provided. The gate-lateral BJT includes a semiconductor substrate, an insulator region disposed on the semiconductor substrate, and a well region having a first conductivity type disposed above the insulator region. An emitter region having a second conductivity type is also disposed in the well region, and a first collector region and a second collector region having the second conductivity type are disposed in the well region.

[0042] Pi-shaped (such as Figure 2A shown) or H-shaped (see Figure 3C ) The gate includes:

[0043] (a) a first gate portion 260A extending between the emitter region 130 and the first collector region 140,

[0044] (b) a second gate portion 260B extending parallel to the first gate portion and between the emitter region 130 and the second collector region 240 , and

[0045] (c) A (first) connecting gate portion 260C that is transverse to and connects the first gate portion and the second gate portion.

[0046] like Figure 1 As shown, the base region 150 is disposed below the first gate portion 260A and below the second gate portion 260B, such that the base 150 is located between the emitter 130 and the first collector 140, as shown in FIG. Figure 1 As shown, and is similarly located between the emitter 130 and the second collector 240 (due to the second gate portion 260B extending between the emitter region 130 and the second collector region 240).

[0047] With respect to the first and second base regions beneath the corresponding first and second gate portions 260A and 260B, the base region 150 includes a non-depleted or partially depleted portion 150 of the well semiconductor material beneath the gate portion, which is surrounded by a depleted portion 151 of the well semiconductor material. A base region extension laterally extends the first and second base regions to provide a first and second base region connection beyond the polysilicon / high-k metal gate overlying the top surfaces of the first and second base regions.

[0048] Figure 2A The Pi-shaped gate of the embodiment actually includes two BJTs: one is formed by the emitter 130, the first collector 140, and the first gate portion 260A extending between the emitter region 130 and the first collector region 140; the other is formed by the emitter 130, the second collector 240, and the second gate portion 260B extending between the emitter region 130 and the second collector region 240. However, in some applications, the BEOL process includes the interconnection of the two collectors 140 and 240 and the interconnection of the two base portions located below the corresponding first gate portion and second gate portion, so that Figure 2A The BJTs are electrically connected to form a single BJT at the circuit level. This approach provides a compact and symmetrical BJT design with long gate and base lines to reduce Rg and Rb, respectively.

[0049] Figure 3A 、 Figure 3B as well as Figure 3C Some other compact gate layouts are shown. Figure 3A A T-shaped gate is shown having an emitter 130, only a single collector 140, and a single gate portion 260A extending between the emitter region 130 and the single collector 140. (In practice, this corresponds to Figure 2A , but without the second collector 240 and the second gate portion 260B). Figure 3B Shown with Figure 2A The same Pi-gate BJT. In order to provide an H-shaped gate, such as Figure 3CAs shown, the gate includes a first gate portion 260A, a second gate portion 260B, and a first connecting gate portion 260C. It also includes a second connecting gate portion 260D that is aligned parallel to the first connecting gate portion 260C and further connects the first gate portion 260A and the second gate portion 260B. The emitter region 130, as well as the first and second collector regions 140 and 240, are disposed between the first connecting gate portion 260C and the second connecting gate portion 260D. The third and fourth base region extensions laterally extend the respective first and second base regions to provide base region connections beyond the H-shaped polysilicon / high-K metal gate that covers the top surfaces of the first and second base regions.

[0050] According to a non-limiting and more specific illustrative example of an NPN BJT embodiment, the semiconductor substrate is a silicon (Si) substrate; the insulator region is silicon dioxide; the well region is a P-type well; the emitter region is N+ doped; and the first and second collector regions are N+ doped. According to a non-limiting and more specific illustrative example of a PNP BJT embodiment, the semiconductor substrate is a silicon (Si) substrate; the insulator region is silicon dioxide; the well region is an N-type well; the emitter region is P+ doped; and the first and second collector regions are P+ doped. It is noted that although in the illustrative example, the lateral BJT is formed in the silicon layer of the SOI wafer, it is contemplated that the lateral BJT may alternatively be formed on the surface of a bulk silicon wafer or in an epitaxially deposited silicon layer, etc.

[0051] Although the detailed description thus far and below focuses on Pi- and H-gate dual BJTs, it should be understood that Figure 3A T-shaped gate single BJTs are also within the scope of the present disclosure. Specifically, the gate lateral bipolar junction transistor includes a semiconductor substrate; an insulator region disposed on the semiconductor substrate; and a well region of a first conductivity type disposed above the insulator region. An emitter region of a second conductivity type is disposed in the well region, and a single collector region of the second conductivity type is also disposed in the well region.

[0052] A base region equivalent to that described with reference to the Pi- and H-gate BJTs is disposed in the well region, the base region being located between the emitter and collector regions. A single, continuous T-shaped polysilicon gate and gate oxide layer overlie the top surface of the base region. A base region extension region laterally extends the base region to provide a base region connection beyond the T-shaped polysilicon gate overlying the top surface of the base region.

[0053] Additional features of the T-gate BJT include, but are not limited to, a first isolation region laterally adjacent to the base region extension; a second isolation region laterally adjacent to the well region and located at a second end of the well region opposite the first end of the well region; at least one electrical contact extending from the emitter region to a top surface of the emitter region; at least one electrical contact extending from the collector region to a top surface of the collector region; at least one electrical contact extending from the base region extension to a top surface of the base region extension; and at least one electrical contact extending from the T-shaped polysilicon gate to a top surface of the T-shaped polysilicon gate.

[0054] Figure 4 A lateral bipolar junction transistor element is shown, comprising a Pi-shaped gate (also shown as Figure 2A and Figure 3B As shown). Gate 260 has Figure 4 The gate length Lg shown is, in this example, the gate length between the emitter 130 and the second collector 240. The gate length Lg between the emitter 130 and the first collector 140 may also be appropriately designated as Lg. As previously mentioned, the gate 260 and the gate contact (e.g. Figure 2A The gate contacts 163A and 163B shown in FIG. Figure 4 , a side cross-sectional view illustrates a trench gate contact arrangement according to some embodiments, which is used to provide a more compact layout area.

[0055] The spacer slits 462 are formed by: (i) SiNx (the remaining spacers 162, see Figure 1 ) and SiOx (etching spacers), and (ii) multi-stage etching power (high ion bombardment: uniform etching of the top of the spacer, lower ion bombardment: gradient etch rate of the top and corners / sidewalls of the spacer). The result is a trench gate contact arrangement including trench gate copper contacts 463A / B, which are electrically connected to the base region 251 through the Pi-shaped gate region 260 and the gate oxide layer 261. Figure 4 The trench gate advantageously facilitates the fabrication of more compact BJT components.

[0056] Reference Figure 5A and Figure 5B , shows an example circuit (BJT thermal sensor) including a compact BJT layout with a common base connection. The example circuit is a BJT thermal sensor circuit.

[0057] like Figure 5BAs shown, the thermal sensor circuit includes a BJT pair 501 and 502 having two branches 510 and 520, each including a corresponding current source 512 and 522, and transistors 501 and 502 connected in series with the current sources 512 and 522. The base and collector of each of the transistors 501 and 502 are connected to each other and to a common reference node, such as a ground reference. The emitters of the transistors 501 and 502 are connected to the corresponding current sources 512 and 522, respectively.

[0058] An amplifier 530 with a gain α is connected to nodes 516 and 526 (eg, the emitters of transistors 501 and 502). Specifically, two input terminals of the amplifier 530 are connected to the respective nodes 516 and 526 to receive a differential signal ΔV. be , which is the base-emitter voltage V at the emitter of transistor 501 BE and the base-emitter voltage V at the emitter of transistor 502 BE The base-emitter voltage VBE of transistors 501 and 502 is complementary to the absolute temperature (CTAT) voltage, and the difference between the two base-emitter voltages ΔV be The voltage proportional to absolute temperature (PTAT) is added by adder 540 to complete the circuit and provide a reference voltage V ref The temperature can then be measured using an analog-to-digital (A / D) converter 550 to obtain a ratio μ, which can be converted to a temperature value, such as degrees Celsius.

[0059] For ideal modules in BJT-pair simulation, use the following formula:

[0060]

[0061] Regarding transistors 501 and 502, according to embodiments of the present disclosure, Figure 5A A compact BJT layout is shown including a top row of lateral bipolar junction transistor elements 502A and 501A with Pi-shaped gates 260 and a bottom row of lateral bipolar junction transistor elements 501B and 502B with Pi-shaped gates 260. The emitters of the lateral bipolar junction transistor elements 502A and 502B are electrically connected to each other to provide Figure 5B Transistor 502 is shown in the BJT thermal circuit shown. The emitters of lateral bipolar junction transistor elements 501A and 501B are electrically connected to each other to provide Figure 5BTransistor 501 is shown in the BJT thermal circuit shown. Common base metallization layer 505 electrically connects the base and collector of transistors 501 and 502. Widths W1 and W2 can be scaled independently, and the components shown provide a compact layout by using a common base node for both mirrored components. The gate terminal (G) is an independent terminal controlled by a DC bias source (not shown).

[0062] Reference Figure 6A and Figure 6B , shows an example circuit (1:8 BJT bandgap voltage reference circuit) that includes a compact BJT layout with Pi-shaped and H-shaped gates, a gate oxide layer, and a common base connection.

[0063] A bandgap voltage reference is a temperature-independent voltage reference circuit used in integrated circuits. It generates a fixed (constant) voltage that is unaffected by power supply variations, temperature changes, and component circuit loading.

[0064] Reference Figure 6B The base-emitter voltage of a bipolar transistor typically exhibits a negative temperature coefficient. The difference between the base-emitter voltages of two bipolar transistors 601 and 602 operating together with unequal current densities exhibits a positive temperature coefficient. Therefore, a bandgap voltage generator can be designed by connecting two bipolar transistors 601 and 602 in parallel with unequal emitter current densities IE1 and IEX and ensuring that the positive and negative temperature coefficients cancel each other out. Other components of the circuit include resistors R1, R2, and R3, and amplifier A1.

[0065] like Figure 6B As shown, BJTs 601 and 602 are provided by a compact BJT layout arrangement using Pi-shaped gates and H-shaped gates and a common base connection. The BJT layout arrangement includes Figure 6B 1:8Q1 / Q2 in the bandgap reference circuit.

[0066] like Figure 6AAs shown, the compact BJT layout arrangement includes a top outer row of lateral BJT elements 602A, 602B, and 602C, each including a Pi-shaped gate 260; a bottom outer row of lateral BJT elements 602F, 602G, and 602H, each including a Pi-shaped gate 260; and a center column of lateral BJT elements 602D, 601A, and 602E, each including an H-shaped gate 360. A common base metallization layer 605 electrically connects the bases and collectors of transistors 602A-H and 601A. The compact BJT layout arrangement provides a multi-cross couple layout of paired elements for mismatch-sensitive circuits. The gate terminals (G) of Q1 (601A) and Q2 (602A-H) are each controlled by a DC bias source (not shown) in the circuit.

[0067] Previous embodiments have employed lateral BJTs, whose gate layout advantageously facilitates compact BJT devices and BJT arrays and reduces device resistance (e.g., reducing Rg and Rb). However, the disclosed gate layouts (e.g., Pi-gate or H-gate) can also be effectively used for other types of gated transistors, such as metal oxide semiconductor (MOS) field effect transistors (FETs).

[0068] Reference Figure 7A and Figure 7B , shows an example MOS circuit (flipped gate bandgap voltage reference circuit) that includes a compact MOSFET layout with a Pi-shaped gate, a gate oxide layer, and a common base connection. The circuit generates a bandgap reference voltage VREF. The circuit includes a current source I1, FG nMOS M1701, nMOS M2702, a current source I2, and nMOS M3.

[0069] Regarding transistors 701 and 702, according to one embodiment of the present disclosure, Figure 7AA compact MOSFET layout is shown, including a top row of MOSFET transistor elements 702A (nMOS) with Pi-shaped gates 260 and MOSFET transistor elements 701A (FGnMOS flipped gate) with Pi-shaped gates 760, and a bottom row of MOS transistor elements 701B (FGnMOS flipped gate) with Pi-shaped gates 760 and MOSFET transistor elements 702B (nMOS) with Pi-shaped gates 260. Each MOS2 transistor includes a drain region 730, a first source region 741, and a second source region 742, as well as a Pi-shaped gate and a gate oxide layer. The Pi-shaped gate includes a first gate portion 260A extending between the drain region 730 and the first source region 741, a second gate portion 260B extending parallel to the first gate portion 260A and between the drain region 730 and the second source region 742, and a first connecting gate portion 260C extending transversely to and connecting the first and second gate portions. The flip gate process of exchanging the N / PMOS polysilicon gate pre-dopants or metal gate stack can change the surface potential of the bulk Si and affect the n-factor when a negative Vg bias is applied. The source and base of the MOSFET transistor elements 701A, 701B, 702A and 702B are electrically connected to each other using a metallization layer 705 to provide Figure 7B The flipped gate bandgap voltage reference circuit shown is for transistors 702 and 701.

[0070] Figure 7B The circuit is as follows to provide a bandgap reference VREF. Two MOS transistors 701 and 702 are connected in a common gate configuration, i.e. they have a common gate voltage V G Considering MOS M1, it can be seen that the common gate voltage V G It can be written as V G =V SS +V GS,1 , where V GS,1 is the gate-source voltage of MOS M1. Considering MOS M2, it can be seen that this common gate voltage V G It can be written as V G = VREF + V GS,2 , where V GS,2 is the gate-source voltage of MOS M2. Equating the right-hand side expressions of the common gate voltage VG given by these two equations gives V SS +V GS,1 = VREF + V GS,2 , can be rearranged to produce the reference voltage:

[0071] VREF=V SS +(V GS，1 -VGS，2 )=V SS +ΔV GS (2)

[0072] where ΔV GS =V GS，1 -V GS，2 If V SS As the circuit is grounded, V SS =0, then the output reference voltage VREF=ΔV GS The different transistor types (FGnMOS 701 and nMOS 702) result in different threshold voltages of the two transistors 701 and 702, making ΔVGS non-zero.

[0073] In the following, some further embodiments are described.

[0074] In a non-limiting illustrative embodiment, a lateral bipolar junction transistor (BJT) is disclosed. The lateral bipolar junction transistor (BJT) includes a semiconductor substrate; an insulator region disposed on the semiconductor substrate; a well region including a well semiconductor of a first conductivity type disposed above the insulator region; an emitter region of a second conductivity type disposed in the well region; a first collector region of the second conductivity type and a second collector region of the second conductivity type disposed in the well region; a Pi-shaped or H-shaped gate and a gate oxide layer, the Pi-shaped or H-shaped gate including a first gate portion extending between the emitter region and the first collector region, a second gate portion extending parallel to the first gate portion and between the emitter region and the second collector region, and a first connecting gate portion extending transversely to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion; and a first base region disposed below the first gate portion, and a second base region disposed below the second gate portion.

[0075] In a non-limiting illustrative embodiment, a circuit is disclosed. The circuit includes a plurality of MOS transistors. Each MOS transistor includes: a semiconductor substrate; an insulator region disposed on the semiconductor substrate; a well region including a well semiconductor of a first conductivity type disposed above the insulator region; a drain region of a second conductivity type disposed in the well region; a first source region of the second conductivity type and a second source region of the second conductivity type disposed in the well region; a Pi-shaped gate and a gate oxide layer, the Pi-shaped gate including a first gate portion extending between the drain region and the first source region, a second gate portion extending parallel to the first gate portion and between the drain region and the second source region, and a first connecting gate portion transverse to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion; and a first base region disposed below the first gate portion, and a second base region disposed below the second gate portion.

[0076] In a non-limiting illustrative embodiment, a method for forming a lateral bipolar junction transistor is disclosed. The method includes providing a semiconductor substrate; forming an insulator region on the semiconductor substrate; forming a well region containing a well semiconductor of a first conductivity type above the insulator region; forming an emitter region of a second conductivity type in the well region; forming a first collector region of the second conductivity type and a second collector region of the second conductivity type in the well region; forming a Pi-shaped or H-shaped gate and a gate oxide layer, the Pi-shaped or H-shaped gate including a first gate portion extending between the emitter region and the first collector region, a second gate portion extending parallel to the first gate portion and between the emitter region and the second collector region, and a first connecting gate portion extending transversely to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion; and forming a first base region below the first gate portion and a second base region below the second gate portion.

[0077] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and variations may be made to this document without departing from the spirit and scope of the present invention.

Claims

1. A lateral bipolar junction transistor, comprising: semiconductor substrates; An insulator region is provided on the semiconductor substrate; A well region including a well semiconductor of a first conductivity type is disposed above the insulator region; An emitter region having a second conductivity type is disposed in the well region; A first collector region having the second conductivity type and a second collector region having the second conductivity type are arranged in the well region; a Pi-shaped or H-shaped gate and a gate oxide layer, wherein the Pi-shaped or H-shaped gate includes a first gate portion extending between the emitter region and the first collector region, a second gate portion parallel to the first gate portion and extending between the emitter region and the second collector region, and a first connecting gate portion transverse to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion; as well as A first base region is disposed under the first gate portion, and a second base region is disposed under the second gate portion.

2. The lateral bipolar junction transistor according to claim 1, wherein: The Pi-shaped or H-shaped gate is an H-shaped gate, and the H-shaped gate further includes a second connecting gate portion arranged in parallel with the first connecting gate portion and further connecting the first gate portion and the second gate portion, and The emitter region, the first collector region, and the second collector region are arranged between the first connecting gate portion and the second connecting gate portion.

3. The lateral bipolar junction transistor according to claim 1, wherein: Also includes: At least one trench gate contact extends from the Pi-shaped or H-shaped gate to a top surface of the Pi-shaped or H-shaped gate.

4. The lateral bipolar junction transistor according to claim 1, wherein: Also includes: The metallization layer includes a conductive trace electrically connecting the first collector region and the second collector region to provide a single collector.

5. The lateral bipolar junction transistor according to claim 4, wherein: The conductive trace also electrically connects the first base region and the second base region to the single collector.

6. The lateral bipolar junction transistor according to claim 1, wherein: The semiconductor substrate is a silicon substrate; The insulator region is silicon dioxide; The well area is a P-type well; The emitter region is N+ doped; and The first collector region and the second collector region are N+ doped.

7. The lateral bipolar junction transistor according to claim 1, wherein: Also includes: A first base region extension region extending laterally from the first base region and a second base region extension region extending laterally from the corresponding first base region and the corresponding second base region, the first base region extension region and the second base region extension region being associated with the first end of the well region to provide a first base region connection and a second base region connection extending beyond the Pi-shaped or H-shaped gate covering the top surface of the first base region and the second base region.

8. The lateral bipolar junction transistor according to claim 1, wherein: The Pi-shaped or H-shaped gate is H-shaped, and the lateral bipolar junction transistor further includes: The third base region extension region and the fourth base region extension region laterally extend the corresponding first base region and the corresponding second base region, and are associated with the first end of the well region to provide a third base region connection and a fourth base region connection that extend beyond the H-shaped gate covering the top surface of the first base region and the second base region.

9. A circuit comprising: A plurality of metal oxide semiconductor transistors, each metal oxide semiconductor transistor comprising: drain region; a first source region and a second source region; and A Pi or H-shaped gate and a gate oxide layer, the Pi or H-shaped gate includes a first gate portion extending between the drain region and the first source region, a second gate portion parallel to the first gate portion and extending between the drain region and the second source region, and a first connecting gate portion transverse to the first gate portion and the second gate portion and connecting the first gate portion and the second gate portion.

10. The circuit according to claim 9, characterized in that The Pi or H-shaped gate is an H-shaped gate, and the H-shaped gate also includes a second connecting gate part arranged parallel to the first connecting gate part and also connecting the first gate part and the second gate part, wherein the drain region and the first source region and the second source region are arranged between the first connecting gate part and the second connecting gate part.

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