Integrated grain structure

Abstract

The utility model relates to an integrated crystal grain structure. The integrated die structure includes a first capacitor conductor disposed over an isolation structure disposed within a substrate. The isolation structure extends laterally beyond opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is disposed along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is disposed along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps portions of both the capacitor dielectric and the first capacitor conductor.

Description

Technical Field

[0001] The utility model relates to an integrated grain structure. Background Art

[0002] An integrated die is formed on a semiconductor chip that includes millions or billions of transistor devices. The transistor devices are configured to act as switches and / or generate power gains to implement the logic functions of the integrated die (e.g., forming a processor configured to perform logic functions). The integrated die also includes passive devices such as capacitors, resistors, inductors, and varactors. Passive devices are widely used to control the characteristics of the integrated die, such as gain and time constant. Utility Model Content

[0003] In some embodiments, the present invention relates to an integrated die structure comprising: a first capacitor conductor disposed above an isolation structure disposed within a substrate, the isolation structure extending laterally beyond opposing outer sidewalls of the first capacitor conductor; a capacitor dielectric disposed along one of the opposing outer sidewalls of the first capacitor conductor and disposed above a top surface of the first capacitor conductor; and a second capacitor conductor disposed along one outer sidewall of the capacitor dielectric and disposed above a top surface of the capacitor dielectric, wherein the second capacitor conductor laterally overlaps portions of both the capacitor dielectric and the first capacitor conductor.

[0004] In other embodiments, the present invention relates to an integrated die structure. The integrated die structure includes: a first capacitor conductor disposed above a substrate; a capacitor dielectric disposed on the first capacitor conductor; a second capacitor conductor separated from the first capacitor conductor by the capacitor dielectric, wherein a recess is disposed along a top portion of the second capacitor conductor and extends laterally from directly above the first capacitor conductor to a laterally outer side of the first capacitor conductor; a metal inlay disposed within the recess within the second capacitor conductor; and an interlayer dielectric (ILD) structure extending from above the metal inlay to an opposite side along the second capacitor conductor.

[0005] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated die structures including disclosed front-end-of-line (FEOL) capacitors are shown.

[0008] Figure 2 Cross-sectional views of some additional embodiments of integrated die structures including disclosed FEOL capacitors are shown.

[0009] Figures 3A-3C Cross-sectional views of some embodiments including integrated die structures integrating the disclosed FEOL capacitors with FEOL transistor devices are shown.

[0010] Figure 4 Cross-sectional views of some additional embodiments are shown including integrated die structures integrating the disclosed FEOL capacitors with FEOL transistor devices.

[0011] Figure 5 Cross-sectional views of some additional embodiments are shown including integrated die structures integrating the disclosed FEOL capacitors with FEOL transistor devices.

[0012] Figure 6-27 Cross-sectional views of some embodiments are shown corresponding to methods of forming an integrated die including integrating the disclosed FEOL capacitor and FEOL transistor devices.

[0013] Figure 28 Flowcharts illustrating some embodiments of methods for forming an integrated die including integrating the disclosed FEOL capacitor and FEOL transistor devices are shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the description below may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, specify the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "above," and "upper" may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] A capacitor is a device for storing energy in an electric field generated by the charge accumulated on the capacitor's conductive plates. A capacitor typically includes a first conductive plate and a second conductive plate separated from the first conductive plate by a dielectric. Modern integrated circuits include a variety of capacitors, which can be roughly divided into front-end-of-line (FEOL) capacitors and back-end-of-line (BEOL) capacitors. FEOL capacitors are capacitors placed on and / or within a substrate and may include MOS capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, or similar capacitors. BEOL capacitors are capacitors placed on and / or within a dielectric structure above a substrate and may include MIM (metal-insulator-metal) capacitors, MOM (metal-insulator-metal) capacitors, or similar capacitors.

[0017] FEOL capacitors are often integrated onto the same substrate as other FEOL devices (e.g., low-voltage transistor devices, medium-voltage transistor devices, and high-voltage transistor devices). The integration of FEOL capacitors with other FEOL devices can lead to numerous issues with the FEOL capacitors. For example, FEOL PIP capacitors are typically formed above a p-doped substrate and have high parasitic capacitance between the lower capacitor plate and the p-type substrate, while FEOL MOS capacitors have capacitance that varies with gate voltage, resulting in unstable capacitance values ​​when the gate voltage varies. Furthermore, the different structures of capacitors and transistor devices complicate manufacturing. For example, in emerging technology nodes (e.g., at the 16nm technology node and below), additional hard masks may be used during the formation of FEOL capacitors to protect the gate oxide of the high-voltage devices and / or to prevent the logic fin recess process from consuming various isolation structures within the substrate, thereby reducing the electrical isolation between the logic device and the high-voltage devices.

[0018] The present invention relates to an integrated die including a FEOL capacitor (e.g., a PIP capacitor) formed using a simple and low-cost fabrication process that leverages process steps used to form other FEOL devices (e.g., high-voltage and logic transistor devices). In some embodiments, the disclosed FEOL capacitor includes a first capacitor conductor disposed above an isolation structure disposed within a substrate. The isolation structure extends laterally beyond the opposite outermost walls of the first capacitor conductor. A capacitor dielectric is disposed along one of the opposite outermost walls of the first capacitor conductor and disposed above the topmost surface of the first capacitor conductor. A second capacitor conductor is disposed along the outermost wall of one of the capacitor dielectrics and disposed above the topmost surface of the capacitor dielectric. The second capacitor conductor laterally overlaps portions of both the capacitor dielectric and the first capacitor conductor. By forming the second capacitor conductor to laterally overlap the capacitor dielectric and the first capacitor conductor, the second capacitor conductor can be formed using layers and processes used during the fabrication of other FEOL devices, thereby allowing the disclosed FEOL capacitor to be formed without adding expensive fabrication processes. Furthermore, by forming the first capacitor conductor above the isolation structure, the disclosed FEOL capacitor can achieve stable operation.

[0019] Figure 1 A cross-sectional view of some embodiments of an integrated die structure 100 including a disclosed front end of line (FEOL) capacitor is shown.

[0020] The integrated die structure 100 includes a FEOL capacitor 104 disposed above a substrate 102. The FEOL capacitor 104 includes a first capacitor conductor 106 separated from a second capacitor conductor 110 by a capacitor dielectric 108. The capacitor dielectric 108 extends along the sidewalls and top surface of the first capacitor conductor 106. The second capacitor conductor 110 extends along the sidewalls and top surface of the first capacitor conductor 106, extending laterally from outside the capacitor dielectric 108 and the first capacitor conductor 106 to directly above the capacitor dielectric 108 and the first capacitor conductor 106. The second capacitor conductor 110 also extends vertically from the bottom of the first capacitor conductor 106 to above the top of the first capacitor conductor 106, such that the capacitor dielectric 108 vertically and laterally separates the first capacitor conductor 106 from the second capacitor conductor 110.

[0021] In some embodiments, second capacitor conductor 110 has a first upper surface located outside capacitor dielectric 108 and a second upper surface located above capacitor dielectric 108 and first capacitor conductor 106. In some embodiments, the second upper surface is vertically above the first upper surface such that second capacitor conductor 110 has a greater height directly above first capacitor conductor 106 than laterally outward from first capacitor conductor 106.

[0022] In some embodiments, a lower dielectric 114 is disposed over the substrate 102. The first capacitor conductor 106 and the second capacitor conductor 110 are disposed over the lower dielectric 114 such that the lower dielectric 114 extends along the bottommost surfaces of the first capacitor conductor 106 and the second capacitor conductor 110. In some embodiments, the first capacitor conductor 106 contacts a first portion of the lower dielectric 114, the capacitor dielectric 108 contacts a second portion of the lower dielectric 114, and the second capacitor conductor 110 contacts a third portion of the lower dielectric 114.

[0023] In some embodiments, lower dielectric 114 is disposed on isolation structure 112, which is disposed on and / or within substrate 102. In some embodiments, isolation structure 112 comprises a shallow trench isolation (STI) structure disposed within a trench formed by one or more sidewalls of substrate 102. In such embodiments, isolation structure 112 comprises one or more dielectric materials disposed within the trench.

[0024] An inter-level dielectric (ILD) structure 118 is disposed over the substrate 102 and the FEOL capacitor 104. The ILD structure 118 laterally surrounds the FEOL capacitor 104 and the lower dielectric 114. In some embodiments, sidewall spacers 116 are disposed along the outermost wall of the capacitor dielectric 108 and along the opposite outermost wall of the second capacitor conductor 110. The sidewall spacers 116 laterally separate the capacitor dielectric 108 and the second capacitor conductor 110 from the ILD structure 118. A conductive interconnect 120 extends vertically through the ILD structure 118 to contact the first capacitor conductor 106 and the second capacitor conductor 110.

[0025] By extending the second capacitor conductor 110 along the sidewalls and upper surface of the first capacitor conductor 106, the FEOL capacitor 104 can be formed using processing steps used to form other FEOL devices (e.g., logic transistor devices, high voltage transistor devices, etc.). Therefore, the FEOL capacitor 104 can be formed without specialized processing steps (e.g., masking and / or patterning steps) that increase the cost of forming the integrated die structure 100. Furthermore, by separating the FEOL capacitor 104 from the substrate 102 via the isolation structure 112 and the lower dielectric 114, the FEOL capacitor 104 can be formed to have a stable capacitance and low parasitic capacitance.

[0026] Figure 2 Cross-sectional views of some additional embodiments of integrated die structures 200 including disclosed FEOL capacitors are shown.

[0027] The integrated die structure 200 includes a FEOL capacitor 104 disposed above a substrate 102. The FEOL capacitor 104 includes a first capacitor conductor 106 separated from a second capacitor conductor 110 by a capacitor dielectric 108. The capacitor dielectric 108 extends along the opposite outermost sidewalls and the upper surface of the first capacitor conductor 106. The second capacitor conductor 110 extends laterally from the outer side of the capacitor dielectric 108 and the first capacitor conductor 106 to directly above the capacitor dielectric 108 and the first capacitor conductor 106.

[0028] The first capacitor conductor 106 includes a first conductive material and the second capacitor conductor 110 includes a second conductive material. In some embodiments, the first conductive material and the second conductive material may include or be doped polysilicon, titanium, titanium nitride, tantalum, tantalum nitride, and / or the like. In some embodiments, the first conductive material and the second conductive material may be the same material (e.g., doped polysilicon). In other embodiments, the first conductive material may include or be a first material (e.g., titanium nitride), and the second conductive material may include or be a different second material (e.g., doped polysilicon). The capacitor dielectric 108 may include an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a carbide (e.g., silicon carbide, silicon oxycarbide, etc.), and / or the like.

[0029] In some embodiments, the second capacitor conductor 110 has a curved upper surface 110r that forms a recess 202 that is recessed below the highest point of the second capacitor conductor 110. In some embodiments, the recess 202 extends laterally from directly above the first capacitor conductor 106 to laterally outward of the first capacitor conductor 106. In some embodiments, the highest point of the second capacitor conductor 110 is laterally outward of the first capacitor conductor 106. The recess 202 causes the width of the second capacitor conductor 110 along the outermost wall of the second capacitor conductor 110 to be greater than the width between the outermost wall and the lateral center of the second capacitor conductor 110.

[0030] In some embodiments, a metallic inset 204 is disposed within the recess 202 in the second capacitor conductor 110. The metallic inset 204 can have a curved lower surface facing the second capacitor conductor 110 and a substantially flat upper surface facing away from the second capacitor conductor 110. In some embodiments, the metallic inset 204 can include or be tungsten, ruthenium, and / or the like.

[0031] FEOL capacitor 104 is vertically separated from substrate 102 by isolation structure 112 and lower dielectric 114. Isolation structure 112 is disposed within a trench formed by the sidewalls of substrate 102. Lower dielectric 114 is disposed on isolation structure 112. In some embodiments, isolation structure 112 may extend laterally beyond the opposite outermost wall of lower dielectric 114. FEOL capacitor 104 is laterally set back from the opposite outermost wall of lower dielectric 114. In some embodiments, FEOL capacitor 104 may be laterally set back from the opposite outermost wall of lower dielectric 114 by different distances. For example, the outermost wall of second capacitor conductor 110 may be laterally set back from the first outermost wall of lower dielectric 114 by a first distance, and the outermost wall of first capacitor conductor 106 may be laterally set back from the second outermost wall of lower dielectric 114 by a second distance, the second distance being different from the first distance.

[0032] In some embodiments, sidewall spacers 116a-116c may be disposed along the outermost wall of the capacitor dielectric 108 and along the opposite outermost wall of the second capacitor conductor 110. In some embodiments, the sidewall spacers 116a-116c may include a first sidewall spacer 116a, a second sidewall spacer 116b, and a third sidewall spacer 116c. The first sidewall spacer 116a is disposed along the outermost wall of the capacitor dielectric 108. The capacitor dielectric 108 laterally separates the first sidewall spacer 116a from the first capacitor conductor 106. The second sidewall spacer 116b is disposed on the upper surface of the capacitor dielectric 108 and along the first outermost wall of the second capacitor conductor 110. The third sidewall spacer 116c is disposed along the second outermost wall of the second capacitor conductor 110.

[0033] In some embodiments, the third sidewall spacer 116c can be substantially aligned with the first outermost sidewall of the lower dielectric 114, and the first sidewall spacer 116a can be set back from the second outermost sidewall of the lower dielectric 114. In such embodiments, the lower dielectric 114 extends laterally from the outermost sidewall of the third sidewall spacer 116c beyond the outermost sidewall of the first sidewall spacer 116a. In some embodiments, the first sidewall spacer 116a, the second sidewall spacer 116b, and the third sidewall spacer 116c have topmost surfaces located at different heights above the substrate 102.

[0034] An interlayer dielectric (ILD) structure 118 is disposed over the substrate 102. In some embodiments, the ILD structure 118 extends continuously from over the metal inlay 204 to along the sidewalls of the second capacitor conductor 110 and the lower dielectric 114. In some embodiments, the ILD structure 118 may include a first ILD layer 118a surrounding opposite sides of the second capacitor conductor 110 and a second ILD layer 118b over the first ILD layer 118a and the second capacitor conductor 110. In some embodiments, the first ILD layer 118a may have an uppermost surface located at or below an uppermost surface of the second capacitor conductor 110. In some embodiments, the first ILD layer 118a and the second ILD layer 118b may include one or more of silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), a porous dielectric material, or the like.

[0035] A conductive interconnect 120 extends vertically through the ILD structure 118 to electrically contact the first capacitor conductor 106 and the second capacitor conductor 110. In some embodiments, the conductive interconnect 120 may include a conductive contact extending vertically through the ILD structure 118 to contact the first capacitor conductor 106 and the second capacitor conductor 110. In some embodiments, the conductive interconnect 120 may be electrically coupled to the first capacitor conductor 106 and the second capacitor conductor 110 through the silicide 206.

[0036] Figure 3A A cross-sectional view of some embodiments including an integrated die structure 300 integrating the disclosed FEOL capacitor and FEOL transistor devices is shown.

[0037] The integrated die structure 300 includes a substrate 102 having a capacitor region 302, a high voltage region 304, and a logic region 306. The disclosed FEOL capacitor 104 is disposed above the substrate 102 and within the capacitor region 302. The disclosed FEOL capacitor 104 includes a first capacitor conductor 106 separated from a second capacitor conductor 110 by a capacitor dielectric 108. In some embodiments, the second capacitor conductor 110 is at least partially disposed above and laterally outside the first capacitor conductor 106.

[0038] A high voltage transistor device 308 is disposed within the high voltage region 304. The high voltage transistor device 308 includes a high voltage gate structure 310 disposed above a high voltage gate dielectric 314. Source / drain regions 312 are disposed within the substrate 102 on opposite sides of the high voltage gate structure 310. In some embodiments, the high voltage gate dielectric 314 may be disposed within a high voltage gate dielectric recess within the substrate 102. The high voltage gate dielectric recess is formed by the sidewalls and recess surface of the substrate 102. The high voltage gate dielectric recess allows the high voltage gate dielectric 314 to be formed to a relatively large thickness without causing planarization issues during fabrication of the integrated die structure 300.

[0039] In some embodiments, the high-voltage gate dielectric 314 may include a first high-voltage gate dielectric 314 a and a second high-voltage gate dielectric 314 b. The first high-voltage gate dielectric 314 a is disposed along the sidewalls and surface of a recess in the substrate 102 that forms the high-voltage gate dielectric recess. The second high-voltage gate dielectric 314 b is disposed above the first high-voltage gate dielectric 314 a. In some embodiments, the outermost wall of the second high-voltage gate dielectric 314 b may be laterally offset from the outermost wall of the first high-voltage gate dielectric 314 a.

[0040] In some embodiments, the high-voltage gate structure 310 may include a high-voltage metal gate 310 b and a high-voltage metal cap 310 a disposed over the high-voltage metal gate 310 b. In some embodiments, the high-voltage metal gate 310 b may include or be an n-type metal (e.g., aluminum, tantalum, titanium, hafnium, or the like) or a p-type metal (e.g., nickel, cobalt, molybdenum, platinum, lead, gold, or the like). In various embodiments, the high-voltage metal cap 310 a may include or be tungsten, ruthenium, titanium, and / or the like.

[0041] Logic transistor device 316 is disposed within logic region 306. Logic transistor device 316 has a first threshold voltage (e.g., 1.8 volts (V)) that is less than a second voltage of high-voltage transistor device 308. Logic transistor device 316 includes a logic gate structure 322 disposed above a logic gate dielectric layer 324. Logic gate dielectric layer 324 may be disposed along sidewalls and an upper surface of one or more fins of semiconductor material 320 that protrude outward from the upper surface of substrate 102. In some embodiments, the one or more fins of semiconductor material 320 are laterally separated from each other by one or more fin isolation structures 321. Source / drain regions (not shown) are disposed within substrate 102 on opposite sides of logic gate structure 322. In some embodiments, a channel region of logic transistor device 316 may be disposed within the one or more fins of semiconductor material 320 and may extend between the source / drain regions along a line extending into the page.

[0042] In some embodiments, the logic gate structure 322 may include a logic metal gate 322b and a logic metal cap 322a disposed above the logic metal gate 322b. In some embodiments, the logic metal gate 322b may include or be an n-type metal (e.g., aluminum, tantalum, titanium, hafnium, or the like) or a p-type metal (e.g., nickel, cobalt, molybdenum, platinum, lead, gold, or the like). In various embodiments, the logic metal cap 322a may include or be tungsten, ruthenium, titanium, and / or the like.

[0043] In some embodiments, a boundary isolation structure 318 may be disposed between the high voltage region 304 and the logic region 306. The ILD structure 118 is disposed above the substrate 102. A conductive interconnect 120 extends vertically through the ILD structure 118 to contact the first capacitor conductor 106, the second capacitor conductor 110, the source / drain regions 312, the high voltage gate structure 310, and the logic gate structure 322.

[0044] Figure 3B A cross-sectional view 326 is shown illustrating some embodiments of a high voltage gate dielectric 314 disposed within the high voltage region 304 of the substrate 102 .

[0045] As shown in cross-sectional view 326, the high-voltage gate dielectric 314 includes a first high-voltage gate dielectric 314a and a second high-voltage gate dielectric 314b positioned above the first high-voltage gate dielectric 314a. The first high-voltage gate dielectric 314a has a first thickness 328, and the second high-voltage gate dielectric 314b has a second thickness 330 extending from the bottom of the second high-voltage gate dielectric 314b to the upper surface of the substrate 102. The first high-voltage gate dielectric 314a and the second high-voltage gate dielectric 314b provide a collective thickness 332 measured between the bottom of the first high-voltage gate dielectric 314a and the upper surface of the substrate 102.

[0046] In some embodiments, the high voltage transistor device ( Figure 3A The first thickness 328 may have a threshold voltage in the range of about 4 V to about 8 V. In such an embodiment, the first thickness 328 may be about 100 angstroms. and about 150 angstroms, about 110 angstroms and about 130 angstroms, or other similar values; the second thickness 330 may be between about 90 angstroms and about 130 angstroms, about 100 angstroms and about 120 angstroms, or other similar values; the total thickness 332 may be between about 200 angstroms and about 300 angstroms, about 210 angstroms and about 250 angstroms, or other similar values.

[0047] In other embodiments, the high voltage transistor device ( Figure 3A 308) may have a threshold voltage in the range of about 20V and about 35V. In such embodiments, the first thickness 328 may be in the range of about 100 angstroms and about 150 angstroms, about 120 angstroms and about 140 angstroms, or other similar values; the second thickness 330 may be in the range of about 700 angstroms and about 1300 angstroms, about 800 angstroms and about 1200 angstroms, or other similar values; and the total thickness 332 may be in the range of about 800 angstroms and about 1500 angstroms, about 920 angstroms and about 1360 angstroms, or other similar values. In still other embodiments, the high voltage transistor device ( Figure 3A 308) may have a threshold voltage greater than 35 V. In such an embodiment, the first thickness 328, the second thickness 330, and the total thickness 332 may be greater than the above range.

[0048] Figure 3C A cross-sectional view 334 is shown, which shows a circuit disposed in a high voltage region ( Figure 3A 304) and logical area ( Figure 3A 306) between the boundary isolation structure 318 of some embodiments.

[0049] As shown in cross-sectional view 334, boundary isolation structure 318 includes a first upper surface 318a and a second upper surface 318b located above first upper surface 318a. First upper surface 318a is laterally located between second upper surface 318b and logic transistor device 316. In some embodiments, first upper surface 318a may have a first length 336 and second upper surface 318b may have a second length 338. In some embodiments, first length 336 is greater than second length 338.

[0050] In some embodiments, the high voltage transistor device ( Figure 3A 308 ) may have a threshold voltage in a range between about 4 V and about 8 V. In such an embodiment, the first length 336 may be in a range between about 0.1 micrometers (μm) and about 0.5 μm, between about 0.2 μm and about 0.3 μm, or other similar values; the second length 338 may be in a range between about 0.05 μm and about 0.4 μm, between about 0.1 μm and about 0.2 μm, or other similar values.

[0051] In other embodiments, the high voltage transistor device ( Figure 3A 308) may have a threshold voltage in the range of about 20V to about 35V. In such an embodiment, the first length 336 may be in the range of about 0.1 μm to about 0.5 μm, about 0.25 μm to about 0.35 μm, or other similar values; the second length 338 may be in the range of about 0.05 μm to about 0.4 μm, about 0.15 μm to about 0.25 μm, or other similar values. In yet other embodiments, the high voltage transistor device ( Figure 3A 308) may have a threshold voltage greater than 35 V. In such an embodiment, the first length 336 and the second length 338 may be greater than the above range.

[0052] Figure 4 Cross-sectional views of some additional embodiments are shown including integrated die structures 400 integrating the disclosed FEOL capacitors with FEOL transistor devices.

[0053] Integrated die structure 400 includes substrate 102 having capacitive region 302, high voltage region 304, and logic region 306. FEOL capacitor 104 is disposed in capacitive region 302, high voltage transistor device 308 is disposed in high voltage region 304, and logic transistor device 316 is disposed in logic region 306.

[0054] The substrate 102 has a stepped region 402 that is laterally located between a high-voltage isolation structure 408 in the high-voltage region 304 and one or more proximate fin isolation structures 321 in the logic region 306. The stepped region 402 includes a first upper surface 402a and a second upper surface 402b located above the first upper surface 402a. The first upper surface 402a is laterally located between the second upper surface 402b and the logic transistor device 316. In some embodiments, the first upper surface 402a may have a first length 404, and the second upper surface 402b may have a second length 406. In some embodiments, the first length 404 is greater than the second length 406.

[0055] In some embodiments, the high voltage transistor device 308 may have a threshold voltage in a range between about 4 V and about 8 V. In such embodiments, the first length 404 may be in a range between about 0.3 μm and about 0.6 μm, about 0.4 μm and about 0.5 μm, or other similar values; and the second length 406 may be in a range between about 0.2 μm and about 0.5 μm, about 0.3 μm and about 0.4 μm, or other similar values.

[0056] In other embodiments, the high-voltage transistor device 308 may have a threshold voltage within a range between approximately 20 V and approximately 35 V. In such embodiments, the first length 404 may be within a range between approximately 0.4 μm and approximately 0.6 μm, approximately 0.45 μm and approximately 0.55 μm, or other similar values; and the second length 406 may be within a range between approximately 0.3 μm and approximately 0.5 μm, approximately 0.35 μm and approximately 0.45 μm, or other similar values. In still other embodiments, the high-voltage transistor device 308 may have a threshold voltage greater than 35 V. In such embodiments, the first length 404 and the second length 406 may be greater than the aforementioned ranges.

[0057] Figure 5 Cross-sectional views of some additional embodiments are shown including integrated die structures 500 integrating the disclosed FEOL capacitors with FEOL transistor devices.

[0058] Integrated die structure 500 includes substrate 102 having capacitive region 302, high voltage region 304, and logic region 306. FEOL capacitor 104 is disposed in capacitive region 302, high voltage transistor device 308 is disposed in high voltage region 304, and logic transistor device 316 is disposed in logic region 306.

[0059] FEOL capacitor 104 includes a first capacitor conductor 106 separated from a second capacitor conductor 110 by a capacitor dielectric 108. A lower dielectric 114 is disposed below FEOL capacitor 104, and an isolation structure 112 is disposed below lower dielectric 114. In some embodiments, lower dielectric 114 may have a first upper surface 114a directly below first capacitor conductor 106 and a second upper surface 114b laterally outward from first capacitor conductor 106. In some embodiments, first upper surface 114a may be higher than second upper surface 114b.

[0060] The first capacitor conductor 106 has a thickness 502 in a range of between about 150 angstroms and about 300 angstroms, between about 175 angstroms and about 250 angstroms, about 200 angstroms, or other similar values. The capacitor dielectric 108 has a thickness 504 in a range of between about 25 angstroms and about 75 angstroms, between about 40 angstroms and about 50 angstroms, about 45 angstroms, or other similar values. The second capacitor conductor 110 has a thickness 506 in a range of between about 500 angstroms and about 1500 angstroms, between about 750 angstroms and about 1250 angstroms, about 1000 angstroms, or other similar values.

[0061] Isolation structure 112 has a thickness 508 in a range of between about 2000 angstroms and about 5000 angstroms, between about 2500 angstroms and about 4000 angstroms, about 3000 angstroms, or other similar values. Lower dielectric 114 has a thickness 510 in a range of between about 100 angstroms and about 200 angstroms, between about 125 angstroms and about 175 angstroms, about 140 angstroms, or other similar values. First capacitor conductor 106 is vertically spaced apart from substrate 102 by a distance 512 in a range of between about 3000 angstroms and about 3500 angstroms, between about 3100 angstroms and about 3250 angstroms, or other similar values.

[0062] The high-voltage transistor device 308 includes a high-voltage gate structure 310 separated from the substrate 102 by a high-voltage gate dielectric 314. The high-voltage gate dielectric 314 includes a first high-voltage gate dielectric 314a and a second high-voltage gate dielectric 314b. In some embodiments, the second high-voltage gate dielectric 314b and the lower dielectric 114 are made of the same material (e.g., high-temperature silicon dioxide). In some embodiments, the thickness 514 of the outermost wall of the second high-voltage gate dielectric 314b and the thickness 510 of the lower dielectric 114 are substantially equal. In some embodiments, the second high-voltage gate dielectric 314b has an upper surface that is substantially coplanar with the upper surface of the lower dielectric 114.

[0063] Logic transistor device 316 includes a logic gate structure 322 separated from substrate 102 by a logic gate dielectric layer 324 extending along the sidewalls and upper surface of one or more fins in semiconductor material 320. In some embodiments, logic gate dielectric layer 324 and capacitor dielectric 108 are the same material (e.g., oxide). In some embodiments, logic gate dielectric layer 324 can have a thickness 516 that is substantially equal to the thickness 504 of capacitor dielectric 108.

[0064] It should be understood that the disclosed integrated die structures (e.g., integrated die structures 300, 400, and / or 500) can be implemented in a wide range of applications. For example, the disclosed integrated die structures can be implemented in bipolar-CMOS-DMOS (BCD), driver integrated die (IC), image sensor, power management device, image signal processing (ISP), or the like.

[0065] Figure 6-27 Some embodiments are shown in cross-sectional views 600-2700 corresponding to methods of forming an integrated die including integrating the disclosed FEOL capacitor with a FEOL transistor device. Figure 6-27 Although described in relation to a method, it should be understood that the structure disclosed in the method is not limited to the method, but can stand alone as a structure independent of the method.

[0066] like Figure 6 As shown in cross-sectional view 600 of FIG, a substrate 102 is provided. In various embodiments, substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, etc.), such as a semiconductor wafer and / or one or more chips thereon, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, substrate 102 may include p-type doping. Substrate 102 includes a capacitor region 302, a high voltage region 304, and a logic region 306. In some embodiments, high voltage region 304 may be adjacent to logic region 306.

[0067] like Figure 7 As shown in cross-sectional view 700 of FIG, substrate 102 is patterned to form one or more fins of semiconductor material 320 within logic region 306. By etching substrate 102 to form one or more fins of semiconductor material 320, sidewalls of substrate 102 protrude outward from the recessed surface of substrate 102. In some embodiments, substrate 102 may be patterned by selectively exposing substrate 102 to an etchant 702 according to mask 704. In some embodiments, etchant 702 may include a dry etchant (e.g., including fluorine, chlorine, and / or the like). In some embodiments, mask 704 may include a photosensitive material (e.g., photoresist), a hard mask, and / or the like.

[0068] like Figure 8 As shown in cross-sectional view 800 of FIG, one or more trenches 802 are formed in substrate 102. In some embodiments, the one or more trenches 802 can be formed by selectively etching substrate 102. In some embodiments, substrate 102 can be selectively etched by forming a mask 806 over substrate 102 and then exposing substrate 102 to an etchant 804. The etchant 804 is configured to selectively remove unmasked portions of substrate 102 and form the one or more trenches 802. In various embodiments, etchant 804 can include a dry etchant having an etching chemistry including a fluorine species (e.g., CF4, CHF3, C4F8, etc.) or an etchant including hydrofluoric acid (HF), potassium hydroxide (KOH), or the like. In some embodiments, mask 806 can be formed over a pad oxide layer (not shown) disposed along the upper surface of substrate 102. In some embodiments, one or more trenches 802 can be disposed in substrate 102 within capacitor region 302 and along a boundary between high voltage region 304 and logic region 306.

[0069] like Figure 9 As shown in cross-sectional view 900 of FIG, isolation structure 112 and boundary isolation structure 318 are formed in one or more trenches 802 in substrate 102. In some embodiments, isolation structure 112 and boundary isolation structure 318 may be formed by forming one or more dielectric materials in one or more trenches 802. In some embodiments, one or more dielectric materials may also be formed between adjacent fins in one or more fins of semiconductor material to form one or more fin isolation structures 321.

[0070] In some embodiments, the one or more dielectric materials may include oxides (e.g., silicon oxide), nitrides, carbides, or the like. In some embodiments, the one or more dielectric materials may be formed by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). In some embodiments, the one or more dielectric materials may be formed by performing a thermal oxidation process over the substrate 102, wherein a mask (e.g., Figure 8 A mask 806 (e.g., a dielectric mask 806) is in place, followed by a deposition process to fill the one or more trenches 802 with one or more dielectric materials. After the one or more trenches 802 are filled with the one or more dielectric materials, a planarization process (e.g., a chemical mechanical planarization process) may be performed to remove the mask and excess one or more dielectric materials above the substrate 102.

[0071] like Figure 10As shown in the cross-sectional view 1000 of FIG, the substrate 102 is selectively patterned to form a high-voltage gate dielectric recess 1002 within the upper surface 102u of the substrate 102 and within the high-voltage region 304. The substrate 102 can be selectively patterned by exposing the substrate 102 to an etchant 1004 according to a mask 1006 to form sidewalls of the substrate 102, which form the high-voltage gate dielectric recess 1002. After forming the high-voltage gate dielectric recess 1002, a first high-voltage dielectric 314a is formed along the sidewalls and upper surface of the substrate 102 where the high-voltage gate dielectric recess 1002 is formed. In some embodiments, the first high-voltage dielectric 314a can be formed by a thermal oxidation process (e.g., a dry thermal oxidation process or a wet thermal oxidation process). In some embodiments, the first high voltage dielectric 314a may be formed to a thickness ranging between about 5 angstroms and about 50 angstroms, between about 10 angstroms and about 50 angstroms, or other similar values.

[0072] like Figure 11 As shown in cross-sectional view 1100 of FIG, a second high-voltage dielectric layer 1102 is formed above the upper surface 102u of the substrate 102 and above the first high-voltage dielectric 314a. In some embodiments, the second high-voltage dielectric layer 1102 is formed to extend continuously from directly above the first high-voltage dielectric 314a to above the isolation structure 112 within the capacitor region 302. In some embodiments, the second high-voltage dielectric layer 1102 may include a high-temperature oxide (e.g., high-temperature silicon dioxide). In some such embodiments, the second high-voltage dielectric layer 1102 may be formed by the reaction of nitrous oxide (N2O) and dichlorosilane during a low-pressure chemical vapor deposition (LP-CVD) process.

[0073] like Figure 12 As shown in the cross-sectional view 1200 of FIG, a first conductive layer 1202 is formed over the second high voltage dielectric layer 1102. In some embodiments, the first conductive layer 1202 may be formed along the upper surface and sidewalls of the second high voltage dielectric layer 1102. In such an embodiment, the first conductive layer 1202 may be formed to continuously extend from within the capacitor region 302 into the high voltage region 304 and into the logic region 306.

[0074] In various embodiments, first conductive layer 1202 may include or be doped polysilicon, titanium nitride, or the like. In some embodiments, first conductive layer 1202 may be formed to a thickness ranging from about 150 angstroms to about 300 angstroms, from about 175 angstroms to about 250 angstroms, or about 200 angstroms, or other similar values. In some embodiments, first conductive layer 1202 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, or the like).

[0075] like Figure 13 As shown in the cross-sectional view 1300, the first conductive layer ( Figure 12 1202) to form the first capacitor conductor 106, a high voltage mask 1302 is formed, and the first conductive layer is removed from the logic region 306. The first capacitor conductor 106 is formed above the isolation structure 112 such that the isolation structure 112 extends laterally from directly below the first capacitor conductor 106 beyond the outermost sidewalls of the first capacitor conductor 106. The high voltage mask 1302 is formed to protect the high voltage gate dielectric 314 from damage during subsequent etching processes.

[0076] like Figure 14 As shown in cross-sectional view 1400 , the boundary isolation structure 318 and one or more fin isolation structures 321 within the logic region 306 are selectively etched. The boundary isolation structure 318 and one or more fin isolation structures 321 are selectively etched to recess the boundary isolation structure 318 and one or more fin isolation structures 321 and expose upper portions of the sidewalls of the substrate 102 forming one or more fins of the semiconductor material 320. In some embodiments, the boundary isolation structure 318 and one or more fin isolation structures 321 are etched with a mask 1402 in place to cover the capacitor region 302 and the high voltage region 304.

[0077] like Figure 15 As shown in cross-sectional view 1500 of FIG1 , a logic gate dielectric layer 324 is formed on the exposed surfaces of the one or more fins of the semiconductor material 320. For example, the logic gate dielectric layer 324 can be formed on the upper portions of the sidewalls of the substrate 102 and on the upper surface of the substrate 102 of the one or more fins of the semiconductor material 320. In some embodiments, the logic gate dielectric layer 324 can also be formed on the opposite sidewalls and the uppermost surface of the high voltage mask 1302. In some embodiments, the capacitor dielectric 108 can be simultaneously formed on the opposite sidewalls and the uppermost surface of the first capacitor conductor 106.

[0078] In some embodiments, the logic gate dielectric layer 324 and the capacitor dielectric 108 may be formed to a thickness ranging from about 25 angstroms to about 75 angstroms, about 40 angstroms to about 50 angstroms, about 45 angstroms, or other similar values. In some embodiments, the logic gate dielectric layer 324 and the capacitor dielectric 108 may be formed by the same thermal oxidation process. In other embodiments, the logic gate dielectric layer 324 and the capacitor dielectric 108 may be formed by the same deposition process (e.g., PVD, CVD, PE-CVD, or the like).

[0079] like Figure 16As shown in the cross-sectional view 1600 of FIG, the high voltage mask 1302 is removed from the high voltage region 304. In some embodiments, the high voltage mask 1302 can be removed by an etching process.

[0080] like Figure 17 As shown in cross-sectional view 1700 of FIG1 , a second conductive layer 1702 is formed over the substrate 102. In some embodiments, the second conductive layer 1702 may be formed along the upper surfaces and sidewalls of the second high-voltage dielectric layer 1102, the capacitor dielectric 108, the logic gate dielectric layer 324, and the boundary isolation structure 318. In such an embodiment, the second conductive layer 1702 may be formed to continuously extend from within the capacitor region 302 into the high-voltage region 304 and into the logic region 306.

[0081] In some embodiments, second conductive layer 1702 may include or be doped polysilicon, titanium nitride, and / or the like. In some embodiments, second conductive layer 1702 may be formed to a thickness ranging from about 500 angstroms to about 1500 angstroms, about 750 angstroms to about 1250 angstroms, about 1000 angstroms, or other similar values. In some embodiments, second conductive layer 1702 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, or the like).

[0082] like Figure 18 As shown in the cross-sectional view 1800, the second conductive layer ( Figure 17 1702) to form a second capacitor conductor 110, a high voltage sacrificial gate structure 1802, and a logic sacrificial gate structure 1804. The second capacitor conductor 110 is formed to extend laterally from directly above the first capacitor conductor 106 beyond the outermost sidewalls of the first capacitor conductor 106. The first capacitor conductor 106, the capacitor dielectric 108, and the second capacitor conductor 110 together form the FEOL capacitor 104. In some embodiments, the second conductive layer can be selectively patterned by forming a mask over the second conductive layer and then exposing the second conductive layer to an etchant configured to selectively remove unmasked portions of the second conductive layer. In various embodiments, the etchant can include a dry etchant having an etching chemistry including a fluorine species (e.g., CF4, CHF3, C4F8, etc.) or an etchant including hydrofluoric acid (HF), potassium hydroxide (KOH), or the like.

[0083] like Figure 19As shown in cross-sectional view 1900 of the embodiment of the present invention, sidewall spacers 116 are formed on opposing sides of the second capacitor conductor 110, the high-voltage sacrificial gate structure 1802, and the logic sacrificial gate structure 1804. The sidewall spacers 116 can be formed by depositing a spacer layer over the substrate 102. In some embodiments, the spacer layer can be deposited to a thickness in a range of about 400 angstroms to about 600 angstroms by a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). The spacer layer is then etched to remove the spacer layer from horizontal surfaces, leaving the sidewall spacers 116 along opposing sides of the second capacitor conductor 110, the high-voltage sacrificial gate structure 1802, and the logic sacrificial gate structure 1804. In various embodiments, the spacer layer can include silicon nitride, silicon dioxide (SiO2), silicon oxynitride (e.g., SiON), or the like.

[0084] like Figure 20 As shown in the cross-sectional view 2000, the second high voltage dielectric layer ( Figure 19 A lower dielectric 114 is formed on the isolation structure 112 and a second high-voltage gate dielectric 314b is further formed over the first high-voltage gate dielectric 314a. The first high-voltage gate dielectric 314a and the second high-voltage gate dielectric 314b together form the high-voltage gate dielectric 314 that separates the high-voltage sacrificial gate structure 1802 from the substrate 102.

[0085] After patterning the second high-voltage dielectric layer, source / drain regions 312 may be formed within the high-voltage region 304 on opposite sides of the high-voltage sacrificial gate structure 1802. In some embodiments, the source / drain regions 312 may comprise highly doped regions within the substrate 102 (e.g., regions having a doping concentration greater than 1×10 18 cm −3 , greater than 1×10 19 cm −3 , or other similar values). In such embodiments, the source / drain regions 312 may be formed by selectively implanting a dopant species into the substrate 102 according to a mask. The dopant species may include n-type dopants (e.g., phosphorus, arsenic, antimony, bismuth, or the like) or p-type dopants (e.g., boron, aluminum, gallium, indium, or the like). In other embodiments (not shown), the source / drain regions 312 may comprise highly doped epitaxial regions. In such an embodiment, the source / drain regions 312 may be formed by selectively etching the substrate 102 to form source / drain recesses on opposite sides of the high voltage sacrificial gate structure 1802 and subsequently forming a doped epitaxial material within the source / drain recesses.

[0086] In some embodiments (not shown), additional source / drain regions may be formed within the logic region 306 on opposite sides of the logic sacrificial gate structure 1804. In some embodiments, the additional source / drain regions may include highly doped epitaxial regions. In such embodiments, the additional source / drain regions may be formed by selectively etching a portion of one or more fins of the semiconductor material 320 to form source / drain recesses on opposite sides of the logic sacrificial gate structure 1804, and then forming doped epitaxial material within the source / drain recesses.

[0087] After forming the source / drain regions 312, a first ILD layer 118a is formed over the substrate 102 and between the sides of the second capacitor conductor 110, the high voltage sacrificial gate structure 1802, and the logic sacrificial gate structure 1804. In some embodiments, the first ILD layer 118a can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In various embodiments, the first ILD layer 118a can include one or more of silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, a porous dielectric material, or the like.

[0088] In some embodiments, a planarization process may be performed after forming the first ILD layer 118a over the substrate 102. The planarization process removes portions of the first ILD layer 118a to expose the uppermost surfaces of the second capacitor conductor 110, the high-voltage sacrificial gate structure 1802, and the logic sacrificial gate structure 1804. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In some embodiments, the planarization process may result in a recess along the uppermost surface of the second capacitor conductor 110. This recess forms a recess 202 within the uppermost surface of the second capacitor conductor 110. The recess 202 is recessed below the uppermost surface of the second capacitor conductor 110.

[0089] like Figure 21 As shown in the cross-sectional view 2100, the high voltage sacrificial gate structure ( Figure 20 1802) and logic sacrificial gate structure ( Figure 20 1804) to form a high voltage gate hole 2102 and a logic gate hole 2104. In some embodiments, the high voltage sacrificial gate structure and the logic sacrificial gate structure can be removed by selectively exposing the high voltage sacrificial gate structure and the logic sacrificial gate structure to an etchant 2106. In some embodiments, before removing the high voltage sacrificial gate structure and the logic sacrificial gate structure, a mask 2108 can be formed over the capacitor region 302 to prevent the etchant 2106 from damaging the second capacitor conductor 110.

[0090] like Figure 22As shown in cross-sectional view 2200 of FIG, a high voltage gate structure 310 is formed within the high voltage gate hole 2102, and a logic gate structure 322 is formed within the logic gate hole 2104. The high voltage gate structure 310 forms a high voltage transistor device 308 within the high voltage region 304, and the logic gate structure 322 forms a logic transistor device 316 within the logic region 306. In some embodiments, the high voltage gate structure 310 may include a high voltage metal gate 310b and a high voltage metal cap 310a disposed over the high voltage metal gate 310b. In some embodiments, the logic gate structure 322 may include a logic metal gate 322b and a logic metal cap 322a disposed over the logic metal gate 322b. In various embodiments, the high voltage gate structure 310 and the logic gate structure 322 may be formed by forming a metal gate layer followed by forming a metal cap layer. The metal gate layer and the metal cap layer may be formed using deposition techniques (e.g., CVD, PE-CVD, PVD, etc.) and / or electroplating techniques (e.g., electroplating). After depositing the metal capping layer, a planarization process is subsequently performed to form the high voltage gate structure 310 and the logic gate structure 322. In various embodiments, the metal layer may include or may be an n-type metal (e.g., aluminum, tantalum, titanium, hafnium, or the like) or a p-type metal (e.g., nickel, cobalt, molybdenum, platinum, lead, gold, or the like). In various embodiments, the metal capping layer may include or may be tungsten, ruthenium, titanium, and / or the like.

[0091] like Figure 23 As shown in the cross-sectional view 2300 of FIG, a second ILD layer 118b is formed over the first ILD layer 118a, the second capacitor conductor 110, the high voltage gate structure 310, and the logic gate structure 322. In some embodiments, the second ILD layer 118b can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In various embodiments, the second ILD layer 118b can include one or more of silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, a porous dielectric material, or the like.

[0092] like Figure 24As shown in cross-sectional view 2400 of FIG. 1 , a first plurality of contact openings 2402 are formed in the first ILD layer 118 a and the second ILD layer 118 b. The first plurality of contact openings 2402 extend vertically through the first ILD layer 118 a and the second ILD layer 118 b to expose the first capacitor conductor 106 in the capacitor region 302 and further expose the source / drain region 312 in the high voltage region 304. In some embodiments, the first plurality of contact openings 2402 can be formed by selectively etching the first ILD layer 118 a and the second ILD layer 118 b according to a patterning process that exposes exposed areas of the first ILD layer 118 a and the second ILD layer 118 b that are not covered by the mask to an etchant.

[0093] like Figure 25 As shown in the cross-sectional view 2500 of FIG, a second plurality of contact openings 2502 are formed in the second ILD layer 118b. The second plurality of contact openings 2502 extend vertically through the second ILD layer 118b to expose the second capacitor conductor 110 in the capacitor region 302, the high voltage gate structure 310 in the high voltage region 304, and the logic gate structure 322 in the logic region 306. In some embodiments, the second plurality of contact openings 2502 can be formed by selectively etching the second ILD layer 118b according to a patterning process that exposes areas of the second ILD layer 118b not covered by the mask to an etchant.

[0094] like Figure 26 As shown in cross-sectional view 2600 of FIG, a self-aligned silicidation process may be performed to form silicide 206 on exposed surfaces of the first capacitor conductor 106, the second capacitor conductor 110, the source / drain regions 312, the high-voltage gate structure 310, and the logic gate structure 322. The self-aligned silicidation process may be performed by depositing metal and heating the integrated grain structure to integrate the metal into the exposed areas of the first capacitor conductor 106, the second capacitor conductor 110, the source / drain regions 312, the high-voltage gate structure 310, and the logic gate structure 322. Excess metal may then be removed by etching.

[0095] like Figure 27As shown in cross-sectional view 2700 of FIG, a plurality of conductive interconnects 120 (e.g., conductive contacts) are formed within the first plurality of contact openings 2402 and the second plurality of contact openings 2502. In some embodiments, the conductive interconnects 120 can be formed by filling the first plurality of contact openings 2402 and the second plurality of contact openings 2502 with one or more conductive materials. In some embodiments, the one or more conductive materials can include tungsten, ruthenium, titanium, copper, aluminum, and / or the like. The one or more conductive materials can be formed by a deposition process (e.g., by CVD, PVD, ALD, sputtering, or the like) and / or a plating process (e.g., electrochemical plating, electroless plating, etc.). A planarization process (e.g., CMP) can then be performed to remove excess one or more conductive materials from above the second ILD layer 118b and form the plurality of conductive interconnects 120.

[0096] Figure 28 A flow chart illustrating some embodiments of a method 2800 for forming an integrated die integrating the disclosed FEOL capacitor and FEOL transistor devices.

[0097] Although method 2800 is illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be interpreted as limiting. For example, some actions may occur in a different order and / or concurrently with other actions or events than those illustrated and / or described herein. In addition, not all illustrated actions are required to implement one or more aspects or embodiments described herein. Furthermore, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0098] At act 2802, a substrate having a capacitor region, a high voltage region, and a logic region is provided. Figure 6 A cross-sectional view 600 corresponding to some embodiments of act 2802 is shown.

[0099] At act 2804 , the substrate is patterned to form one or more fins of semiconductor material within the logic region. Figure 7 A cross-sectional view 700 corresponding to some embodiments of act 2804 is shown.

[0100] At act 2806 , one or more isolation structures are formed within the one or more trenches in the substrate. Figure 8-9 Cross-sectional views, 800 and 900 , corresponding to some embodiments of act 2806 are shown.

[0101] At act 2808 , a high voltage dielectric layer is formed over the substrate and the one or more isolation structures within the high voltage region and the capacitance region. Figure 11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 2808 .

[0102] At act 2810 , a first conductive layer is formed over the substrate and the high voltage dielectric layer. Figure 12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 2810 .

[0103] At act 2812 , the first conductive layer is patterned to form a first capacitor conductor over the high voltage dielectric layer and the one or more isolation structures. Figure 13 Cross-sectional view 1300 is shown corresponding to some embodiments of act 2812 .

[0104] At act 2814 , a logic dielectric is formed over the one or more fins of semiconductor material, and a capacitor dielectric is formed over the first capacitor conductor. Figure 15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 2814 .

[0105] At act 2816, a second conductive layer is formed over the substrate and the capacitor dielectric. Figure 17 Cross-sectional view 1700 is shown corresponding to some embodiments of act 2816 .

[0106] At act 2818, the second conductive layer is patterned to form a second capacitor conductor, a high voltage sacrificial gate structure, and a logic sacrificial gate structure. Figure 18 Cross-sectional view 1800 is shown corresponding to some embodiments of act 2818 .

[0107] At act 2820 , the high voltage dielectric layer is patterned to form a lower dielectric over the one or more isolation structures within the capacitor region. Figure 20 Cross-sectional view 2100 is shown corresponding to some embodiments of act 2820 .

[0108] At act 2822, a first inter-layer dielectric (ILD) layer is formed around the second capacitor conductor, the high voltage sacrificial gate structure, and the logic sacrificial gate structure. Figure 20 Cross-sectional view 2100 is shown corresponding to some embodiments of act 2822 .

[0109] At act 2824 , the high voltage sacrificial gate structure and the logic sacrificial gate structure are replaced with a high voltage gate structure and a logic gate structure. Figure 21-22 Cross-sectional views, 2100 and 2200 , corresponding to some embodiments of act 2824 are shown.

[0110] At act 2826 , a second interlayer dielectric (ILD) layer is formed on the first ILD layer. Figure 23 Cross-sectional view 2300 is shown corresponding to some embodiments of act 2826 .

[0111] At act 2828 , conductive interconnects are formed within the first ILD layer and / or the second ILD layer. Figures 24-27 Cross-sectional views 2400 , 2500 , 2600 , and 2700 are shown corresponding to some embodiments of act 2828 .

[0112] Thus, the present invention is directed to integrated die structures including FEOL capacitors (eg, PIP capacitors) formed by a simple and low-cost fabrication process that utilizes process steps used to form other FEOL devices (eg, high voltage and logic transistor devices).

[0113] In some embodiments, the present invention relates to an integrated die structure comprising: a first capacitor conductor disposed above an isolation structure disposed within a substrate, the isolation structure extending laterally beyond opposing outer sidewalls of the first capacitor conductor; a capacitor dielectric disposed along one of the opposing outer sidewalls of the first capacitor conductor and disposed above a top surface of the first capacitor conductor; and a second capacitor conductor disposed along one outer sidewall of the capacitor dielectric and disposed above a top surface of the capacitor dielectric, wherein the second capacitor conductor laterally overlaps portions of both the capacitor dielectric and the first capacitor conductor.

[0114] In some embodiments, the present invention further comprises: a transistor device disposed on the substrate; and a first interlayer dielectric layer, the uppermost surface of which is located at or below the uppermost surface of the second capacitor conductor, wherein the first interlayer dielectric layer laterally separates the transistor device and the second capacitor conductor. In some embodiments, the second capacitor conductor has a curved upper surface forming a recess, wherein the recess extends laterally from directly above the first capacitor conductor to a laterally outer side of the first capacitor conductor. In some embodiments, the curved upper surface is recessed below a highest point of the second capacitor conductor, wherein the highest point is laterally outer side of the first capacitor conductor. In some embodiments, the present invention further comprises: a metal inlay disposed within the recess within the second capacitor conductor; and an interlayer dielectric structure extending from above the metal inlay to along a sidewall of the second capacitor conductor. In some embodiments, the present invention further comprises: a first conductive interconnect extending through the interlayer dielectric structure to contact the first capacitor conductor; and a second conductive interconnect extending vertically through the interlayer dielectric structure to contact the second capacitor conductor, wherein the first conductive interconnect and the second conductive interconnect extend above the top of the metal inlay. In some embodiments, the method further includes: a lower dielectric disposed on the upper surface of the isolation structure and extending along the bottommost surfaces of the first capacitor conductor and the second capacitor conductor.

[0115] In other embodiments, the present invention relates to an integrated die structure. The integrated die structure includes: a first capacitor conductor disposed above a substrate; a capacitor dielectric disposed on the first capacitor conductor; a second capacitor conductor separated from the first capacitor conductor by the capacitor dielectric, wherein a recess is disposed along a top portion of the second capacitor conductor and extends laterally from directly above the first capacitor conductor to a laterally outer side of the first capacitor conductor; a metal inlay disposed within the recess within the second capacitor conductor; and an interlayer dielectric (ILD) structure extending from above the metal inlay to an opposite side along the second capacitor conductor.

[0116] In some embodiments, the present invention further comprises: a first sidewall spacer disposed along an outermost wall of the capacitor dielectric, wherein the capacitor dielectric laterally separates the first sidewall spacer from the first capacitor conductor; a second sidewall spacer disposed along an upper surface of the capacitor dielectric and a first outermost wall of the second capacitor conductor; and a third sidewall spacer disposed along a second outermost wall of the second capacitor conductor. In some embodiments, the first sidewall spacer, the second sidewall spacer, and the third sidewall spacer have topmost surfaces located at different heights above the substrate. In some embodiments, the present invention further comprises: an isolation structure disposed between the sidewalls of the substrate; a lower dielectric disposed on an upper surface of the isolation structure and extending laterally along the bottommost surfaces of the first capacitor conductor and the second capacitor conductor; and wherein the lower dielectric laterally extends from the outermost wall of the third sidewall spacer to laterally beyond the outermost wall of the first sidewall spacer. In some embodiments, the present invention further includes: a high-voltage transistor device comprising a high-voltage gate structure separated from the substrate by a first high-voltage gate dielectric and a second high-voltage gate dielectric above the first high-voltage gate dielectric, wherein the first high-voltage gate dielectric extends along the sidewalls and lower surface of the second high-voltage gate dielectric. In some embodiments, the second high-voltage gate dielectric has an upper surface that is substantially coplanar with the upper surface of the lower dielectric. In some embodiments, the thickness of the outermost walls of the lower dielectric and the second high-voltage gate dielectric are substantially equal. In some embodiments, the present invention further includes: a logic transistor device comprising a logic gate structure separated from the substrate by a logic gate dielectric layer, wherein the thickness of the capacitor dielectric and the logic gate dielectric layer are substantially equal.

[0117] In yet other embodiments, the present invention relates to a method for forming an integrated die structure, the method comprising: forming an isolation structure within a trench formed by sidewalls of a substrate; forming a high-voltage dielectric layer over the isolation structure and the substrate; forming a first conductive layer over the high-voltage dielectric layer; patterning the first conductive layer to form a first capacitor conductor over the high-voltage dielectric layer; forming a capacitor dielectric along the sidewalls and upper surface of the first capacitor conductor; forming a second conductive layer along the sidewalls and upper surface of the capacitor dielectric; patterning the second conductive layer to form a second capacitor conductor along the sidewalls and upper surface of the capacitor dielectric; and patterning the high-voltage dielectric layer to form a lower dielectric between the isolation structure and lower surfaces of the first and second capacitor conductors.

[0118] In some embodiments, the method further includes: selectively patterning the substrate to form a high-voltage gate dielectric recess within the substrate; forming a first high-voltage gate dielectric within the high-voltage gate dielectric recess; and patterning the high-voltage dielectric layer to form a second high-voltage gate dielectric above the first high-voltage gate dielectric and within the high-voltage gate dielectric recess. In some embodiments, the method further includes: patterning the substrate to form one or more fins of semiconductor material; and forming a logic gate dielectric layer along the sidewalls and upper surfaces of the one or more fins of semiconductor material, wherein forming the logic gate dielectric layer is performed simultaneously with forming the capacitor dielectric on the first capacitor conductor. In some embodiments, the method further includes: patterning the second conductive layer to form a high-voltage sacrificial gate structure above the second high-voltage gate dielectric, and further forming a logic sacrificial gate structure above the logic gate dielectric layer. In some embodiments, the method further includes: removing the high-voltage sacrificial gate structure to form a high-voltage gate hole; removing the logic sacrificial gate structure to form a logic gate hole; forming a high-voltage gate structure within the high-voltage gate hole; and forming a logic gate structure within the logic gate hole.

[0119] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present invention.

Claims

1. An integrated grain structure, characterized in that include: a first capacitor conductor disposed over an isolation structure disposed within the substrate, the isolation structure extending laterally beyond opposing outer sidewalls of the first capacitor conductor; a capacitor dielectric disposed along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor; as well as A second capacitor conductor is disposed along one outer sidewall of the capacitor dielectric and above a top surface of the capacitor dielectric, wherein the second capacitor conductor laterally overlaps portions of both the capacitor dielectric and the first capacitor conductor.

2. The integrated grain structure according to claim 1, wherein: Also includes: a transistor device disposed on the substrate; as well as A first interlayer dielectric layer has an uppermost surface located at or below an uppermost surface of the second capacitor conductor, wherein the first interlayer dielectric layer laterally separates the transistor device and the second capacitor conductor.

3. The integrated grain structure according to claim 1, wherein: The second capacitor conductor has a curved upper surface forming a recess that extends laterally from directly above the first capacitor conductor to laterally outward of the first capacitor conductor.

4. The integrated grain structure according to claim 3, wherein: The curved upper surface is recessed below a highest point of the second capacitor conductor, and the highest point is laterally located outside of the first capacitor conductor.

5. The integrated grain structure according to claim 3, wherein: Also includes: a metal insert disposed in the recess within the second capacitor conductor; as well as An interlayer dielectric structure extends from above the metal insert to along the sidewall of the second capacitor conductor.

6. The integrated grain structure according to claim 5, characterized in that Also includes: a first conductive interconnect extending through the interlayer dielectric structure to contact the first capacitor conductor; as well as A second conductive interconnect extends vertically through the interlayer dielectric structure to contact the second capacitor conductor, wherein the first conductive interconnect and the second conductive interconnect extend above a top portion of the metal inlay.

7. The integrated grain structure according to claim 1, wherein: Also includes: A lower dielectric is disposed on the upper surface of the isolation structure and extends along the bottommost surfaces of the first capacitor conductor and the second capacitor conductor.

8. An integrated grain structure, characterized in that include: a first capacitor conductor disposed above the substrate; a capacitor dielectric disposed on the first capacitor conductor; a second capacitor conductor separated from the first capacitor conductor by the capacitor dielectric, wherein a recess is provided along a top portion of the second capacitor conductor and extends laterally from directly above the first capacitor conductor to laterally outward of the first capacitor conductor; a metal insert disposed within the recess within the second capacitor conductor; as well as An interlayer dielectric structure extends from above the metal inlay to along an opposite side of the second capacitor conductor.

9. The integrated grain structure according to claim 8, characterized in that Also includes: a first sidewall spacer disposed along an outermost sidewall of the capacitor dielectric, wherein the capacitor dielectric laterally separates the first sidewall spacer from the first capacitor conductor; a second sidewall spacer disposed along an upper surface of the capacitor dielectric and a first outermost sidewall of the second capacitor conductor; as well as A third sidewall spacer is disposed along the second outermost sidewall of the second capacitor conductor.

10. The integrated grain structure according to claim 9, characterized in that The first sidewall spacer, the second sidewall spacer, and the third sidewall spacer have topmost surfaces located at different heights above the substrate.

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