Optical module

Abstract

In the optical module provided by the invention, a light emitting component comprises a temperature adjusting device, a first laser chip and a second laser chip. The temperature adjusting device comprises a first substrate, a second substrate and at least two third substrates. A seventh circuit array is formed on the upper surface of the third substrate to bear the first laser chip. And an eighth circuit array is formed on the upper surface of the other third substrate to bear the second laser chip, so that the first laser chip and the second laser chip are respectively arranged on different surfaces of the third substrate. The seventh circuit array includes a first electrical connection portion and a second electrical connection portion to electrically connect the first laser chip to the electrical connector. The seventh circuit array includes a third electrical connection portion and a fourth electrical connection portion to electrically connect the third electrode portion and the fourth electrode portion to the electrical connector, respectively. The first laser chip and the second laser chip are respectively located on different third substrates, so that the first laser chip and the second laser chip do not influence each other when temperature adjustment is carried out on the first laser chip and the second laser chip.

Description

Technical Field

[0001] The present application relates to the field of optical communication technology, and in particular to an optical module. Background Art

[0002] With the development of new services and applications such as cloud computing, mobile internet, and video, advances in optical communication technology are becoming increasingly important. As a key component in optical communication equipment, optical modules enable photoelectric signal conversion. As optical communication technology evolves, the data transmission rate of these modules continues to increase. Utility Model Content

[0003] Some embodiments provide an optical module to improve the accuracy of the output wavelength of a laser chip.

[0004] In some embodiments, an optical module is provided, comprising:

[0005] circuit boards;

[0006] A light emitting component, electrically connected to the circuit board, comprising:

[0007] The tube shell has an opening formed at an end thereof, wherein an electrical connector is embedded in the opening, and the electrical connector includes a first solder pad surface and a second solder pad surface;

[0008] First laser chip;

[0009] a second laser chip;

[0010] The temperature regulating device is located in the tube shell and includes:

[0011] a first substrate;

[0012] a second substrate, located above the first substrate;

[0013] at least two third substrates, the third substrates being located above the second substrate, wherein a seventh circuit array is formed on the upper surface of one of the third substrates to carry the first laser chip; an eighth circuit array is formed on the upper surface of the other third substrate to carry the second laser chip; a third electrode portion and a fourth electrode portion are embedded in the third substrates respectively; the seventh circuit array includes a first electrical connection portion and a second electrical connection portion, one end of the first electrical connection portion is electrically connected to the positive electrode of the first laser chip, and the other end is electrically connected to the first pad surface; one end of the second electrical connection portion is electrically connected to the negative electrode of the first laser chip, and the other end is electrically connected to the first pad surface; the seventh circuit array includes a third electrical connection portion and a fourth electrical connection portion, one end of the third electrical connection portion is electrically connected to the third electrode portion, and the other end is electrically connected to the second pad surface, and one end of the fourth electrical connection portion is electrically connected to the fourth electrode portion, and the other end is electrically connected to the second pad surface.

[0014] The above technical solution has the following advantages or beneficial effects: The optical module includes a circuit board and a light emitting component. The light emitting component includes a temperature control device, a first laser chip, and a second laser chip. The temperature control device includes a first substrate, a second substrate, and at least two third substrates. A seventh circuit array is formed on the upper surface of the third substrate to support the first laser chip. An eighth circuit array is formed on the upper surface of another third substrate to support the second laser chip, thereby allowing the first laser chip and the second laser chip to be positioned on different surfaces of the third substrate. A third electrode portion and a fourth electrode portion are embedded on the surface of the third substrate. By forming the seventh circuit array on the upper surface of the third substrate, the first laser chip can be directly positioned. The seventh circuit array includes a first electrical connection portion and a second electrical connection portion. One end of the first electrical connection portion is electrically connected to the positive electrode of the first laser chip and the other end is electrically connected to the first solder pad surface, thereby electrically connecting the positive electrode of the first laser chip to the electrical connector. One end of the second electrical connection portion is electrically connected to the negative electrode of the first laser chip and the other end is electrically connected to the first solder pad surface, thereby electrically connecting the negative electrode of the first laser chip to the electrical connector. The seventh circuit array includes a third electrical connection portion and a fourth electrical connection portion. One end of the third electrical connection portion is electrically connected to the third electrode portion, and the other end is electrically connected to the second pad surface, thereby electrically connecting the third electrode portion to the electrical connector. One end of the fourth electrical connection portion is electrically connected to the fourth electrode portion, and the other end is electrically connected to the second pad surface, thereby electrically connecting the fourth electrode portion to the electrical connector. The first and second laser chips can be temperature-adjusted to a target temperature range using the second substrate. Then, using the target temperature range as the reference temperature range, the first laser chip can be independently temperature-adjusted using the third substrate on which the first laser chip is located until the first laser chip is adjusted to the target temperature. Alternatively, the second laser chip can be independently temperature-adjusted using the third substrate on which the second laser chip is located until the second laser chip is adjusted to the target temperature. Because the first and second laser chips are located on different third substrates, temperature tuning of the first or second laser chip can be performed without affecting the temperature of the other laser chip. At the same time, the third substrate where the first laser chip and the second laser chip are located are independent of each other, so the temperature of the first laser chip and the second laser chip can be tuned at the same time, thereby meeting the temperature tuning requirements of the first laser chip and the second laser chip at the same time.

[0015] In some embodiments, a third heat-sensitive portion is formed on the surface of the third substrate carrying the first laser chip, and the third heat-sensitive portion is located on one side of the first laser chip;

[0016] The seventh circuit array includes a fifth electrical connection portion and a sixth electrical connection portion;

[0017] One end of the fifth electrical connection portion is electrically connected to the third thermal sensitive portion, and the other end is electrically connected to the electrical connector; one end of the sixth electrical connection portion is electrically connected to the third thermal sensitive portion, and the other end is electrically connected to the electrical connector.

[0018] The above technical solution has the following advantages or beneficial effects: By providing a third thermal sensor on one side of the first laser chip, the temperature of the first laser chip is monitored. The seventh circuit array includes a fifth electrical connection portion and a sixth electrical connection portion. The fifth electrical connection portion has one end electrically connected to the third thermal sensor and the other end electrically connected to the electrical connector, thereby electrically connecting the positive electrode of the third thermal sensor. The sixth electrical connection portion has one end electrically connected to the third thermal sensor and the other end electrically connected to the electrical connector, thereby electrically connecting the negative electrode of the third thermal sensor.

[0019] In some embodiments, a first electrode portion and a second electrode portion are provided on the surface of the first substrate, and a first circuit array is formed on the upper surface of the first substrate;

[0020] A second circuit array is formed on the lower surface of the second substrate, and a third circuit array and a fourth circuit array are formed on the upper surface, which are independent of each other; wherein the second circuit array is electrically connected to the first circuit array to achieve electrical connection between the second substrate and the first substrate; the surface of the third circuit array carries N-type semiconductor portions and P-type semiconductor portions arranged alternately; and the surface of the fourth circuit array carries N-type semiconductor portions and P-type semiconductor portions arranged alternately.

[0021] A fifth circuit array is formed on the lower surface of one of the third substrates, and the fifth circuit array is electrically connected to the third circuit array, so that the third substrate is located above the N-type semiconductor portion and the P-type semiconductor portion carried on the surface of the third circuit array; a sixth circuit array is formed on the lower surface of the other third substrate, and the sixth circuit array is electrically connected to the fourth circuit array, so that the third substrate is located above the N-type semiconductor portion and the P-type semiconductor portion carried on the surface of the fourth circuit array.

[0022] The above technical solution has the following advantages or beneficial effects: a first circuit array is formed on the upper surface of the first substrate, a second circuit array is formed on the lower surface of the second substrate, and a third circuit array and a fourth circuit array are formed on the upper surface, which are independent of each other. Different circuit arrays are formed on the upper and lower surfaces of the second substrate, respectively, so that the second substrate can be electrically connected to the first substrate downwardly and to the third substrate upwardly. The second circuit array is electrically connected to the first circuit array to achieve electrical connection between the second and first substrates. The surface of the third circuit array is provided with alternating N-type semiconductor portions and P-type semiconductor portions to support one of the third substrates. The surface of the fourth circuit board array is provided with alternating N-type semiconductor portions and P-type semiconductor portions to support another of the third substrates. To achieve electrical connection between one of the third substrates and the second substrate, a fifth circuit array is formed on the surface of the third substrate, and the fifth circuit array is electrically connected to the third circuit array, so that the third substrate is located on the surface of the N-type semiconductor portion and the P-type semiconductor portion supported on the surface of the third circuit array. In order to achieve electrical connection between another third substrate and the second substrate, a sixth circuit array is formed on the surface of the third substrate, and the sixth circuit array is electrically connected to the fourth circuit array, so that the third substrate is located on the surface of the N-type semiconductor portion and the P-type semiconductor portion carried by the surface of the fourth circuit array.

[0023] In some embodiments, the third electrode portion penetrates the third substrate and is connected to one of the N-type semiconductor portions;

[0024] The fourth electrode portion penetrates the third substrate and is electrically connected to one of the P-type semiconductor portions;

[0025] The fourth electrode portion is electrically connected to the third electrode portion through an N-type semiconductor portion and a P-type semiconductor portion distributed between the third substrate and the second substrate.

[0026] The above technical solution has the following advantages or beneficial effects: the first electrode portion is electrically connected to the N-type semiconductor portion, and the second electrode portion is electrically connected to the P-type semiconductor portion, thereby realizing closed-loop transmission of current from the first electrode portion to the second electrode portion.

[0027] In some embodiments, N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the first substrate and the second substrate; N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the second substrate and one of the third substrates;

[0028] The number of N-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of N-type semiconductor portions distributed between the second substrate and one of the third substrates;

[0029] The number of the P-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of the P-type semiconductor portions distributed between the second substrate and one of the third substrates.

[0030] The above technical solution has the following advantages or beneficial effects: the number of N-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of N-type semiconductor portions distributed between the second substrate and one of the third substrates, and the number of P-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of P-type semiconductor portions distributed between the second substrate and one of the third substrates. Therefore, a strong thermoelectric effect exists between the first substrate and the second substrate, and thus, when the first laser chip or the second laser chip is initially adjusted to the target temperature range through the second substrate, the first laser chip or the second laser chip can be quickly adjusted to within the target temperature range.

[0031] In some embodiments, an optical module is provided, comprising:

[0032] circuit boards;

[0033] A light emitting component, electrically connected to the circuit board, comprising:

[0034] The tube shell has an opening formed at an end thereof, and an electrical connector is embedded in the opening;

[0035] First laser chip;

[0036] a second laser chip;

[0037] The temperature regulating device is located in the tube shell and includes:

[0038] a first substrate;

[0039] a second substrate, located above the first substrate;

[0040] A third substrate is located above the second substrate; a third electrode portion and a fourth electrode portion are passed through the surface of the third substrate; an eleventh circuit array is formed on the surface of the third substrate to carry the first laser chip and the second laser chip; the eleventh circuit array includes a first temperature control portion and a second temperature control portion, the first temperature control portion and the second temperature control portion are electrically connected to the electrical connector respectively, the first temperature control portion is located on one side of the first laser chip, and the second temperature control portion is located on one side of the second laser chip; the eleventh circuit array includes a chip positive electrode pad portion and a chip negative electrode pad portion, the chip positive electrode pad portion and the chip negative electrode pad portion are electrically connected to the electrical connector respectively; the eleventh circuit array includes a first via pad portion and a second via pad portion, one end of the first via pad portion is electrically connected to the third electrode portion, and the other end is electrically connected to the electrical connector, one end of the second via pad portion is electrically connected to the fourth electrode portion, and the other end is electrically connected to the electrical connector.

[0041] The above technical solution has the following advantages or beneficial effects: The optical module includes a circuit board and a light emitting component. The light emitting component includes a temperature control device, a first laser chip, and a second laser chip. The temperature control device includes a first substrate, a second substrate, and a third substrate. A third electrode portion and a fourth electrode portion extend through the surface of the third substrate. An eleventh circuit array is formed on the surface of the third substrate to support the first laser chip and the second laser chip, so that the first laser chip and the second laser chip are co-located on the surface of the third substrate. The eleventh circuit array includes a first temperature control portion and a second temperature control portion. The first temperature control portion and the second temperature control portion are each electrically connected to a connector. The first temperature control portion is located on one side of the first laser chip and can independently control the temperature of the first laser chip. The second temperature control portion is located on one side of the second laser chip and can independently control the temperature of the second laser chip. The eleventh circuit array includes a chip positive electrode pad portion and a chip negative electrode pad portion. The chip positive electrode pad portion and the chip negative electrode pad portion are each electrically connected to the electrical connector, thereby electrically connecting the first laser chip to the electrical connector. The eleventh circuit array includes a first via pad portion and a second via pad portion. One end of the first via pad portion is electrically connected to the third electrode portion, and the other end is electrically connected to the electrical connector, thereby electrically connecting the third electrode portion to the electrical connector. One end of the second via pad portion is electrically connected to the fourth electrode portion, and the other end is electrically connected to the electrical connector, thereby electrically connecting the fourth electrode portion to the electrical connector. When temperature adjustment is performed, the temperature of the first laser chip and the second laser chip is adjusted to a first target temperature range by controlling the heating or cooling of the second substrate; then, with the first target temperature range as a reference temperature, the temperature of the first laser chip and the second laser chip is adjusted to a second target temperature range by controlling the heating or cooling of the third substrate; and then, with the second target temperature range as a reference temperature, the first laser chip is independently temperature-tuned by controlling the first temperature control portion to tune the first laser chip to the target temperature, or the second laser chip is independently temperature-tuned by controlling the second temperature control portion to tune the second laser chip to the target temperature. Because the second laser chip is farther away from the first temperature control unit, the temperature of the second laser chip remains unaffected when the first laser chip is independently temperature-controlled by the first temperature control unit. Similarly, when the second laser chip is temperature-controlled, the temperature of the first laser chip remains unaffected. Therefore, when tuning the wavelength, the temperature of either the first or second laser chip can be independently adjusted without affecting each other. Furthermore, because the first and second temperature control units are independent of each other, the temperatures of the first and second laser chips can be tuned simultaneously, thereby meeting the temperature tuning requirements of both.

[0042] In some embodiments, a first thermally sensitive portion is formed between the first laser chip and the second temperature control portion;

[0043] Two pads are formed at both ends of the first thermosensitive portion, and the two pads are electrically connected to the electrical connectors.

[0044] The above technical solution has the following advantages or beneficial effects: the temperature of the first laser chip or the second laser chip can be monitored by the first thermal sensing portion. Two solder pads are formed at each end of the first thermal sensing portion, and the two solder pads are electrically connected to the electrical connector, thereby achieving electrical connection of the first thermal sensing portion.

[0045] In some embodiments, a first electrode portion and a second electrode portion are provided on the surface of the first substrate, and a first circuit array is formed on the upper surface of the first substrate;

[0046] A second circuit array is formed on the lower surface of the second substrate, and a ninth circuit array is formed on the upper surface; wherein the second circuit array is electrically connected to the first circuit array, and the ninth circuit array carries alternating N-type semiconductor portions and P-type semiconductor portions on its surface;

[0047] A tenth circuit array is formed on the lower surface of the third substrate. The tenth circuit array is electrically connected to the ninth circuit array so that the third substrate is disposed above the N-type semiconductor portion and the P-type semiconductor portion carried on the surface of the ninth circuit array.

[0048] The above technical solution has the following advantages or beneficial effects: a first circuit array is formed on the upper surface of the first substrate, a second circuit array is formed on the lower surface of the second substrate, and the first circuit array and the second circuit array are electrically connected to achieve electrical connection between the first and second substrates. A ninth circuit array is formed on the upper surface of the second substrate, and the surface of the ninth circuit array carries alternating N-type semiconductor portions and P-type semiconductor portions. A tenth circuit array is formed on the lower surface of the third substrate, and the tenth circuit array is electrically connected to the ninth circuit array, so that the third substrate is positioned on the N-type semiconductor portions and P-type semiconductor portions carried on the surface of the ninth circuit array, thereby achieving electrical connection between the second and third substrates. A tenth circuit array is formed on the upper surface of the third substrate, and the first laser chip and the second laser chip are respectively located on the surface of the tenth circuit array, so that the first laser chip and the second laser chip are respectively located on the surface of the third substrate.

[0049] In some embodiments, the third electrode portion penetrates the third substrate and is connected to one of the N-type semiconductor portions;

[0050] The fourth electrode portion passes through the third substrate and is electrically connected to one of the P-type semiconductor portions; the fourth electrode portion is electrically connected to the third electrode portion through the N-type semiconductor portion and the P-type semiconductor portion distributed between the third substrate and the second substrate.

[0051] The above technical solution has the following advantages or beneficial effects: the first electrode portion is electrically connected to the N-type semiconductor portion, and the second electrode portion is electrically connected to the P-type semiconductor portion, thereby realizing closed-loop transmission of current from the first electrode portion to the second electrode portion.

[0052] In some embodiments, N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the first substrate and the second substrate; N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the second substrate and one of the third substrates;

[0053] The number of N-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of N-type semiconductor portions distributed between the second substrate and the third substrate;

[0054] The number of the P-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of the P-type semiconductor portions distributed between the second substrate and the third substrate.

[0055] The above technical solution has the following advantages or beneficial effects: the number of N-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of N-type semiconductor portions distributed between the second substrate and the third substrate, and the number of P-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of P-type semiconductor portions distributed between the second substrate and the third substrate. Therefore, there is a strong thermoelectric effect between the first substrate and the second substrate, and thus, when the first laser chip or the second laser chip is initially adjusted to the target temperature range through the second substrate, the first laser chip or the second laser chip can be quickly adjusted to within the target temperature range. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] To more clearly illustrate the technical solutions of the present disclosure, the following briefly describes the drawings used in some embodiments of the present disclosure. Obviously, the drawings described below are merely illustrations of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0057] Figure 1 A partial architecture diagram of an optical communication system provided according to some embodiments of the present disclosure;

[0058] Figure 2 A partial structural diagram of a host computer provided according to some embodiments of the present disclosure;

[0059] Figure 3 A structural diagram of an optical module provided according to some embodiments of the present disclosure;

[0060] Figure 4 An exploded view of an optical module provided according to some embodiments of the present disclosure;

[0061] Figure 5 An overall diagram of a light emitting component provided according to some embodiments of the present disclosure;

[0062] Figure 6A An electrical connector and housing assembly structure provided according to some embodiments of the present disclosure Figure 1 ;

[0063] Figure 6B An electrical connector and housing assembly structure provided according to some embodiments of the present disclosure Figure 2 ;

[0064] Figure 7 A diagram showing the internal structure of a tube shell provided according to some embodiments of the present disclosure;

[0065] Figure 8 An exploded view of the interior of a tube shell provided according to some embodiments of the present disclosure;

[0066] Figure 9A A structural diagram of a temperature control device provided according to some embodiments of the present disclosure;

[0067] Figure 9B A partial exploded view of a temperature control device provided according to some embodiments of the present disclosure;

[0068] Figure 9C Decomposition of a temperature control device according to some embodiments of the present disclosure Figure 1 ;

[0069] Figure 10A A schematic diagram of a surface of a third substrate provided according to some embodiments of the present disclosure;

[0070] Figure 10B A partially enlarged view of a temperature control device provided according to some embodiments of the present disclosure;

[0071] Figure 10C A partially enlarged view of a third substrate provided according to some embodiments of the present disclosure;

[0072] Figure 10D A schematic structural diagram of another temperature control device provided according to some embodiments of the present disclosure;

[0073] Figure 10E Schematic diagram of another temperature control device provided according to some embodiments of the present disclosure Figure 1 ;

[0074] Figure 10FSchematic diagram of another temperature control device provided according to some embodiments of the present disclosure Figure 2 ;

[0075] Figure 10G Schematic diagram of another temperature control device provided according to some embodiments of the present disclosure Figure 3

[0076] Figure 10H A schematic diagram of another surface structure of a third substrate provided according to some embodiments of the present disclosure;

[0077] Figure 11A A cross-sectional structure of a temperature control device provided according to some embodiments of the present disclosure Figure 1 ;

[0078] Figure 11B A cross-sectional structure of a temperature control device provided according to some embodiments of the present disclosure Figure 2 ;

[0079] Figure 12A According to some embodiments of the present disclosure, a first substrate and a second substrate are provided. Figure 1 ;

[0080] Figure 12B According to some embodiments of the present disclosure, a first substrate and a second substrate are provided. Figure 2 ;

[0081] Figure 12C A schematic diagram of current transmission between a first electrode portion and a second electrode portion according to some embodiments of the present disclosure;

[0082] Figure 13A A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 1 ;

[0083] Figure 13B A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 2 ;

[0084] Figure 14 The cross-sectional structure of a temperature control device provided according to some embodiments of the present disclosure is Figure 3 ;

[0085] Figure 15 Decomposition of a temperature control device according to some embodiments of the present disclosure Figure 2 ;

[0086] Figure 16 Decomposition of a temperature control device according to some embodiments of the present disclosure Figure 3 ;

[0087] Figure 17 A schematic diagram of current transmission between a second substrate and a third substrate according to some embodiments of the present disclosure;

[0088] Figure 18A A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 3 ;

[0089] Figure 18B A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 4 ;

[0090] Figure 19 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 1 ;

[0091] Figure 20 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 2 ;

[0092] Figure 21 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 3 ;

[0093] Figure 22 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 4 ;

[0094] Figure 23 A cross-sectional structural diagram of another light emitting component provided according to some embodiments of the present disclosure;

[0095] Figure 24 A partial structural diagram of another light emitting component provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0096] Some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described are only some of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present disclosure are within the scope of protection of the present disclosure.

[0097] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open and inclusive, that is, "including, but not limited to"; the terms "first" and "second" are not to be understood as indicating or implying relative importance or indicating an upper limit on quantity; the term "plurality" means two or more; the term "connected" is to be understood in a broad sense, for example, "connected" can be a fixed connection, a detachable connection, or an integral connection, and can be directly connected or indirectly connected through an intermediate medium; the use of the terms "suitable for" or "configured to" means open and inclusive language, which does not exclude equipment that is suitable for or configured to perform additional tasks or steps; terms such as "parallel", "perpendicular", "same", "consistent", "level" and so on are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges generated in practice, and also include differences based on the same design concept but due to manufacturing reasons.

[0098] In optical communications, information is transferred between information processing devices by loading it onto light and leveraging its propagation speed. This information-carrying light is called an optical signal. Transmitting optical signals through optical information transmission equipment reduces optical power loss, enabling long-distance transmission. Furthermore, optical information transmission equipment, such as optical fiber, is less expensive than electrical information transmission equipment, such as copper wire. Therefore, optical communications technology enables high-speed, long-distance, and low-cost information transmission.

[0099] Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, and televisions. Optical information transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can identify and process electrical signals, while optical communication technology uses optical signals for transmission, requiring optical modules to convert optical and electrical signals.

[0100] Optical modules can enable mutual conversion between optical and electrical signals between information processing equipment and optical information transmission equipment. In some embodiments, at least one of the optical signal input or output ends of the optical module is connected to an optical fiber, and at least one of the electrical signal input or output ends of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber.

[0101] Because multiple information processing devices can transmit information via electrical signals, at least one of the multiple information processing devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is also referred to as the optical module's host computer. Furthermore, the optical signal input or output end of an optical module is referred to as an optical port, while the electrical signal input or output end of an optical module is referred to as an electrical port.

[0102] Figure 1 FIG. 1 is a partial structural diagram of an optical communication system according to some embodiments. Figure 1 As shown, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, an optical module host computer 100, an optical module 200, an optical fiber 101 and a network cable 103, wherein the optical fiber 101 belongs to an optical information transmission device and the network cable 103 belongs to an electrical information transmission device.

[0103] In some embodiments, one end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can undergo total reflection in the optical fiber 101, and the propagation of the optical signal in the direction of total reflection can almost maintain the original optical power. The optical signal undergoes multiple total reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby achieving long-distance information transmission with low power loss.

[0104] The optical communication system includes one or more optical fibers 101. In some embodiments, the optical fibers 101 and the optical module 200 are detachably connected; in some embodiments, the optical fibers 101 and the optical module 200 are non-detachably connected.

[0105] The host computer 100 is configured to provide a data signal to the optical module 200 , or receive a data signal from the optical module 200 , or monitor or control the working state of the optical module 200 .

[0106] The host computer 100 includes a housing for accommodating the optical module 200 and an optical module interface 102 provided on the housing. The optical module 200 is inserted into the housing through the optical module interface 102 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0107] The host computer 100 also includes an external electrical interface that can be connected to an electrical signal network. In some embodiments, the external electrical interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to connect to the network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103.

[0108] One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, so that an electrical signal connection is established between the local information processing device 2000 and the host computer 100 via the network cable 103. In some embodiments, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 via the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted to the remote information processing device 1000 in the optical fiber 101.

[0109] In some embodiments, a first optical signal from a remote information processing device 1000 propagates through an optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to the optical module 200. The optical module 200 converts the first optical signal into a first electrical signal. The optical module 200 transmits the first electrical signal to the host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to the local information processing device 2000.

[0110] In some embodiments, the optical module is a tool for converting optical signals into electrical signals. During the conversion between optical signals and electrical signals, the information does not change, but the encoding or decoding method of the information changes.

[0111] In addition to the optical network terminal, the host computer 100 also includes an optical line terminal (OLT), an optical network device (ONT) or a data center server.

[0112] Figure 2 FIG1 is a partial structural diagram of a host computer according to some embodiments. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. Figure 2As shown, in some embodiments, the host computer 100 further includes a PCB circuit board 105 disposed in the accommodating cavity, and a cage 106 disposed on the surface of the PCB circuit board 105; the optical module 200 is inserted into the cage 106 and fixed by the cage 106;

[0113] In some embodiments, a heat sink 107 is provided on the cage 106 to dissipate heat for the optical module; in some embodiments, the heat sink 107 has a protruding structure such as fins to increase the heat dissipation area.

[0114] In some embodiments, an electrical connector is disposed inside the cage 106 , and the electrical connector is configured to connect to an electrical port of the optical module 200 .

[0115] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100 , and the cage 106 fixes the optical module 200 . The heat generated by the optical module 200 is transferred to the cage 106 and then diffused through the heat sink 107 .

[0116] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100 , and the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106 , thereby establishing an electrical signal connection between the optical module 200 and the host computer 100 .

[0117] In some embodiments, the optical port of the optical module 200 is connected to the optical fiber 101 , so that the optical module 200 establishes an optical signal connection with the optical fiber 101 .

[0118] Figure 3 is a structural diagram of an optical module according to some embodiments. Figure 4 FIG. 1 is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, an optical module 200 includes a housing, which includes an upper housing 201 and a lower housing 202. The upper housing 201 covers the lower housing 202, forming two openings 204 and 205, one of which is an electrical port and the other is an optical port. In some embodiments, the housing forms a single opening that serves as both an electrical port and an optical port.

[0119] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0120] The upper shell 201 and the lower shell 202 are combined to facilitate the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc. into the above shell. The upper shell 201 and the lower shell 202 can encapsulate and protect the above components.

[0121] The direction of the line connecting the two openings 204 and 205 may be consistent with the length direction of the optical module 200, or may be inconsistent with the length direction of the optical module 200. For example, the opening 204 is located at the end of the optical module 200 ( Figure 3 The opening 205 is also located at the end of the optical module 200 ( Figure 3 Alternatively, the opening 204 is located at the end of the optical module 200, while the opening 205 is located at the side of the optical module 200.

[0122] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicular to the base plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0123] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicularly to the base plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and arranged perpendicularly to the cover plate 2011. The two upper side plates are combined with the two lower side plates 2022 to achieve the upper shell 201 covering the lower shell 202.

[0124] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed in a housing. The circuit board 300 includes circuit traces, electronic components, and chips. The electronic components and chips are connected according to the circuit design through the circuit traces to achieve functions such as power supply, electrical signal transmission, and grounding. The electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). The chips may include a microcontroller unit (MCU), a laser driver chip, a transimpedance amplifier (TIA), a limiting amplifier (LA), a clock and data recovery chip (CDR), a power management chip, and a digital signal processing (DSP) chip.

[0125] In some embodiments, the circuit board includes a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also achieve a load-bearing function. For example, the rigid circuit board can stably support the above-mentioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0126] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0127] In some embodiments, the circuit board further includes a gold finger formed on an end surface thereof, wherein the gold finger is composed of a plurality of independent pins.

[0128] In some implementations, the gold finger 301 is disposed on a surface of one side of the circuit board 300 (eg Figure 4 In some implementations, the gold fingers 301 are provided on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to occasions where a large number of pins are required.

[0129] In some implementations, the circuit board's gold fingers extend from opening 204 and insert into an electrical connector on the host computer 100. The circuit board is inserted into cage 106, with gold fingers 301 electrically connected to the electrical connector within cage 106. Gold fingers 301 are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (I2C) signal transmission, and data signal transmission.

[0130] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0131] For example, the unlocking component 600 is located on the outside of the two lower side panels 2022 of the lower housing 202 and includes a snap-fit ​​component that mates with the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the snap-fit ​​component of the unlocking component 600 secures the optical module 200 in the cage 106. When the unlocking component 600 is pulled, the snap-fit ​​component of the unlocking component 600 moves accordingly, thereby changing the connection between the snap-fit ​​component and the host computer, thereby releasing the optical module 200 from the cage 106 and allowing the optical module 200 to be removed from the cage 106.

[0132] In some embodiments, the light module includes a light emitting component 400 .

[0133] In some embodiments, the optical module includes a light receiving component 500 .

[0134] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on a side of the circuit board 300 away from the gold finger 301 .

[0135] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300 and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0136] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on a surface of the circuit board 300 or a side of the circuit board 300.

[0137] Figure 5 This is an overall diagram of a light emitting component provided according to some embodiments of the present disclosure. Figure 5 As shown, in some embodiments, the light emitting component 400 may include a housing 410. The housing 410 has a certain accommodation space to accommodate the optical device.

[0138] In some embodiments, the light emitting component 400 may include a cover plate 420 . The cover plate 420 is connected to the tube package 410 to achieve airtight packaging of the components in the tube package 410 .

[0139] In some embodiments, the light emitting component 400 may include an electrical connector 430 . The electrical connector 430 is located at an end of the housing 410 , and can achieve electrical connection between the components in the housing 410 and the circuit board 300 .

[0140] Figure 6A An electrical connector and housing assembly structure provided according to some embodiments of the present disclosure Figure 1 .like Figure 6A As shown, in some embodiments, an end portion of the tube shell 410 has an opening 411 , and the electrical connector 430 can be embedded in the opening 411 .

[0141] In some embodiments, one end of the electrical connector 430 is located inside the tube shell 410 to be electrically connected to the optical device inside the tube shell 410; the other end of the electrical connector 430 is located outside the tube shell 410 to be electrically connected to the circuit board 300, and thus the electrical connection between the optical device in the tube shell 410 and the circuit board 300 can be achieved through the electrical connector 430.

[0142] In some embodiments, where bonding is required, the end of the electrical connector 430 located within the housing 410 includes a first pad surface 431 and a second pad surface 432 to provide more pads to meet bonding requirements. For example, the first pad surface 431 and the second pad surface 432 can be arranged in a stepped manner to fully utilize the longitudinal space.

[0143] In some embodiments, the first pad surface 431 is used for electrical connection of high-frequency signals, and the second pad surface 432 is used for electrical connection of low-frequency signals.

[0144] In some embodiments, the upper and lower surfaces of the electrical connector 430 located outside the tube shell 410 can form wiring patterns respectively, thereby forming pad surfaces respectively. Figure 5 As shown, the upper and lower surfaces are electrically connected to the first flexible circuit board 300a and the second flexible circuit board 300b respectively. The first flexible circuit board 300a and the second flexible circuit board 300b are electrically connected to the circuit board 300 respectively.

[0145] In some embodiments, the first pad surface 431 is located below the second pad surface 432. The first pad surface 431 is electrically connected to the upper surface of the electrical connector 430 located outside the housing 410, thereby electrically connecting to the second flexible printed circuit board 300b. The second pad surface 432 is electrically connected to the lower surface of the electrical connector 430 located outside the housing 410, thereby electrically connecting to the first flexible printed circuit board 300a.

[0146] Figure 6B An electrical connector and housing assembly structure provided according to some embodiments of the present disclosure Figure 2 .like Figure 6B As shown, in some embodiments, one end of the electrical connector 430 located inside the tube shell 410 includes a first pad surface 431 and a second pad surface 432 to provide more pads to meet wire bonding requirements.

[0147] In some embodiments, electrical connector 430 is located on one of the exterior surfaces of housing 410 to form a third pad surface 433. Third pad surface 433 may be located on the top or bottom surface. For example, a trace pattern is formed on the top surface to form third pad surface 433. Electrical connector 430 is located at one end of the exterior of housing 410, and pads for electrically connecting first pad surface 431 to second pad surface 432 are distributed on third pad surface 433.

[0148] In some embodiments, the first pad surface 431 is used for electrical connection of high frequency signals, and the second pad surface 432 is used for electrical connection of low frequency signals. The third pad surface 433 is flush with the first pad surface 431 to ensure electrical connection between the two, thereby ensuring high frequency signal transmission.

[0149] In some embodiments, the second pad surface 432 is higher than the third pad surface 433. Inside the electrical connector 430, a via portion 434 is formed between the second pad surface 432 and the third pad surface 433. For example, the upward end of the via portion 434 is electrically connected to the second pad surface 432, and the downward end is electrically connected to the third pad surface 433, thereby achieving electrical connection between the second pad surface 432 and the third pad surface 433.

[0150] In some embodiments, the electrical connector 430 is a multi-layer structure, and a via portion 434 is provided between the layer where the second pad surface 432 is located and the layer where the third pad surface 433 is located, and then lamination is performed to form the electrical connector 430 .

[0151] Figure 7 This is a diagram of the internal structure of a tube shell provided according to some embodiments of the present disclosure. Figure 8 This is an exploded view of the interior of a tube shell provided according to some embodiments of the present disclosure. Figure 7 and Figure 8 As shown, in some embodiments, an opening 411 is formed at the end of the tube shell 410 , and an electrical connector 430 is embedded in the opening 411 .

[0152] In some embodiments, the light emitting component 400 may include a laser chip array 440. The laser chip array 440 is located inside the tube housing 410. For example, the laser chip array 440 includes at least a first laser chip 441 and a second laser chip 442. Different laser chips emit light signals of different wavelengths.

[0153] In some embodiments, the wavelength emitted by the laser chip is affected by temperature fluctuations. Therefore, the temperature of the laser chip can be adjusted to ensure that the wavelength emitted by the laser chip reaches the target wavelength. In some optical modules, the accuracy of the wavelength emitted by the laser chip is required to be higher. For example, when using dense wavelength division multiplexing (DWDM) wavelength to achieve multi-channel parallel transmission, the wavelength spacing between adjacent optical channels is very narrow, which also requires higher wavelength accuracy.

[0154] In some embodiments, the light emitting component 400 may include a temperature control device 450. The temperature control device 450 may be located inside the tube housing 410. The laser chips in the laser chip array 440 are located on the surface of the temperature control device 450. By changing the direction and magnitude of the driving current applied to the temperature control device 450, the temperature control device 450 can be controlled to cool or heat the laser chips it carries, thereby regulating the temperature of the laser chips.

[0155] In some embodiments, the temperature control device 450 can adjust the laser chips in the laser chip array 440 to a common target temperature range, and then independently adjust each laser chip. When independently adjusting the temperature of the current laser chip, it will not affect the temperature of other laser chips, thereby adjusting each laser chip to the target temperature to achieve target wavelength tuning.

[0156] In some embodiments, the optical emitting component 400 may include an optical multiplexing assembly 460 . The optical multiplexing assembly 460 may be located inside the housing 410 . The optical multiplexing assembly 460 combines the optical signals of different wavelengths emitted by the first laser chip 441 and the second laser chip 442 into a single optical signal and outputs it along the housing 410 .

[0157] Figure 9A This is a structural diagram of a temperature control device provided according to some embodiments of the present disclosure. Figure 9B This is a partial exploded view of a temperature control device provided according to some embodiments of the present disclosure. Figure 9C Decomposition of a temperature control device according to some embodiments of the present disclosure Figure 1 .like Figures 9A-9C As shown, in some embodiments, the temperature regulating device 450 is used to regulate the temperature of the laser chip.

[0158] In some embodiments, the temperature regulating device 450 may include a first substrate 451 . The first substrate 451 is located at the bottom of the temperature regulating device 450 .

[0159] In some embodiments, the temperature regulating device 450 may include a second substrate 452. The second substrate 452 is located above the first substrate 451, and the two are arranged opposite to each other.

[0160] In some embodiments, the temperature control device 450 may include a third substrate 453. The third substrate 453 is located above the second substrate 452, and the second substrate 452 is also disposed opposite to each other. The surface of the third substrate 453 carries the first laser chip 441 and / or the second laser chip 442.

[0161] In some embodiments, the surface of the third substrate 453 may support at least one laser chip. Figure 9A The third substrate 453 is shown as carrying one laser chip. In some embodiments, the third substrate 453 may also carry two laser chips.

[0162] In some embodiments, taking four-way light emission as an example, when the surface of the third substrate 453 carries one laser chip, four third substrates 453 are respectively disposed above the second substrate 452 to separately carry one of the laser chips. When the surface of the third substrate 453 carries two laser chips, two third substrates 453 are respectively disposed above the second substrate 452.

[0163] In some embodiments, when the first laser chip 441 is disposed on one surface of the third substrate 453 and the second laser chip 442 is disposed on the other surface of the third substrate 453, the first and second laser chips 441, 442 can be individually adjusted to a common target temperature range through heat transfer between the first and second substrates 451, 452. Then, using this target temperature range as a reference temperature, the first laser chip 441 can be independently temperature-regulated to the target temperature through heat transfer between the second substrate 452 and the third substrate 453 where the first laser chip 441 is located. The second laser chip 442 can be independently temperature-regulated to the target temperature through heat exchange between the second substrate 452 and the third substrate 453 where the second laser chip 442 is located. Independent temperature regulation of the first laser chip 441 does not affect the temperature change of the second laser chip 442, and independent temperature regulation of the second laser chip 442 does not affect the temperature change of the first laser chip 441.

[0164] In some embodiments, since the third substrate 453 on which the first laser chip 441 is located and the third substrate 453 on which the second laser chip 442 is located are independent circuits, the temperatures of the first laser chip 441 and the second laser chip 442 can be independently adjusted simultaneously, thereby meeting the temperature tuning requirements of the first laser chip 441 and the second laser chip 442.

[0165] In some embodiments, a circuit pattern consisting of a circuit array is formed on the surface of the third substrate 453 for electrical connection to the first laser chip 441 and / or the second laser chip 442 carried on the surface. The first laser chip 441 and / or the second laser chip 442 can be directly disposed on the surface of the third substrate 453. For example, the surface of the third substrate 453 carries at least one laser chip.

[0166] In some embodiments, the temperature control device 450 may include an N-type semiconductor portion 454 and a P-type semiconductor portion 455. One N-type semiconductor portion 454 and one P-type semiconductor portion 455 are connected in series to form a thermocouple pair. Several alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 form several thermocouple pairs.

[0167] In some embodiments, the N-type semiconductor portion 454 is obtained by doping an intrinsic semiconductor with a pentavalent impurity element, and the P-type semiconductor portion 455 is obtained by doping an intrinsic semiconductor with a trivalent impurity element. The primary charge carriers in the N-type semiconductor portion 454 are electrons, while the primary charge carriers in the P-type semiconductor portion 455 are holes. The carriers in the N-type semiconductor portion 454 and the P-type semiconductor portion 455 move in the same direction. The carriers in the N-type semiconductor portion 454 and the P-type semiconductor portion 455 move in the same direction.

[0168] In some embodiments, a plurality of alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 are distributed between the first substrate 451 and the second substrate 452 , that is, a plurality of thermocouple pairs are distributed between the first substrate 451 and the second substrate 452 , and the plurality of thermocouple pairs are connected in series.

[0169] In some embodiments, the N-type semiconductor portions 454 and the P-type semiconductor portions 455 are arranged in an alternating manner to form a plurality of thermocouple pairs. The N-type semiconductor portion 454 of each thermocouple pair is connected to the P-type semiconductor portion 455 of the next thermocouple pair to form a continuous electrical connection, thereby achieving a series connection.

[0170] In some embodiments, a plurality of alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 are distributed between the second substrate 452 and the third substrate 453 , that is, a plurality of thermocouple pairs are distributed between the second substrate 452 and the third substrate 453 , and the plurality of thermocouple pairs are connected in series.

[0171] In some embodiments, the temperature control device 450 may include a first electrode portion 4561 and a second electrode portion 4562. The first electrode portion 4561 is electrically connected to the second electrode portion 4562 via a plurality of thermocouple pairs connected in series between the first substrate 451 and the second substrate 452. Current flowing into the first electrode portion 4561 sequentially travels up and down through each of the series-connected thermocouple pairs to reach the second electrode portion 4562.

[0172] In some embodiments, the first electrode portion 4561 is electrically connected to the N-type semiconductor portion 454 , and the second electrode portion 4562 is electrically connected to the P-type semiconductor portion 455 .

[0173] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 are each electrically connected to a current source on the surface of the circuit board 300, thereby supplying power to the thermocouple pair between the first substrate 451 and the second substrate 452. By adjusting the direction and magnitude of the supplied current, the direction and magnitude of heat transfer between the first substrate 451 and the second substrate 452 can be changed, thereby controlling the temperature of the second substrate 452.

[0174] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 may be located on the surface of the first substrate 451. For example, the first substrate 451 is longer than the second substrate 452, so that the first electrode portion 4561 and the second electrode portion 4562 are located at the ends of the first substrate 451.

[0175] In some embodiments, the temperature control device 450 may include a third electrode portion 4571 and a fourth electrode portion 4572. The third electrode portion 4571 is electrically connected to the fourth electrode portion 4572 via a plurality of thermocouple pairs connected in series between the second substrate 452 and the third substrate 453. Current flowing into the third electrode portion 4571 sequentially travels up and down through each of the series-connected thermocouple pairs before reaching the fourth electrode portion 4572.

[0176] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 are respectively located in the third substrate 453. The third electrode portion 4571 and the fourth electrode portion 4572 are formed by punching holes in the third substrate 453, thereby reducing the occupied space and rationally deploying the third electrode portion 4571 and the fourth electrode portion 4572.

[0177] In some embodiments, the third electrode portion 4571 is electrically connected to the N-type semiconductor portion 454 , and the fourth electrode portion 4572 is electrically connected to the P-type semiconductor portion 455 .

[0178] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 are respectively electrically connected to a current source on the surface of the circuit board 300, thereby supplying power to the thermocouple pair between the second substrate 452 and the third substrate 453. By adjusting the direction and magnitude of the supplied current, the direction of heat transfer between the second substrate 452 and the third substrate 453 can be changed, thereby controlling the temperature of the third substrate 453.

[0179] In some embodiments, the direction of heat transfer between the first substrate 451 and the second substrate 452 can be controlled by changing the direction of carrier movement in the N-type semiconductor portion 454 and the P-type semiconductor portion 455 between the first substrate 451 and the second substrate 452. Similarly, the direction of heat transfer between the second substrate 452 and the third substrate 453 can be controlled by changing the direction of carrier movement in the N-type semiconductor portion 454 and the P-type semiconductor portion 455 between the second substrate 452 and the third substrate 453.

[0180] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 may be respectively located in the third substrate 453. For example, via holes are formed through the third substrate 453, and the via holes are filled with a metal dielectric to form the third electrode portion 4571 and the fourth electrode portion 4572.

[0181] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 can be electrically connected to the second pad surface 432 as the positive electrode and the negative electrode, respectively. The second pad surface 432 is electrically connected to the third pad surface 433. The third pad surface 433 is electrically connected to the driver chip on the circuit board 300, which is electrically connected to the thermostat 450, via the flexible circuit board. Thus, the first electrode portion 4561 and the second electrode portion 4562 are electrically connected to the driver chip. An external power source supplies power to the circuit board 300 through the gold finger 301. The circuit board 300 supplies power to the driver chip, which in turn supplies power to the first electrode portion 4561 and the second electrode portion 4562.

[0182] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 can be electrically connected to the second pad surface 432 as the positive electrode and the negative electrode, respectively. The power supply connection method of the third electrode portion 4571 and the fourth electrode portion 4572 can be the same as the power supply connection method of the first electrode portion 4561 and the second electrode portion 4562 described above.

[0183] In some embodiments, by changing the direction and size of the current source electrically connected to the first electrode portion 4561 and the second electrode portion 4562, the temperature of the second substrate 452 can be controlled so that the temperature of the second substrate 452 cools or heats the laser chip, thereby tuning the reference temperature of the laser chip on the surface of the third substrate 453.

[0184] In some embodiments, a second thermal sensing portion 458 is provided on the surface of the second substrate 452 to monitor the temperature of the second substrate 452. The second thermal sensing portion 458 is relatively temperature-sensitive, and changes in the ambient temperature will cause its resistance to change. The MCU collects the resistance of the second thermal sensing portion 458 and converts the temperature characteristic of the resistance changing with temperature into an electrical signal. Based on the electrical signal, the MCU controls a driver chip electrically connected to the thermostat 450, thereby controlling the direction and magnitude of the current provided by the driver chip to the first electrode portion 4561 and the second electrode portion 4562, thereby controlling the temperature of the second substrate 452, so that the second substrate 452 adjusts the reference temperature of the first laser chip 441, thereby tuning the temperature of the first laser chip 441 to the target temperature range.

[0185] In some embodiments, the second thermal-sensitive portion 458 may be a thermistor.

[0186] Figure 10A FIG. 1 is a schematic diagram of a third substrate surface provided according to some embodiments of the present disclosure. Figure 10A As shown, in some embodiments, the temperature regulating device 450 includes a third substrate 453a. A circuit pattern is formed on the surface of the third substrate 453a to support the laser chip.

[0187] In some embodiments, the laser chip array includes a first laser chip 441 and a second laser chip 442. The first laser chip 441 is located on a surface of one of the third substrates 453a, and the second laser chip 442 is located on a surface of the other third substrate 453a.

[0188] In some embodiments, a seventh circuit array 453e is formed on the upper surface of one third substrate 453a to support the first laser chip 441. An eighth circuit array is formed on the upper surface of the other third substrate 453a to support the second laser chip 442. By way of example, the structures of the seventh circuit array 453e and the eighth circuit array may be identical or different. The following description will use the example of an identical structure for both circuit arrays.

[0189] In some embodiments, the first laser chip 441 is located on a surface of the seventh circuit array 453 e , and the second laser chip 442 is located on a surface of the eighth circuit array.

[0190] In some embodiments, the seventh circuit array 453e includes a first electrical connection portion 4531 and a second electrical connection portion 4532. The first electrical connection portion 4531 and the second electrical connection portion 4532 are respectively connected to the electrical connector 430 by wire bonding.

[0191] In some embodiments, the first electrical connection portion 4531 is used for signal connection of the first laser chip 441 , and the second electrical connection portion 4532 is used for ground connection of the first laser chip 441 .

[0192] In some embodiments, one end of the first electrical connection portion 4531 is electrically connected to the positive electrode of the first laser chip 441, and the other end is electrically connected to the first pad surface 431; one end of the second electrical connection portion 4532 is electrically connected to the negative electrode of the first laser chip 441, and the other end is electrically connected to the first pad surface 431.

[0193] In some embodiments, a third electrode portion 4571 and a fourth electrode portion 4572 are embedded in the third substrate 453a. The third electrode portion 4571 is electrically connected downward to the N-type semiconductor portion 454, and the fourth electrode portion 4572 is electrically connected downward to the P-type semiconductor portion 455.

[0194] In some embodiments, the seventh circuit array 453e includes a third electrical connection portion 4533 and a fourth electrical connection portion 4534. The third electrical connection portion 4533 and the fourth electrical connection portion 4534 are respectively wire-bonded to the electrical connector 430. The third electrical connection portion 4533 is used for wire-bonding the third electrode portion 4571 to the electrical connector 430, and the fourth electrical connection portion 4534 is used for wire-bonding the fourth electrode portion 4572 to the electrical connector 430.

[0195] In some embodiments, one end of the third electrical connection portion 4533 is electrically connected to the third electrode portion 4571, and the other end is electrically connected to the second pad surface 432; one end of the fourth electrical connection portion 4534 is electrically connected to the fourth electrode portion 4572, and the other end is electrically connected to the second pad surface 432.

[0196] In some embodiments, a third thermally sensitive portion 4535 is formed on the surface of the third substrate 453a for monitoring the temperature of the first laser chip 441. For example, the third thermally sensitive portion 4535 is a thermistor wire.

[0197] In some embodiments, the third thermal sensing portion 4535 is sensitive to temperature, and changes in the ambient temperature can cause changes in its resistance. The MCU collects the resistance of the third thermal sensing portion 4535 and converts the temperature characteristic of the resistance changing with temperature into an electrical signal. Based on the electrical signal, the MCU controls a driver chip electrically connected to the thermostat 450, thereby controlling the direction and magnitude of the current provided by the driver chip to the third electrode portion 4571 and the fourth electrode portion 4572, thereby controlling the temperature of the third substrate 453a, thereby further tuning the temperature of the laser chip on the surface of the third substrate 453a to ensure the accuracy of the laser chip's output wavelength.

[0198] In some embodiments, the seventh circuit array 453 e includes a fifth electrical connection portion 4536 and a sixth electrical connection portion 4537 .

[0199] In some embodiments, the fifth electrical connection portion 4536 is electrically connected to the third thermal sensing portion 4535 at one end and to the electrical connector 430 at the other end. The sixth electrical connection portion 4537 is electrically connected to the third thermal sensing portion 4535 at one end and to the electrical connector 430 at the other end.

[0200] In some embodiments, the fifth electrical connection portion 4536 is used to electrically connect the positive electrode of the third thermal sensitive portion 4535 to the electrical connector 430 , and the sixth electrical connection portion 4537 is used to electrically connect the negative electrode of the third thermal sensitive portion 4535 to the electrical connector 430 .

[0201] Figure 10B This is a partially enlarged view of a temperature control device provided according to some embodiments of the present disclosure. Figure 10C This is a partial enlarged view of a third substrate provided according to some embodiments of the present disclosure. Figure 10B and Figure 10C As shown, in some embodiments, a third electrode portion 4571 and a fourth electrode portion 4572 are respectively embedded in the third substrate 453a.

[0202] In some embodiments, the third electrode portion 4571 is electrically connected to the N-type semiconductor portion 454 , and the fourth electrode portion 4572 is electrically connected to the P-type semiconductor portion 455 .

[0203] In some embodiments, the N-type semiconductor portion 454 electrically connected to the third electrode portion 4571 and the P-type semiconductor portion 455 electrically connected to the fourth electrode portion 4572 are respectively located on different pads of the second substrate 452 and also on different pads of the third substrate 453a.

[0204] In some embodiments, the third electrode portion 4571 is located at one end of the top surface of the third substrate 453a and is electrically connected to the electrical connector 430 through the third electrical connection portion 4533, and the third electrode portion 4571 is located at one end of the bottom surface of the third substrate 453a and is electrically connected to the N-type semiconductor portion 454.

[0205] In some embodiments, the fourth electrode portion 4572 is located at one end of the top surface of the third substrate 453a and is electrically connected to the electrical connector 430 through the fourth electrical connection portion 4534, and the fourth electrode portion 4572 is located at one end of the bottom surface of the third substrate 453a and is electrically connected to the P-type semiconductor portion 455.

[0206] In some embodiments, the current source on the surface of the circuit board 300 is electrically connected to the third electrode portion 4571 and the fourth electrode portion 4572 via the electrical connector 430. For example, the third electrode portion 4571 serves as the positive electrode, and the fourth electrode portion 4572 serves as the negative electrode. When the current source is a positive current source, the current is transmitted to the third electrode portion 4571 via the electrical connector 430, and then to the N-type semiconductor portion 454 electrically connected to the third electrode portion 4571. The current is then transmitted in sequence along the P-type semiconductor portion 455 and the N-type semiconductor portion 454 connected in series until it reaches the P-type semiconductor portion 455 electrically connected to the fourth electrode portion 4572, and then transmitted to the fourth electrode portion 4572.

[0207] The third substrate 453a has a first via hole 4538 and a second via hole 4539. The first via hole 4538 and the second via hole 4539 respectively penetrate the third substrate 453a. For example, the depth of the first via hole 4538 and the second via hole 4539 is equal to the thickness of the third substrate 453a.

[0208] In some embodiments, the first via portion 4538 and the second via portion 4539 are respectively filled with metal dielectrics to form a third electrode portion 4571 and a fourth electrode portion 4572 , respectively.

[0209] In some embodiments, the first laser chip 441 and the second laser chip 442 are individually adjusted to a common target temperature range through heat transfer between the first substrate 451 and the second substrate 452. Alternatively, they can be tuned to different temperature ranges. The target temperature range is then used as a reference temperature. The first laser chip 441 is independently temperature-regulated to the target temperature through heat transfer between the second substrate 452 and the third substrate 453 on which the first laser chip 441 is located. The second laser chip 442 is independently temperature-regulated to the target temperature through heat exchange between the second substrate 452 and the third substrate 453 on which the second laser chip 442 is located.

[0210] In some embodiments, the number of N-type semiconductor portions 454 distributed between the first substrate 451 and the second substrate 452 exceeds the number of N-type semiconductor portions 454 distributed between the second substrate 452 and one of the third substrates 453 a , and the number of P-type semiconductor portions 455 distributed between the first substrate 451 and the second substrate 452 exceeds the number of P-type semiconductor portions 455 distributed between the second substrate 452 and one of the third substrates 453 a . Therefore, the number of thermocouple pairs distributed between the first substrate 451 and the second substrate 452 is proportional to the number of thermocouple pairs distributed between the second substrate 452 and one of the third substrates 453 a . Therefore, the thermoelectric effect between the first substrate 451 and the second substrate 452 is stronger than the thermoelectric effect between the second substrate 452 and one of the third substrates 453 a . Consequently, heat transfer between the first substrate 451 and the second substrate 452 can quickly adjust the first laser chip 441 and the second laser chip 442 to a common target temperature range, thereby improving the speed.

[0211] In some embodiments, the size of the N-type semiconductor portion 454 distributed between the first substrate 451 and the second substrate 452 is larger than the size of the N-type semiconductor portion 454 distributed between the second substrate 452 and one of the third substrates 453 a , and the size of the P-type semiconductor portion 455 distributed between the first substrate 451 and the second substrate 452 is larger than the size of the P-type semiconductor portion 455 distributed between the first substrate 451 and the second substrate 452 and one of the third substrates 453 a . This can also increase the thermoelectric effect between the first substrate 451 and the second substrate 452 , thereby increasing the rate at which the first laser chip 441 and the second laser chip 442 are adjusted to a common target temperature range.

[0212] Figure 10D This is a schematic diagram of another temperature control device structure provided according to some embodiments of the present disclosure. Figure 10E Schematic diagram of another temperature control device provided according to some embodiments of the present disclosure Figure 1 .like Figure 10D and 10EAs shown, in some embodiments, the temperature regulating device 450 includes a third substrate 453b.

[0213] In some embodiments, a circuit pattern is formed on the surface of the third substrate 453b to support the laser chip.

[0214] In some embodiments, the surface of the third substrate 453b can support two laser chips. Taking a four-way emission array as an example, the laser chip array 440 includes a first laser chip 441, a second laser chip 442, a third laser chip 443, and a fourth laser chip 444. The first laser chip 441 and the second laser chip 442 are co-located on the surface of one third substrate 453b, while the third laser chip 443 and the fourth laser chip 444 are co-located on the surface of the other third substrate 453b.

[0215] In some embodiments, when the temperature control device 450 includes the third substrate 453b, the electrical connection between the first substrate 451 and the second substrate 452 is the same as when the temperature control device 450 includes the third substrate 453a. The electrical connection between the second substrate 452 and the third substrate 453a is the same as the electrical connection between the second substrate 452 and the third substrate 453b.

[0216] In some embodiments, since the length of the third substrate 453b is greater than that of the third substrate 453a, the number of N-type semiconductor portions 454 and P-type semiconductor portions 455 distributed between the second substrate 452 and the third substrate 453b is greater than that between the second substrate 452 and the third substrate 453a.

[0217] In some embodiments, to control the cooling or heating of the third substrate 453b, a third electrode portion 4571b and a fourth electrode portion 4572b are formed through one side of the third substrate 453b. The third electrode portion 4571b is electrically connected to the fourth electrode portion 4572b via the N-type semiconductor portions 454 and P-type semiconductor portions 455 alternately disposed between the third substrate 453b and the second substrate 452. By varying the direction and magnitude of the current transmitted within the alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 between the second substrate 452 and the third substrate 453b, the cooling or heating effect of the third substrate 453b can be controlled.

[0218] In some embodiments, the configuration and electrical connection of the third electrode portion 4571b and the fourth electrode portion 4572b in the third substrate 453b may be the same as the configuration and electrical connection of the third electrode portion 4571 and the fourth electrode portion 4572 in the third substrate 453a.

[0219] Figure 10F Schematic diagram of another temperature control device provided according to some embodiments of the present disclosure Figure 2 , Figure 10G Schematic diagram of another temperature control device provided according to some embodiments of the present disclosure Figure 3 , Figure 10H FIG. 1 is a schematic diagram of another surface structure of a third substrate provided according to some embodiments of the present disclosure. Figures 10F-10H As shown, in some embodiments, the surface of the third substrate 453 b carries a first laser chip 441 and a second laser chip 442 .

[0220] In some embodiments, a ninth circuit array 452d is formed on the upper surface of the second substrate 452. In some embodiments, a tenth circuit array 453f is formed on the lower surface of the third substrate 453b. Alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 are arranged between the ninth circuit array 452d and the tenth circuit array 453f to support the third substrate 453b.

[0221] In some embodiments, the pad portions of the ninth circuit array 452 d and the tenth circuit array 453 f are staggered to achieve electrical connection, thereby achieving a series connection of the alternately arranged N-type semiconductor portions 454 and P-type semiconductor portions 455 .

[0222] In some embodiments, an eleventh circuit array 453 g is formed on the upper surface of the third substrate 453 b .

[0223] In some embodiments, the first laser chip 441 and the second laser chip 442 are respectively disposed on a surface of the eleventh circuit array 453 g .

[0224] In some embodiments, the eleventh circuit array 453 g may include a first temperature control unit 4531 b located on one side of the first laser chip 441 to heat or cool the first laser chip 441 independently.

[0225] In some embodiments, the eleventh circuit array 453 g may include a second temperature control unit 4532 b located on one side of the second laser chip 442 to independently heat or cool the second laser chip 442 .

[0226] In some embodiments, the eleventh circuit array 453 g may include a first thermal sensing portion 4533 b configured to monitor the temperatures of the first laser chip 441 and the second laser chip 442 .

[0227] In some embodiments, to monitor the temperatures of both the first laser chip 441 and the second laser chip 442, the first thermal sensing portion 4533b is located between the first laser chip 441 and the second laser chip 442. For example, the first thermal sensing portion 4533b is located between the first temperature control portion 4531b and the second temperature control portion 4532b.

[0228] In some embodiments, the first thermal portion 4533 b is located in the middle of the third substrate 453 b , with the first laser chip 441 on one side of the first thermal portion 4533 b and the second temperature control portion 4532 b on the other side.

[0229] In some embodiments, during temperature adjustment, the first laser chip 441 and the second laser chip 442 are individually adjusted to a first target temperature range via the second substrate 452 by controlling the heating or cooling of the first substrate 451 and the second substrate 452. Then, using the first target temperature range as a reference temperature, the third substrate 453 is controlled to heat or cool the first laser chip 441 and the second laser chip 442 to a second target temperature range. Furthermore, using the second target temperature range as a reference temperature, the first laser chip 441 is independently temperature-controlled by the first temperature control unit 4531b to tune the first laser driver chip 441 to the target temperature, or the second laser chip 442 is independently temperature-controlled by the second temperature control unit 4532b to tune the second laser driver chip 442 to the target temperature. Because the second laser chip 442 is located farther from the first temperature control unit 4531b, the temperature of the second laser chip 442 is not affected by the independent temperature adjustment of the first laser chip 441 by the first temperature control unit 4531b. Likewise, when the temperature of the second laser chip 442 is adjusted, the temperature of the first laser chip 441 is not affected. Therefore, when tuning the wavelength, the temperature of the first laser chip 441 or the second laser chip 442 can be adjusted independently to avoid affecting the temperature of the other laser chip.

[0230] In some embodiments, since the first temperature control unit 4531 b and the second temperature control unit 4532 b are independent circuits, the temperatures of the first laser chip 441 and the second laser chip 442 can be independently adjusted simultaneously.

[0231] In some embodiments, the first temperature control portion 4531b may be a resistance wire, and the two ends of the first temperature control portion 4531b respectively form two solder pad portions to achieve positive and negative electrical connection of the first temperature control portion 4531b. For example, one end is electrically connected to the surface of the first solder pad surface 431, and the other end is electrically connected to the surface of the second solder pad surface 432.

[0232] In some embodiments, the second temperature control portion 4532b may be a resistance wire, and two solder pads are formed at each end of the second temperature control portion 4532b to achieve positive and negative electrical connection of the second temperature control portion 4532b. For example, one end is electrically connected to the surface of the first solder pad surface 431, and the other end is electrically connected to the surface of the second solder pad surface 432.

[0233] In some embodiments, two pads are formed at each end of the first thermally sensitive portion 4533b to achieve electrical connection between the positive and negative terminals of the first thermally sensitive portion 4533b. For example, one end is electrically connected to the surface of the first pad surface 431, and the other end is electrically connected to the surface of the second pad surface 432.

[0234] In some embodiments, the eleventh circuit array 453g may include a positive chip pad portion 4534b and a negative chip pad portion 4535b, each electrically connected to the electrical connector 430.

[0235] In some embodiments, the positive electrode pad portion 4534b is used to connect the positive electrode of the first laser chip 441, and the negative electrode pad portion 4535b is used to connect the negative electrode of the first laser chip 441. Exemplarily, the positive electrode pad portion 4534b and the negative electrode pad portion 4535b are electrically connected to the surface of the first pad surface 431.

[0236] In some embodiments, the eleventh circuit array 453g may include a first via pad portion 4536b and a second via pad portion 4537b. The first via pad portion 4536b has one end electrically connected to the third electrode portion 4571 and the other end electrically connected to the electrical connector 430. The second via pad portion 4537b has one end electrically connected to the fourth electrode portion 4572 and the other end electrically connected to the electrical connector 430.

[0237] In some embodiments, the first via pad portion 4536b is used to electrically connect to the third electrode portion 4571, and the second via pad portion 4537b is used to electrically connect to the fourth electrode portion 4572. For example, one of the first via pad portion 4536b and the second via pad portion 4537b is electrically connected to the first pad surface 431, and the other is electrically connected to the second pad surface 432.

[0238] In some embodiments, the surface of the first via pad portion 4536b extends downwardly to form a first via portion, which is then filled with a metal dielectric to form a third electrode portion 4571. The surface of the second via pad portion 4537b extends downwardly to form a second via portion, which is then filled with a metal dielectric to form a fourth electrode portion 4572.

[0239] Figure 11A A cross-sectional structure of a temperature control device provided according to some embodiments of the present disclosure Figure 1 , Figure 11B A cross-sectional structure of a temperature control device provided according to some embodiments of the present disclosure Figure 2 .like Figure 11A and Figure 11B As shown, in some embodiments, the temperature control device 450 includes a first electrode portion 4561 and a second electrode portion 4562 .

[0240] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 may be respectively located on the surface of the first substrate 451 .

[0241] In some embodiments, the first electrode portion 4561 is electrically connected to the second electrode portion 4562 via thermocouple pairs distributed between the first substrate 451 and the second substrate 452. For example, a forward current source is transmitted to the temperature control device 450, starting from the first electrode portion 4561 and passing through the series-connected thermocouple pairs to reach the second electrode portion 4562. Specifically, an N-type semiconductor portion 454 and a P-type semiconductor portion 455 are connected in series to form a thermocouple pair.

[0242] In some embodiments, the first electrode portion 4561 is electrically connected to the N-type semiconductor portion 454 . The first electrode portion 4561 and the N-type semiconductor portion 454 are co-located on a pad portion on the surface of the first substrate 451 .

[0243] In some embodiments, the second electrode portion 4562 is electrically connected to the P-type semiconductor portion 455 . The second electrode portion 4562 and the P-type semiconductor portion 455 are co-located on another pad portion on the surface of the first substrate 451 .

[0244] In some embodiments, when the current source is a positive current source, the current flows out through the first electrode portion 4561 and is transmitted to the N-type semiconductor portion 454 located on the same pad as the first electrode portion 4561. The current then continues to be transmitted to the P-type semiconductor portion 455 located on the same pad as the N-type semiconductor portion 454, flows through each thermocouple pair, and finally flows into the second electrode portion 4562 through the P-type semiconductor portion 455 located on the same pad as the second electrode portion 4562. When the current source is a negative current source, the current is transmitted along the opposite path.

[0245] Figure 12A According to some embodiments of the present disclosure, a first substrate and a second substrate are provided. Figure 1 , Figure 12B According to some embodiments of the present disclosure, a first substrate and a second substrate are provided. Figure 2 , Figure 12C Schematic diagram of current transmission between a first electrode portion and a second electrode portion according to some embodiments of the present disclosure. Figures 12A-12C As shown, in some embodiments, multiple thermocouple pairs are distributed between the first substrate 451 and the second substrate 452, and the multiple thermocouple pairs are connected in series. An N-type semiconductor portion 454 and a P-type semiconductor portion 455 are connected in series to form a thermocouple pair.

[0246] In some embodiments, each thermocouple pair connected in series is located between the first electrode portion 4561 and the second electrode portion 4562. When the current source is a forward current source, current flows from the first electrode portion 4561, along the N-type semiconductor portion 454 and the P-type semiconductor portion 455, and then through each thermocouple pair until it reaches the second electrode portion 4562.

[0247] In some embodiments, by adjusting the direction and magnitude of the current flow, adjusting the direction of carrier movement in the N-type semiconductor portion 454 and the P-type semiconductor portion 455, and then adjusting the direction of heat transfer between the first substrate 451 and the second substrate 452, the temperature of the second substrate 452 can be controlled, so that the second substrate 452 has a cooling or heating function, thereby adjusting the temperature of the laser chip carried on the surface of the third substrate 453a to within the target temperature range, and taking the target temperature range as the reference temperature.

[0248] In some embodiments, a first circuit array 451a is formed on the upper surface of the first substrate 451, and a second circuit array 452a is formed on the lower surface of the second substrate 452. The first circuit array 451a and the second circuit array 452a are arranged vertically opposite each other and are electrically connected. For example, the first circuit array 451a includes a plurality of pad portions, and the second circuit array 452a includes a plurality of pad portions.

[0249] In some embodiments, multiple thermocouple pairs are distributed between the first circuit array 451a and the second circuit array 452a. The pads between the first circuit array 451a and the second circuit array 452a are arranged in an interlaced manner. By interoperating with the pads on the surfaces of the first substrate 451 and the second substrate 452, the thermocouple pairs can be connected in series, thereby achieving electrical connection between the first substrate 451 and the second substrate 452.

[0250] In some embodiments, the top ends of the N-type semiconductor portion 454 and the P-type semiconductor portion 455 in the first thermocouple pair are located at the same pad on the surface of the second substrate 452, the bottom ends of the P-type semiconductor portion 455 in the first thermocouple pair and the N-type semiconductor portion 454 in the second thermocouple pair are located at the same pad on the surface of the first substrate 451, the top ends of the N-type semiconductor portion in the second thermocouple pair and the P-type semiconductor portion 455 in the second thermocouple pair are located at the same pad on the surface of the second substrate 452, and the P-type semiconductor portion in the second thermocouple pair is located at the same pad on the surface of the second substrate 452. The body 455 and the bottom end of the N-type semiconductor portion 454 in the third thermocouple pair are located at a soldering pad on the surface of the first substrate 451, and the top end of the N-type semiconductor portion 454 in the third thermocouple pair and the P-type semiconductor portion 455 in the end of the third thermocouple pair are located at a soldering pad on the surface of the second substrate 452. In this way, the thermocouple pairs are connected in series through the soldering pads arranged alternately on the surfaces of the first substrate 451 and the second substrate 452, and then the N-type semiconductor portions 454 and the P-type semiconductor portions 455 are connected into a line.

[0251] In some embodiments, to illustrate the electrical connection between the first electrode portion 4561, each thermocouple pair, and the second electrode portion 4562, the first circuit array 451a illustratively includes a first pad portion 4511, a second pad portion 4512, a third pad portion 4513, a fourth pad portion 4514, and the like. Exemplarily, one end of the second pad portion 4512 faces the first pad portion 4511, and the other end faces the third pad portion 4513. Multiple pad portions are provided between the third pad portion 4513 and the fourth pad portion 4514.

[0252] In some embodiments, the first electrode portion 4561 is located on the surface of the first pad portion 4511 , and the second electrode portion 4562 is located on the surface of the fourth pad portion 4514 . The first pad portion 4511 and the fourth pad portion 4514 are located on the same end of the first substrate 451 .

[0253] In some embodiments, to illustrate the electrical connection between the first electrode portion 4561, each thermocouple pair, and the second electrode portion 4562, the second circuit array 452a illustratively includes a fifth pad portion 4521, a sixth pad portion 4522, a seventh pad portion 4523, a ninth pad portion 4524, etc. The fifth pad portion 4521 is arranged in an alternating pattern with the first pad portion 4511, the sixth pad portion 4522 is arranged in an alternating pattern with the second pad portion 4512, and the seventh pad portion 4523 is arranged in an alternating pattern with the third pad portion 4513.

[0254] In some embodiments, to illustrate the electrical connection between the first electrode portion 4561, each thermocouple pair, and the second electrode portion 4562, illustratively, a first N-type semiconductor portion 454a, a second N-type semiconductor portion 454b, a third N-type semiconductor portion 454c, and the like are distributed between the first substrate 451 and the second substrate 452. Multiple N-type semiconductor portions are respectively provided between the second N-type semiconductor portion 454b and the third N-type semiconductor portion 454c. In some embodiments, to illustrate the electrical connection between the first electrode portion 4561, each thermocouple pair, and the second electrode portion 4562, illustratively, a first P-type semiconductor portion 455a and a second P-type semiconductor portion 455b are distributed between the first substrate 451 and the second substrate 452. Multiple P-type semiconductor portions are distributed between the first P-type semiconductor portion 455a and the second P-type semiconductor portion 455b.

[0255] In some embodiments, the first N-type semiconductor portion 454a and the first P-type semiconductor portion 455a constitute a first thermocouple pair, the first P-type semiconductor portion 455a and the second N-type semiconductor portion 454b constitute a second thermocouple pair, the second N-type semiconductor portion 454b and the second P-type semiconductor portion 455b constitute a third thermocouple pair, and the second P-type semiconductor portion 455b and the third N-type semiconductor portion 454c constitute a fourth thermocouple pair, as follows.

[0256] In some embodiments, the first electrode portion 4561 and the first N-type semiconductor portion 454a are respectively located on the surface of the first pad portion 4511 on the first substrate 451. The first N-type semiconductor portion 454a and the first P-type semiconductor portion 455a are co-located on the surface of the fifth pad portion 4521 on the second substrate 452. The first P-type semiconductor portion 455a and the second N-type semiconductor portion 454b are co-located on the surface of the second pad portion 4512 on the first substrate 451. Thus, the second N-type semiconductor portion 454b and the next P-type semiconductor portion are co-located on a pad portion on the surface of the second substrate 452. The P-type semiconductor portion is in turn co-located with the next N-type semiconductor portion on a pad portion on the surface of the first substrate 451. In this manner, each thermocouple pair is sequentially connected in series.

[0257] In some embodiments, the first electrode portion 4561 and the first N-type semiconductor portion 454a are respectively located on the surface of the first pad portion 4511 on the first substrate 451. The second electrode portion 4562 is electrically connected to the adjacent P-type semiconductor portion 455, and both are respectively located on the surface of the fourth pad portion 4514 on the first substrate 451. The first pad portion 4511 is used to provide a surface size of the first electrode portion 4561 that is larger than the surface size of the first N-type semiconductor portion 454a. The fourth pad portion 4514 is used to provide a surface size of the second electrode portion 4562 that is larger than the surface size of the corresponding P-type semiconductor portion 455.

[0258] In some embodiments, when the current source is a positive current source, current flows out of the first electrode portion 4561, flows upward into the first N-type semiconductor portion 454a located on the same pad portion as the first electrode portion 4561, then flows downward into the first P-type semiconductor portion 455a located on the same fifth pad portion 4521 as the first N-type semiconductor portion 454a, then flows upward into the second N-type semiconductor portion 454b located on the same pad portion as the first P-type semiconductor portion 455a, and the current continues to shuttle up and down. Until the current flows upward into the second N-type semiconductor portion 454c, then flows downward to the second P-type semiconductor portion 455b located on the same ninth pad portion 4524 as the second N-type semiconductor portion 454c, and then flows upward to the second electrode portion 4562 located on the same pad portion as the second P-type semiconductor portion 455b, achieving a closed-loop current transmission. When the current source is a negative current source, the current is transmitted in the opposite direction.

[0259] like Figure 12C As shown, the N-type semiconductor portion 454 and the P-type semiconductor portion 455 are provided on the surface of the pad portion. The pad portion indicated by the dotted line is the pad portion on the lower surface of the second substrate 452, and the pad portion indicated by the solid line is the pad portion on the upper surface of the first substrate 451. The N-type semiconductor portion 454 and the P-type semiconductor portion 455 are arranged in an alternating manner to form a plurality of thermocouple pairs. The N-type semiconductor portion 454 of each thermocouple pair is connected to the P-type semiconductor portion 455 of the next thermocouple pair to form a continuous electrical connection.

[0260] In some embodiments, the top ends of the N-type semiconductor portion 454 and the P-type semiconductor portion 455 in the same thermocouple pair are co-located on a pad on the lower surface of the second substrate 452. The bottom ends of the P-type semiconductor portion 455 in each thermocouple pair and the N-type semiconductor portion 454 in the next thermocouple pair are co-located on a pad on the surface of the first substrate 451, and the thermocouple pairs are connected in series by alternating connections.

[0261] In some embodiments, when the current source is a forward current source, current is transmitted in one direction, being output from the first electrode portion 4561, passing through the alternatingly arranged N-type semiconductor portions 454 and P-type semiconductor portions 455, and finally flowing into the second electrode portion 4562. When the current source is a reverse current source, current is transmitted in the opposite direction.

[0262] Figure 13A A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 1 .like Figure 13AAs shown, in some embodiments, when the current source electrically connected to the first electrode portion 4561 and the second electrode portion 4562 is a forward current source, the current flows out from the first electrode portion 4561, passes through the alternatingly arranged N-type semiconductor portions 454 and P-type semiconductor portions 455, and directly enters the second electrode portion 4562.

[0263] In some embodiments, when the electrically connected current source is a positive current source, the second substrate 452 can be controlled to be a cold end and the first substrate 451 can be controlled to be a hot end, thereby cooling the laser chip on the surface of the third substrate 453a to a target temperature range. When the electrically connected current source is a negative current source, the second substrate 452 can be controlled to be a hot end and the third substrate 453a can be controlled to be a cold end.

[0264] In some embodiments, the actual temperature of the second substrate 452, and thus the temperature of the laser chip on the surface of the third substrate 453a, can be monitored based on the change in resistance of the second thermal sensor 458. By comparing the actual temperature of the second substrate 452 with the target temperature, the MCU controls the driver chip electrically connected to the temperature control device 450 to output a corresponding current.

[0265] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0266] In some embodiments, the main carriers in the N-type semiconductor portion 454 are electrons, and the movement direction of the electrons in the N-type semiconductor portion 454 is opposite to the current transmission direction in the N-type semiconductor portion 454. When the current source is a forward current source, the electrons in the N-type semiconductor portion 454 move downward from the second substrate 452 to the first substrate 451.

[0267] In some embodiments, the main carriers in the P-type semiconductor portion 455 are holes, and the direction of hole movement in the P-type semiconductor portion 455 is the same as the direction of current transmission in the P-type semiconductor portion 455. When the current source is a forward current source, the holes in the P-type semiconductor portion 455 also move downward from the second substrate 452 to the first substrate 451.

[0268] In some embodiments, when the current source is a forward current source, both electrons and holes move downward from the second substrate 452 to the first substrate 451. The movement of carriers carries energy, and the energy is transferred from the second substrate 452 to the first substrate 451. The second substrate 452 forms a cold end to cool, and the first substrate 451 forms a hot end to heat.

[0269] Figure 13B A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 2 .like Figure 13B As shown, in some embodiments, when the current source electrically connected to the first electrode portion 4561 and the second electrode portion 4562 is a negative current source, the current flows out from the second electrode portion 4562, passes through the alternatingly arranged N-type semiconductor portions 454 and P-type semiconductor portions 455, and directly enters the first electrode portion 4561.

[0270] In some embodiments, when the electrically connected current source is a negative current source, the second substrate 453 can be controlled as the hot end and the first substrate 451 as the cold end, thereby heating the laser chip on the surface of the third substrate 453a to a target temperature range. To increase the temperature of the laser chip, a negative current source can be supplied to the first electrode portion 4561 and the second electrode portion 4562. The degree of temperature increase can be achieved by varying the current magnitude.

[0271] In some embodiments, when the electrically connected current source is a negative current source, the current output by the second electrode portion 4562 flows upward into the P-type semiconductor portion 455 electrically connected thereto, and then flows downward into the N-type semiconductor portion 454 electrically connected to the N-type semiconductor portion 454, and so on.

[0272] In some embodiments, the main carriers in the N-type semiconductor portion 454 are electrons, and the movement direction of the electrons in the N-type semiconductor portion 454 is opposite to the current transmission direction in the N-type semiconductor portion 454. When the current source is a negative current source, the electrons in the N-type semiconductor portion 454 move upward from the first substrate 451 to the second substrate 452.

[0273] In some embodiments, the main carriers in the P-type semiconductor portion 455 are holes, and the direction of hole movement in the P-type semiconductor portion 455 is the same as the direction of current transmission in the P-type semiconductor portion 455. When the current source is a negative current source, the holes in the P-type semiconductor portion 455 also move upward from the first substrate 451 to the second substrate 452.

[0274] In some embodiments, when the current source is a negative current source, both electrons and holes move upward from the first substrate 451 to the second substrate 452. The movement of carriers carries energy, and the energy is transferred from the first substrate 451 to the second substrate 452. The second substrate 452 forms a hot end to generate heat, and the first substrate 451 forms a cold end to generate cooling.

[0275] Figure 14 The cross-sectional structure of a temperature control device provided according to some embodiments of the present disclosure is Figure 3 .like Figure 14As shown, in some embodiments, a laser chip is disposed on the surface of a third substrate 453a. Taking four-way light emission as an example, the laser chip array 440 includes a first laser chip 441, a second laser chip 442, a third laser chip 443, and a fourth laser chip 444. The first laser chip 441, the second laser chip 442, the third laser chip 443, and the fourth laser chip 444 are each located on the surface of a separate third substrate 453a. In this case, the temperature of each third substrate 453a can be controlled to independently cool or heat the laser chips on its surface.

[0276] In some embodiments, the temperature of the laser chips on the surface of the third substrate 453a can be adjusted to within a target temperature range by adjusting the temperature of the second substrate 452. Furthermore, by independently controlling each third substrate 453a, the temperature of the laser chips on its surface can be independently tuned to achieve the target temperature of the corresponding laser chip.

[0277] In some embodiments, a plurality of alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 are provided between the first substrate 451 and the second substrate 452. Current shuttles up and down between the plurality of alternating N-type semiconductor portions 454 and P-type semiconductor portions 455. The movement of carriers realizes energy transfer between the first substrate 451 and the second substrate 452, thereby controlling the cooling or heating of the second substrate 452.

[0278] In some embodiments, a plurality of alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 are provided between the second substrate 452 and the third substrate 453a. Current shuttles up and down between the plurality of alternating N-type semiconductor portions 454 and P-type semiconductor portions 455. The movement of carriers can realize energy transfer between the second substrate 452 and the third substrate 453a, thereby controlling the cooling or heating of the third substrate 453a.

[0279] Figure 15 Decomposition of a temperature control device according to some embodiments of the present disclosure Figure 2 , Figure 16 Decomposition of a temperature control device according to some embodiments of the present disclosure Figure 3 , Figure 17 Schematic diagram of current transmission between a second substrate and a third substrate according to some embodiments of the present disclosure. Figure 15-17 As shown, in some embodiments, a plurality of alternating N-type semiconductor portions 454 and P-type semiconductor portions 455 are disposed between the second substrate 452 and the third substrate 453 a .

[0280] In some embodiments, the first laser chip 441 is located on one surface of the third substrate 453 a , and the second laser chip 442 is located on the other surface of the third substrate 453 a .

[0281] In some embodiments, a third circuit array 452b and a fourth circuit array 452c are formed on the upper surface of the second substrate 452. N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged on the surface of the third circuit array 452b, with a third substrate 453a positioned above these N-type semiconductor portions 454 and P-type semiconductor portions 455. N-type semiconductor portions 454 and P-type semiconductor portions 455 are also alternately arranged on the surface of the fourth circuit array 452c, with another third substrate 453a positioned above these N-type semiconductor portions 454 and P-type semiconductor portions 455.

[0282] For example, the structures of the third circuit array 452 b and the fourth circuit array 452 c , which are independent of each other, may be the same or different.

[0283] In some embodiments, N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged between the third circuit array 452b and a third substrate 453a. N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged between the fourth circuit array 452c and another third substrate 453a.

[0284] In some embodiments, a fifth circuit array 453c is formed on the lower surface of a third substrate 453a, and the fifth circuit array 453c is electrically connected to the third circuit array 452b, so that the third substrate 453a is located above the N-type semiconductor portion 454 and the P-type semiconductor portion 455 carried on the surface of the third circuit array 452b.

[0285] In some embodiments, a sixth circuit array 453d is formed on the lower surface of another third substrate 453a, and the sixth circuit array 453d is electrically connected to the fourth circuit array 452c, so that the third substrate 453 is located above the N-type semiconductor portion 454 and the P-type semiconductor portion 455 carried on the surface of the fourth circuit array 452c.

[0286] In some embodiments, N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged between the third circuit array 452b and the fifth circuit array 453c. The third circuit array 452b and the fifth circuit array 453c are electrically connected to achieve electrical connection between the second substrate 452 and a third substrate 453a.

[0287] In some embodiments, N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged between the fourth circuit array 452c and the sixth circuit array 453d. The fourth circuit array 452c and the sixth circuit array 453d are electrically connected to achieve electrical connection between the second substrate 452 and another third substrate 453a.

[0288] In some embodiments, to illustrate the electrical connection between the third electrode portion 4571, each thermocouple pair, and the fourth electrode portion 4572, the third circuit array 452b illustratively includes a ninth pad portion 4525, a tenth pad portion 4526, and an eleventh pad portion 4527. Multiple pad portions are provided between the tenth pad portion 4526 and the eleventh pad portion 4527.

[0289] In some embodiments, in order to illustrate the electrical connection method between the third electrode portion 4571, each thermocouple pair, and the fourth third electrode portion 4572, illustratively, a fifth circuit array 453c is formed on the lower surface of a third substrate 453a, and the fifth circuit array 453c includes a twelfth pad portion 4531c, a thirteenth pad portion 4532c, a fourteenth pad portion 4533c, and a fifteenth pad portion 4534c.

[0290] In some embodiments, in order to illustrate the electrical connection method between the third electrode portion 4571, each thermocouple pair, and the fourth electrode portion 4572, illustratively, an N-type semiconductor portion 454d, an N-type semiconductor portion 454e, a P-type semiconductor portion 455c, and a P-type semiconductor portion 455d are provided between the third substrate 453a and the second substrate 452.

[0291] In some embodiments, the third electrode portion 4571 is electrically connected to the N-type semiconductor portion 454d, and the fourth electrode portion 4572 is electrically connected to the P-type semiconductor portion 455d. For example, the bottom surface of the third electrode portion 4571 is connected to the N-type semiconductor portion 454d, and the bottom surface of the fourth electrode portion 4572 is connected to the P-type semiconductor portion 455d. The N-type semiconductor portion 454d is electrically connected to the twelfth pad portion 4531c on the lower surface of the third substrate 453a, and the P-type semiconductor portion 455d is electrically connected to the fifteenth pad portion 4534c on the lower surface of the third substrate 453a.

[0292] In some embodiments, the N-type semiconductor portion 454d is electrically connected to the P-type semiconductor portion 455c to form a thermocouple pair, and the P-type semiconductor portion 455c is electrically connected to the N-type semiconductor portion of the next thermocouple pair.

[0293] In some embodiments, the bottom ends of the N-type semiconductor portion 454 and the P-type semiconductor portion 455 in the same thermocouple pair are co-located on a pad on the upper surface of the second substrate 452. The bottom ends of the P-type semiconductor portion 455 in each thermocouple pair and the N-type semiconductor portion 454 in the next thermocouple pair are co-located on a pad on the lower surface of the third substrate 453a, and the thermocouple pairs are connected in series by alternating connections.

[0294] In some embodiments, the N-type semiconductor portion 454d and the P-type semiconductor portion 455c are co-located on the surface of the ninth pad portion 4525 on the upper surface of the second substrate 452. The P-type semiconductor portion 455c and the N-type semiconductor portion 454e are co-located on the thirteenth pad portion 4532c on the lower surface of the third substrate 453a. The N-type semiconductor portion 454e and the P-type semiconductor portion of the thermocouple pair in which it is located are co-located on the tenth pad portion 4526 on the upper surface of the second substrate 452. This alternating connection realizes the series connection of each thermocouple pair.

[0295] like Figure 17 As shown, when the current source is a forward current source, current is transmitted in one direction, output from the third electrode portion 4571, and passes through the alternatingly arranged N-type semiconductor portions 454 and P-type semiconductor portions 455 until it flows into the fourth electrode portion 4572. When the current source is a reverse current source, current is transmitted in the opposite direction.

[0296] Figure 18A A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 3 .like Figure 18A As shown, in some embodiments, when the current source electrically connected to the third electrode portion 4571 and the fourth electrode portion 4572 is a forward current source, the current flows out from the third electrode portion 4571, passes through the alternatingly arranged N-type semiconductor portions 454 and P-type semiconductor portions 455, and directly enters the fourth electrode portion 4572.

[0297] In some embodiments, when the electrically connected current source is a positive current source, the second substrate 452 can be controlled to be a cold end and the third substrate 453a can be controlled to be a hot end, thereby tuning the temperature of the laser chip on the surface of the third substrate 453a to within a target temperature range. When the electrically connected current source is a negative current source, the second substrate 452 can be controlled to be a hot end and the third substrate 453a can be controlled to be a cold end.

[0298] In some embodiments, the actual temperature of the third substrate 453a can be monitored based on the change in the resistance of the third thermistor 4535. By comparing the actual temperature of the third substrate 453a with the target temperature, the MCU controls the driver chip electrically connected to the temperature control device 450 to control the driver chip to output a current of corresponding size.

[0299] In some embodiments, when the electrically connected current source is a forward current source, the current output by the third electrode portion 4571 flows downward into the N-type semiconductor portion 454d electrically connected thereto, and then flows upward into the P-type semiconductor portion 455c electrically connected to the N-type semiconductor portion 454d, and so on alternately.

[0300] In some embodiments, the main carriers in the N-type semiconductor portion 454 are electrons, and the movement direction of the electrons in the N-type semiconductor portion 454 is opposite to the current transmission direction in the N-type semiconductor portion 454. When the current source is a forward current source, the electrons in the N-type semiconductor portion 454 move upward from the second substrate 452 to the third substrate 453a.

[0301] In some embodiments, the main carriers in the P-type semiconductor portion 455 are holes, and the direction of hole movement in the P-type semiconductor portion 455 is the same as the direction of current transmission in the P-type semiconductor portion 455. When the current source is a forward current source, the holes in the P-type semiconductor portion 455 also move upward from the second substrate 452 to the third substrate 453a.

[0302] In some embodiments, when the current source is a forward current source, both electrons and holes move upward from the second substrate 452 to the third substrate 453a. The movement of carriers carries energy, and the energy moves upward from the second substrate 452 to the third substrate 453a. The second substrate 452 forms a cold end to cool, and the third substrate 453a forms a hot end to heat.

[0303] Figure 18B A schematic diagram of a temperature control principle of a temperature control device according to some embodiments of the present disclosure Figure 4 .like Figure 18B As shown, in some embodiments, when the current source electrically connected to the third electrode portion 4571 and the fourth electrode portion 4572 is a negative current source, the current flows out from the fourth electrode portion 4572, passes through the alternatingly arranged N-type semiconductor portions 454 and P-type semiconductor portions 455, and directly enters the third electrode portion 4571.

[0304] In some embodiments, when the electrically connected current source is a negative current source, the second substrate 453 can be controlled as a hot end and the third substrate 451 can be controlled as a cold end, thereby cooling the laser chip on the surface of the third substrate 453a to within a target temperature range.

[0305] In some embodiments, when the electrically connected current source is a negative current source, the current output by the fourth electrode portion 4572 flows downward into the P-type semiconductor portion 455 electrically connected thereto, and then flows upward into the N-type semiconductor portion 454 electrically connected to the P-type semiconductor portion 455, and so on.

[0306] In some embodiments, the main carriers in the N-type semiconductor portion 454 are electrons, and the movement direction of the electrons in the N-type semiconductor portion 454 is opposite to the current transmission direction in the N-type semiconductor portion 454. When the current source is a negative current source, the electrons in the N-type semiconductor portion 454 move downward from the third substrate 453a to the second substrate 452.

[0307] In some embodiments, the main carriers in the P-type semiconductor portion 455 are holes, and the direction of hole movement in the P-type semiconductor portion 455 is the same as the direction of current transmission in the P-type semiconductor portion 455. When the current source is a negative current source, the holes in the P-type semiconductor portion 455 also move downward from the third substrate 453a to the second substrate 452.

[0308] In some embodiments, when the current source is a negative current source, both electrons and holes move downward from the third substrate 453a to the second substrate 452. The movement of carriers carries energy, and the energy is transferred from the third substrate 453a to the second substrate 452. The second substrate 452 forms a hot end to generate heat, and the third substrate 453a forms a cold end to generate cooling.

[0309] Figure 19 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 1 , Figure 20 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 2 .like Figure 19-20 As shown, in some embodiments, to meet greater wiring requirements, the end of the electrical connector 430 located inside the tube shell 410 includes a first pad surface 431 and a second pad surface 432 to provide more pad portions. The first pad surface 431 and the second pad surface 432 can be arranged in a stepped manner.

[0310] In some embodiments, the first pad surface 431 is used for electrical connection of high-frequency signals, and the second pad surface 432 is used for electrical connection of low-frequency signals.

[0311] In some embodiments, the positive electrode of the second thermal-sensitive portion 458 is electrically connected to the second pad surface 432 , and the negative electrode is electrically connected to the first pad surface 431 to achieve grounding.

[0312] In some embodiments, a first electrical connection portion 4531 and a second electrical connection portion 4532 are formed on the surface of the third substrate 453a. The first electrical connection portion 4531 provides a signal connection to the first laser chip 441, and the second electrical connection portion 4532 provides a ground connection to the first laser chip 441. For example, the first electrical connection portion 4531 and the second electrical connection portion 4532 are each electrically connected to the first pad surface 431.

[0313] In some embodiments, a third electrical connection portion 4533 and a fourth electrical connection portion 4534 are formed on a surface of the third substrate 453a. The third electrical connection portion 4533 is used for wire bonding connection between the third electrode portion 4571 and the electrical connector 430, and the fourth electrical connection portion 4534 is used for wire bonding connection between the fourth electrode portion 4572 and the electrical connector 430. Exemplarily, the third electrical connection portion 4533 is electrically connected to the first pad surface 431 or the second pad surface 432, and the fourth electrical connection portion 4534 is electrically connected to the second pad surface 432 or the first pad surface 431.

[0314] In some embodiments, a fifth electrical connection portion 4536 and a sixth electrical connection portion 4537 are formed on the surface of the third substrate 453a. The fifth electrical connection portion 4536 is used to electrically connect the positive electrode of the third thermal sensing portion 4535 to the electrical connector 430, and the sixth electrical connection portion 4537 is used to electrically connect the negative electrode of the third thermal sensing portion 4535 to the electrical connector 430. For example, the fifth electrical connection portion 4536 can be electrically connected to the second pad surface 432, and the sixth electrical connection portion 4537 can be electrically connected to the pad portion of the first pad surface 431 to which the second electrical connection portion 4532 is electrically connected.

[0315] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 may be electrically connected to the second pad surface 432 , respectively.

[0316] Figure 21 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 3 ; Figure 22 Schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure Figure 4 .like Figure 21 and Figure 22 As shown, in some embodiments, the surface of the third substrate 453 b carries a first laser chip 441 and a second laser chip 442 .

[0317] In some embodiments, a first temperature-controlling portion 4531b, a second temperature-controlling portion 4532b, and a first thermally sensitive portion 4533b are formed on the surface of the third substrate 453b. The first temperature-controlling portion 4531b is located on one side of the first laser chip 441 to control the temperature of the first laser chip 441. The second temperature-controlling portion 4532b is located on one side of the second laser chip 442 to control the temperature of the second laser chip 442.

[0318] In some embodiments, when temperature tuning the first laser chip 441, the current flow direction of the N-type semiconductor portion and the P-type semiconductor portion between the first substrate 451 and the second substrate 452 is controlled to control the heating or cooling of the second substrate 452, thereby tuning the temperature of the first laser chip 441 to a target temperature range. The current flow direction of the N-type semiconductor portion and the P-type semiconductor portion between the second substrate 452 and the third substrate where the first laser chip 441 is located is then controlled to control the heating or cooling of the third substrate, thereby further heating or cooling the first laser chip 441. The first laser chip 441 is independently temperature-tuned by controlling the first temperature control unit 4531b, thereby ensuring the wavelength accuracy of the first laser chip 441. By placing the first laser chip 441 and the second laser chip 442 together on a third substrate 453b, and providing a first temperature control unit 4531b on one side of the first laser chip 441 and a second temperature control unit 4532b on the other side of the second laser chip 442, the first laser chip 441 and the second laser chip 442 can be independently temperature-tuned simultaneously, while meeting the wavelength accuracy requirements of the first laser chip 441 and the second laser chip 442. By placing the first laser chip 441 and the second laser chip 442 together on a third substrate 453b, the number of third substrates 453b can be reduced.

[0319] In some embodiments, a second thermally sensitive portion 458 is disposed on the surface of the third substrate 453 b . The positive electrode of the second thermally sensitive portion 458 is electrically connected to the second pad surface 432 , and the negative electrode is electrically connected to the first pad surface 431 .

[0320] In some embodiments, the positive poles of the first temperature control part 4531b, the second temperature control part 4532b, and the first thermosensitive part 4533b are electrically connected to the second solder pad surface 432, and the negative poles of the first temperature control part 4531b, the second temperature control part 4532b, and the first thermosensitive part 4533b are electrically connected to the first solder pad surface 431.

[0321] In some embodiments, the anode and cathode of the first laser chip 441 are both electrically connected to the first pad surface 431 , and the anode and cathode of the second laser chip 442 are both electrically connected to the first pad surface 431 .

[0322] Figure 23 FIG1 is a cross-sectional structural diagram of another light emitting component provided according to some embodiments of the present disclosure. Figure 24 FIG1 is a partial structural diagram of another light emitting component provided according to some embodiments of the present disclosure. Figure 23 and Figure 24As shown, in some embodiments, an electrical connector 430 is provided at the end of the tube housing 410. To meet wire bonding requirements, the end of the electrical connector 430 located inside the tube housing 410 includes a first pad surface 431 and a second pad surface 432 to provide more pad areas. Exemplarily, the first pad surface 431 is lower than the second pad surface 432.

[0323] In some embodiments, the light emitting component 400 may include a TEC 470 . The TEC 470 is located inside the housing 410 . The TEC 470 is located on one side of the electrical connector 430 .

[0324] In some embodiments, the light emitting component 400 may include a substrate 480. The substrate 480 is located on the surface of the TEC 470. A circuit pattern is formed on the surface of the substrate 480.

[0325] In some embodiments, substrate 480 is used to support laser chips. The surface of substrate 480 can support at least one laser chip. For example, a laser chip array 440 supporting a single laser chip on the surface of substrate 480 supports four-way emission. For example, laser chip array 440 includes a first laser chip 441, a second laser chip 442, a third laser chip 443, and a fourth laser chip 444. The first laser chip 441, the second laser chip 442, the third laser chip 443, and the fourth laser chip 444 are respectively disposed on corresponding surfaces of substrate 480.

[0326] In some embodiments, a heating monitoring unit 481 is formed on the surface of the substrate 480. For example, the heating monitoring unit 481 can heat or cool the corresponding laser chip disposed on the surface of the substrate 480 and monitor the real-time temperature of the laser chip disposed on the surface of the substrate 480.

[0327] In some embodiments, the heating monitoring portion 481 may be a heating wire that is sensitive to temperature. For example, the heating monitoring portion 481 is a Pt heating wire.

[0328] In some embodiments, a thermal sensing portion 473 may be provided on the surface of the TEC 470 to monitor the surface temperature of the TEC 470. In some embodiments, the thermal sensing portion 473 has a positive electrode electrically connected to the second pad surface 432 and a negative electrode electrically connected to the first pad surface 431.

[0329] In some embodiments, circuit patterns are formed on the surface of substrate 480 for electrical connection of the laser chip and its heating monitoring unit 481. For example, the laser chip and heating monitoring unit 481 provided on the surface of substrate 480 are electrically connected to the first pad surface 431.

[0330] In some embodiments, a first electrode column 471 and a second electrode column 472 are disposed on the surface of the TEC 470. The first electrode column 471 and the second electrode column 472 can be electrically connected to the second pad surface 432.

[0331] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An optical module, characterized in that: include: circuit boards; A light emitting component, electrically connected to the circuit board, comprising: The tube shell has an opening formed at an end thereof, wherein an electrical connector is embedded in the opening, and the electrical connector includes a first solder pad surface and a second solder pad surface; First laser chip; a second laser chip; The temperature regulating device is located in the tube shell and includes: a first substrate; a second substrate, located above the first substrate; at least two third substrates, the third substrates being located above the second substrate, wherein a seventh circuit array is formed on the upper surface of one of the third substrates to carry the first laser chip; an eighth circuit array is formed on the upper surface of the other third substrate to carry the second laser chip; a third electrode portion and a fourth electrode portion are embedded in the third substrates respectively; the seventh circuit array includes a first electrical connection portion and a second electrical connection portion, one end of the first electrical connection portion is electrically connected to the positive electrode of the first laser chip, and the other end is electrically connected to the first pad surface; one end of the second electrical connection portion is electrically connected to the negative electrode of the first laser chip, and the other end is electrically connected to the first pad surface; the seventh circuit array includes a third electrical connection portion and a fourth electrical connection portion, one end of the third electrical connection portion is electrically connected to the third electrode portion, and the other end is electrically connected to the second pad surface, and one end of the fourth electrical connection portion is electrically connected to the fourth electrode portion, and the other end is electrically connected to the second pad surface.

2. The optical module according to claim 1, wherein A third heat-sensitive portion is formed on the surface of the third substrate carrying the first laser chip, and the third heat-sensitive portion is located on one side of the first laser chip; The seventh circuit array includes a fifth electrical connection portion and a sixth electrical connection portion; One end of the fifth electrical connection portion is electrically connected to the third thermal sensitive portion, and the other end is electrically connected to the electrical connector; one end of the sixth electrical connection portion is electrically connected to the third thermal sensitive portion, and the other end is electrically connected to the electrical connector.

3. The optical module according to claim 1, wherein: A first electrode portion and a second electrode portion are provided on the surface of the first substrate, and a first circuit array is formed on the upper surface of the first substrate; A second circuit array is formed on the lower surface of the second substrate, and a third circuit array and a fourth circuit array are formed on the upper surface, which are independent of each other; wherein the second circuit array is electrically connected to the first circuit array to achieve electrical connection between the second substrate and the first substrate; the surface of the third circuit array carries N-type semiconductor portions and P-type semiconductor portions arranged alternately; and the surface of the fourth circuit array carries N-type semiconductor portions and P-type semiconductor portions arranged alternately. A fifth circuit array is formed on the lower surface of one of the third substrates, and the fifth circuit array is electrically connected to the third circuit array, so that the third substrate is located above the N-type semiconductor portion and the P-type semiconductor portion carried on the surface of the third circuit array; a sixth circuit array is formed on the lower surface of the other third substrate, and the sixth circuit array is electrically connected to the fourth circuit array, so that the third substrate is located above the N-type semiconductor portion and the P-type semiconductor portion carried on the surface of the fourth circuit array.

4. The optical module according to claim 1, wherein: The third electrode portion penetrates the third substrate and is connected to one of the N-type semiconductor portions; The fourth electrode portion penetrates the third substrate and is electrically connected to one of the P-type semiconductor portions; The fourth electrode portion is electrically connected to the third electrode portion through an N-type semiconductor portion and a P-type semiconductor portion distributed between the third substrate and the second substrate.

5. The optical module according to claim 1, wherein: N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the first substrate and the second substrate; N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the second substrate and one of the third substrates; The number of N-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of N-type semiconductor portions distributed between the second substrate and one of the third substrates; The number of the P-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of the P-type semiconductor portions distributed between the second substrate and one of the third substrates.

6. An optical module, characterized in that: include: circuit boards; A light emitting component, electrically connected to the circuit board, comprising: The tube shell has an opening formed at an end thereof, and an electrical connector is embedded in the opening; First laser chip; a second laser chip; The temperature regulating device is located in the tube shell and includes: a first substrate; a second substrate, located above the first substrate; A third substrate is located above the second substrate; a third electrode portion and a fourth electrode portion are passed through the surface of the third substrate; an eleventh circuit array is formed on the surface of the third substrate to carry the first laser chip and the second laser chip; the eleventh circuit array includes a first temperature control portion and a second temperature control portion, the first temperature control portion and the second temperature control portion are electrically connected to the electrical connector respectively, the first temperature control portion is located on one side of the first laser chip, and the second temperature control portion is located on one side of the second laser chip; the eleventh circuit array includes a chip positive electrode pad portion and a chip negative electrode pad portion, the chip positive electrode pad portion and the chip negative electrode pad portion are electrically connected to the electrical connector respectively; the eleventh circuit array includes a first via pad portion and a second via pad portion, one end of the first via pad portion is electrically connected to the third electrode portion, and the other end is electrically connected to the electrical connector, one end of the second via pad portion is electrically connected to the fourth electrode portion, and the other end is electrically connected to the electrical connector.

7. The optical module according to claim 6, wherein: A first heat-sensitive portion is formed between the first laser chip and the second temperature control portion; Two pads are formed at both ends of the first thermosensitive portion, and the two pads are electrically connected to the electrical connectors.

8. The optical module according to claim 6, wherein: A first electrode portion and a second electrode portion are provided on the surface of the first substrate, and a first circuit array is formed on the upper surface of the first substrate; A second circuit array is formed on the lower surface of the second substrate, and a ninth circuit array is formed on the upper surface; wherein the second circuit array is electrically connected to the first circuit array, and the ninth circuit array carries alternating N-type semiconductor portions and P-type semiconductor portions on its surface; A tenth circuit array is formed on the lower surface of the third substrate. The tenth circuit array is electrically connected to the ninth circuit array so that the third substrate is disposed above the N-type semiconductor portion and the P-type semiconductor portion carried on the surface of the ninth circuit array.

9. The optical module according to claim 6, wherein: The third electrode portion penetrates the third substrate and is connected to one of the N-type semiconductor portions; The fourth electrode portion passes through the third substrate and is electrically connected to one of the P-type semiconductor portions; the fourth electrode portion is electrically connected to the third electrode portion through the N-type semiconductor portion and the P-type semiconductor portion distributed between the third substrate and the second substrate.

10. The optical module according to claim 6, wherein: N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the first substrate and the second substrate; N-type semiconductor portions and P-type semiconductor portions are alternately distributed between the second substrate and one of the third substrates; The number of N-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of N-type semiconductor portions distributed between the second substrate and the third substrate; The number of the P-type semiconductor portions distributed between the first substrate and the second substrate is greater than the number of the P-type semiconductor portions distributed between the second substrate and the third substrate.

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