RGMII interface and MII interface direct connection structure

Abstract

The utility model discloses a direct connection structure of an RGMII interface and an MII interface. The direct connection structure is specifically characterized in that a data pin, an enabling pin and a clock pin of the RGMII interface are directly connected with a data pin, an enabling pin and a clock pin of the MII interface respectively; an external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, and the external clock generating circuit outputs clock signals conforming to matched time sequences for the RGMII interface and the MII interface. According to the utility model, under the condition that the RGMII interface is directly connected with the MII interface, the external clock generation circuit can be adopted to output clock signals conforming to matched time sequences for the RGMII interface and the MII interface, so that data communication can be realized by directly connecting the RGMII interface and the MII interface, and compared with the prior art, PHY (Physical Layer) intermediate lines are reduced, the cost is saved, and electromagnetic interference is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of Ethernet communication, in particular to a direct connection structure of an RGMII interface and an MII interface. Background Art

[0002] Currently, many circuit boards are equipped with both a CPU and a single-chip microcomputer. The CPU's network interface is usually an RGMII interface (Gigabit network interface) and cannot be reused as an MII interface, while the network interface of most single-chip microcomputers is an MII interface (100M network interface). Since the network interfaces of the two are different in terms of transmission rate, clock signal reception and transmission timing, direct connection cannot achieve communication. Therefore, if Figure 1 As shown, the industry typically sets up a PHY (Physical Layer) on both the CPU side and the MCU side, and connects through the PHY. The process of sending data from the CPU to the MCU is as follows: the CPU transmits data to the first PHY via the RGMII interface. The first PHY converts the data from a digital signal to an analog signal and transmits it to the second PHY on the MCU side. The second PHY on the MCU side converts the analog signal from the RGMII interface to a digital signal recognizable by the MII interface and transmits it to the MII interface of the MCU. The process of sending data from the MCU to the CPU is as follows: the MCU transmits data to the second PHY via the MII interface. The second PHY converts the data from a digital signal to an analog signal and transmits it to the first PHY on the CPU side. The first PHY on the CPU side converts the analog signal from the MII interface to a digital signal recognizable by the RGMII interface and transmits it to the RGMII interface of the CPU. This connection method requires the installation of two additional PHYs, which incurs a certain cost. In addition, due to the addition of the PHY intermediate line, electromagnetic interference exists. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to realize data communication between the RGMII interface and the MII interface without adding a PHY intermediate line.

[0004] In order to solve the above technical problems, the utility model provides a direct connection structure between the RGMII interface and the MII interface, as follows: the data pin, enable pin, and clock pin of the RGMII interface are directly connected to the data pin, enable pin, and clock pin of the MII interface respectively; an external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, and the external clock generating circuit outputs a clock signal that conforms to the matching timing for the RGMII interface and the MII interface.

[0005] Furthermore, the connection of each of the data pin, the enable pin, and the clock pin is specifically that the sending pin of the RGMII interface is connected to the receiving pin of the MII interface, and the receiving pin of the RGMII interface is connected to the sending pin of the MII interface.

[0006] Furthermore, the external clock generating circuit is specifically connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface. The external clock generating circuit outputs a clock signal that conforms to the matched timing to the clock receiving pin of the RGMII interface, and outputs a clock signal that conforms to the matched timing to the clock sending pin of the MII interface.

[0007] Furthermore, the carrier monitoring pin, the collision monitoring pin, the data error signal sending pin and the data error receiving pin of the MII interface that are not connected to the RGMII interface are all connected to the signal ground.

[0008] Regardless of whether it is an RGMII interface or an MII interface, data can be correctly sent and received as long as the clock signal at the receiving end of the interface can meet the timing specified in the IEEE802.3 standard. The industry uses PHY to make the clock signals at the receiving ends of the RGMII interface and the MII interface meet the specified timing, thereby realizing data communication between the two. The reason why the RGMII interface and the MII interface cannot communicate data directly is that the timing of their clock signals is inconsistent, resulting in the inability of the two to directly receive a clock signal that meets the matched timing from each other. The present utility model takes into account that when the RGMII interface and the MII interface are directly connected, an external clock generating circuit can be used to output a clock signal that meets the matched timing for the RGMII interface and the MII interface. In this way, data communication can be realized by directly connecting the two. Compared with the existing technology, the PHY intermediate line is reduced, cost is saved, and electromagnetic interference is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a network connection structure diagram of the MAC unit of the CPU and the MAC unit of the single-chip microcomputer in the prior art.

[0010] Figure 2 This is a direct connection structure diagram of the MAC unit of the CPU and the MAC unit of the single-chip microcomputer of the utility model.

[0011] Figure 3 This is a pin connection diagram for directly connecting the MAC unit of the CPU and the MAC unit of the single-chip microcomputer of the utility model. DETAILED DESCRIPTION

[0012] The present invention is further described in detail below in conjunction with specific embodiments.

[0013] The direct connection structure between the RGMII interface and the MII interface in this embodiment is as follows Figure 2 As shown, the RGMII interface is directly connected to the MII interface, and then an external clock generation circuit is connected between the RGMII interface and the MII interface. The specific connection method is detailed below.

[0014] like Figure 3 As shown, the technicians connected the data sending pin of the RGMII interface directly to the data receiving pin of the MII interface, connected the data receiving pin of the RGMII interface directly to the data sending pin of the MII interface, connected the receive data valid pin (enable receive pin) of the RGMII interface directly to the enable send pin of the MII interface, connected the enable send pin of the RGMII interface directly to the receive data valid pin (enable receive pin) of the MII interface, and connected the clock sending pin of the RGMII interface directly to the clock receiving pin of the MII interface. The clock sending pin of the RGMII interface can send a clock signal, while the clock receiving pin of the MII interface needs to be connected to the clock signal from the outside. Therefore, the clock sending pin of the RGMII interface can directly send a clock signal that meets the timing matched by the clock receiving pin of the MII interface to the clock receiving pin of the MII interface. The clock receiving pin of the RGMII interface needs to receive a clock signal from the outside, and the clock sending pin of the MII interface also needs to receive a clock signal from the outside. Therefore, in this embodiment, the above-mentioned external clock generating circuit is connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface (this embodiment uses a 25MHz active crystal oscillator as the external clock generating circuit), that is, the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface are connected through the above-mentioned external clock generating circuit. In this way, the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface both receive clock signals from the external clock generating circuit. On the one hand, the external clock generating circuit outputs a clock signal that matches the timing matched by the clock receiving pin of the RGMII interface, and on the other hand, it outputs a clock signal that matches the timing matched by the clock sending pin of the MII interface. The clock signal of the timing matched by the clock receiving pin of the RGMII interface and the clock signals of the timing matched by the clock receiving pin and the clock sending pin of the MII interface refer to the clock signals of the timing specified in the IEEE 802.3 standard. The other pins of the MII interface that are not connected to the RGMII interface are connected to the power supply. Specifically, the CRS pin (carrier detection pin), COL pin (collision detection pin), TXER pin (data error signal sending pin) and RXER pin (data error receiving pin) of the MII interface are all connected to the signal ground.

[0015] After the technicians have connected the RGMII interface and the MII interface according to the above process, they also need to configure the RGMII interface and the MII interface to forced mode, which includes the following configuration operations: (1) the default built-in PHY driver initialization of this interface is completed; (2) the auto-negotiation function is turned off and the transmission rate is set to 100MBits / s; (3) the full-duplex mode is set. After the configuration is completed, the RGMII interface and the MII interface can directly communicate data. Compared with the existing technology, the PHY intermediate line is reduced, which saves costs and reduces electromagnetic interference.

[0016] The above is only an embodiment of the present invention and does not limit the scope of patent protection. Those skilled in the art can make non-substantial changes or substitutions based on the present invention and still fall within the scope of patent protection.

Claims

1. The RGMII interface is directly connected to the MII interface, which is characterized by: The data pin, enable pin and clock pin of the RGMII interface are directly connected to the data pin, enable pin and clock pin of the MII interface respectively; an external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, and the external clock generating circuit outputs a clock signal that meets the matching timing for the RGMII interface and the MII interface.

2. The RGMII interface and MII interface direct connection structure according to claim 1, wherein: Specifically, the connection of each pin among the data pin, enable pin, and clock pin is that the sending pin of the RGMII interface corresponds to the receiving pin of the MII interface, and the receiving pin of the RGMII interface corresponds to the sending pin of the MII interface.

3. The RGMII interface and MII interface direct connection structure according to claim 2, wherein the external The clock generating circuit is specifically connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface. The external clock generating circuit outputs a clock signal that conforms to the matching timing to the clock receiving pin of the RGMII interface, and outputs a clock signal that conforms to the matching timing to the clock sending pin of the MII interface.

4. The RGMII interface and MII interface direct connection structure according to claim 2, wherein: The carrier detection pin, collision detection pin, data error signal sending pin, and data error receiving pin of the MII interface that are not connected to the RGMII interface are all connected to the signal ground.

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