Divided-by-two frequency divider

Abstract

The utility model discloses a divide-by-2 frequency divider. The divide-by-2 frequency divider comprises a first trigger, a second trigger, a third trigger, a fourth trigger and an anti-phase unit, the first trigger, the second trigger, the third trigger and the fourth trigger are cascaded; the inverting unit is used for inverting a first intermediate signal output by the first trigger, a second intermediate signal output by the second trigger, a third intermediate signal output by the third trigger and a fourth intermediate signal output by the fourth trigger to generate a first result signal, a second result signal, a third result signal and a fourth result signal. According to the divide-by-2 frequency divider provided by the utility model, the first trigger, the second trigger, the third trigger and the fourth trigger are cascaded, and each trigger can support a differential mode and is driven by a differential input clock signal, so that the divide-by-2 frequency divider can output a signal with a duty ratio of 25% while realizing divide-by-2 frequency division, and a special output circuit with a duty ratio of 25% is not needed any more; and the power consumption and the chip area are reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and in particular relates to a binary frequency divider. Background Art

[0002] RF transceivers primarily use mixers for up- and down-conversion. Down-conversion mixers have inputs that include the RF port and the local oscillator (LO port), while the output is the intermediate frequency (IF port). Up-conversion mixers have the RF and IF ports interchangeable. Figure 1 This is a typical RF transceiver schematic. You can see that the local oscillator provides frequency conversion signals for the up- and down-conversion mixers.

[0003] Traditional mixers are basically implemented using Gilbert active mixers, such as Figure 2 As shown, the gate inputs of transistors M1 and M4 are differential RF signals VRF+ and VRF-. The gate inputs of transistors M2, M3, M5, and M6 are differential local oscillator signals LOp and LOn. Resistor RD is the load resistor, which is evenly distributed across the differential. The X and Y nodes are differential outputs, with the output voltage VIF.

[0004] Active mixers typically use a local oscillator signal with a 50% duty cycle to achieve mixing while providing a certain gain. However, active mixers have high noise levels and are difficult to optimize for linearity.

[0005] In 2010, the Hooman Darabi project team of Broadcom published an article proposing a receiver solution for a 25% duty cycle passive mixer: "A. Mirzaei, H. Darabi, J. Leete, and Y. Chang, Analysis and optimization of direct-conversion receivers with 25% duty-cycle current-driven passive mixer, IEEE TCAS I: Regular paper, 57, no. 9, 2353-2366, 2010." This article cleverly utilizes the characteristics of the 25% duty cycle local oscillator signal to transfer the RF current to the intermediate frequency load capacitor by turning on the four transistors of the mixer in turn, thus avoiding the overlapping current of the I and Q paths. Therefore, it has the advantages of low noise, good linearity, and low power consumption, and is also called a passive current mode mixer. Figure 3As shown, LO1, LO2, LO3, and LO4 are four-phase local oscillator signals with a 25% duty cycle and no overlap. RF is the RF input current, which is mixed to obtain i BBI and i BBQ The intermediate frequency current passes through the load 2*ZBB to obtain the intermediate frequency voltage V BBI and V BBQ .

[0006] In 2011, the project team published another paper using 25% passive mixers in transmitters: "A. Mirzaei, D. Murphy, and H. Darabi, Analysis of direct-conversion IQ transmitters with 25% duty-cycle passive mixers, IEEE TCS I: Regular papers, 58, no. 10, 2318-23321, 2011." This paper specifically analyzes the performance of a 25% duty cycle local oscillator passive mixer in a transmitter. As in the receiver, it has the advantages of low power consumption and high linearity. Figure 4 As shown in the figure, this circuit first divides the output of the voltage-controlled oscillator (VCO) by two to produce a 50% duty cycle output. Then, through logical combinations (AND gates, inverters, etc.), 25% duty cycle outputs LO1, LO2, LO3, and LO4 are generated. Typically, to minimize I / Q overlap in the transceiver, the duty cycle is slightly lower than 25%, such as 23%.

[0007] Because the VCO frequency is very high, both the divide-by-two circuit and the 25% generator circuit must operate at a high frequency (usually the highest operating frequency in a transceiver circuit). Therefore, in a CMOS integrated circuit, a large amount of current is consumed to implement this function, increasing system power consumption.

[0008] The information disclosed in this background technology section is only intended to increase the understanding of the overall background of the present invention, and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art. Utility Model Content

[0009] The purpose of the utility model is to provide a two-way frequency divider which can reduce its own power consumption.

[0010] In order to achieve the above-mentioned object, a specific embodiment of the present utility model provides a two-frequency divider, comprising: a first trigger, a second trigger, a third trigger, a fourth trigger and an inverting unit;

[0011] The input terminal of the first trigger is connected to the third output terminal of the first trigger, the input terminal of the second trigger is connected to the third output terminal of the second trigger, the input terminal of the third trigger is connected to the third output terminal of the third trigger, and the input terminal of the fourth trigger is connected to the third output terminal of the fourth trigger. The input terminal of the first trigger is used to receive an input signal, the first output terminal of the first trigger outputs a first signal and is connected to the input terminal of the second trigger, the first output terminal of the second trigger outputs a second signal and is connected to the input terminal of the third trigger, the first output terminal of the third trigger outputs a third signal and is connected to the input terminal of the fourth trigger, and the first output terminal of the fourth trigger outputs a fourth signal. The first trigger, the second trigger, the ... first trigger, the second trigger, the first trigger, the second trigger, the first trigger, the second trigger, the first trigger, the first trigger, the second trigger, the first trigger, the second trigger, the The trigger, the third trigger, and the fourth trigger are all driven by a differential input clock signal. The inverting unit is connected to the second output terminal of the first trigger, the second output terminal of the second trigger, the second output terminal of the third trigger, and the second output terminal of the fourth trigger. The inverting unit is used to invert the first intermediate signal output from the second output terminal of the first trigger, the second intermediate signal output from the second output terminal of the second trigger, the third intermediate signal output from the second output terminal of the third trigger, and the fourth intermediate signal output from the second output terminal of the fourth trigger to generate a first result signal, a second result signal, a third result signal, and a fourth result signal. The duty cycle of the first result signal, the second result signal, the third result signal, and the fourth result signal is 25%.

[0012] In one or more embodiments of the present invention, the first clock end of the first trigger is used to receive a first input clock signal, the second clock end of the first trigger is used to receive a second input clock signal, the first clock end of the second trigger is used to receive the second input clock signal, the second clock end of the second trigger is used to receive the first input clock signal, the first clock end of the third trigger is used to receive the first input clock signal, the second clock end of the third trigger is used to receive the second input clock signal, the first clock end of the fourth trigger is used to receive the second input clock signal, and the second clock end of the fourth trigger is used to receive the first input clock signal.

[0013] In one or more embodiments of the present invention, the first trigger includes a first-stage circuit, a second-stage circuit, and a third-stage circuit. The first-stage circuit generates a first signal based on the drive of a differential input clock signal and based on the input signal. The second-stage circuit is connected to the first-stage circuit to receive the first signal and generates a first intermediate signal based on the drive of the clock input signal. The third-stage circuit is connected to the input end of the second-stage circuit.

[0014] In one or more embodiments of the present invention, the first-stage circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the first end of the first transistor is connected to a power supply voltage, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is connected to the second end of the third transistor to output a first signal, the first end of the third transistor is connected to the second end of the fourth transistor, the first end of the fourth transistor is connected to a ground voltage, the control end of the second transistor and the control end of the third transistor are used to receive a differential input clock signal, and the control end of the first transistor and the control end of the fourth transistor are used to receive an input signal.

[0015] In one or more embodiments of the present invention, the second-stage circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; the first end of the fifth transistor is connected to the power supply voltage, the second end of the fifth transistor is connected to the second end of the sixth transistor to output the first intermediate signal, the first end of the sixth transistor is connected to the second end of the seventh transistor, the first end of the seventh transistor is connected to the ground voltage, the control end of the fifth transistor and the control end of the sixth transistor are used to receive the input clock signal, and the control end of the seventh transistor is used to receive the first signal.

[0016] In one or more embodiments of the present invention, the third-stage circuit includes an eighth transistor, a first end of the eighth transistor is connected to the power supply voltage, a control end of the eighth transistor is used to receive a first intermediate signal, and a second end of the eighth transistor is used to output a first result signal.

[0017] In one or more embodiments of the present invention, the third-stage circuit further includes a ninth transistor and a tenth transistor, the second end of the ninth transistor being connected to the second end of the eighth transistor, the first end of the ninth transistor being connected to the second end of the tenth transistor, the control end of the ninth transistor being used to receive an input clock signal, the control end of the tenth transistor being used to receive a first intermediate signal, and the first end of the tenth transistor being connected to a ground voltage.

[0018] In one or more embodiments of the present invention, the first trigger, the second trigger, the third trigger and the fourth trigger have the same structure.

[0019] In one or more embodiments of the present invention, the inverting unit includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter is connected to the second output terminal of the first trigger to invert the first intermediate signal to generate a first result signal, the second inverter is connected to the second output terminal of the second trigger to invert the second intermediate signal to generate a second result signal, the third inverter is connected to the second output terminal of the third trigger to invert the third intermediate signal to generate a third result signal, and the fourth inverter is connected to the second output terminal of the fourth trigger to invert the fourth intermediate signal to generate a fourth result signal.

[0020] In one or more embodiments of the present invention, the phase of the first signal leads the phase of the input signal by 90°, the phase of the second signal leads the phase of the first signal by 90°, the phase of the third signal leads the phase of the second signal by 90°, and the phase of the fourth signal leads the phase of the third signal by 90°.

[0021] Compared with the prior art, the frequency divider of the present invention cascades the first trigger, the second trigger, the third trigger and the fourth trigger, so that each trigger can support the differential mode and be driven by the differential input clock signal to achieve frequency division by two while being able to output a signal with a 25% duty cycle, thereby eliminating the need for a dedicated 25% duty cycle output circuit, reducing power consumption and chip area; the frequency divider of the present invention achieves frequency division by two by cascading triggers, and has the advantages of high operating frequency, fast speed, low power consumption and small area. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some of the embodiments described in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts.

[0023] Figure 1 Schematic diagram of the structure of a radio frequency transceiver in the prior art.

[0024] Figure 2 Schematic diagram of the structure of a Gilbert active mixer in the prior art.

[0025] Figure 3 Schematic diagram of the structure of a 25% duty cycle passive mixer in the prior art.

[0026] Figure 4 This is a circuit schematic diagram of a local oscillator signal generating circuit with a 25% duty cycle in the prior art.

[0027] Figure 5 FIG. 4 is a structural diagram of a two-way frequency divider in one embodiment.

[0028] Figure 6 Schematic diagram of the structure of a first trigger in one embodiment.

[0029] Figure 7 FIG. 4 is a signal waveform diagram of a first trigger in an embodiment. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only a portion of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0031] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0032] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense.

[0033] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0034] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0035] Various components and devices may be referred to or shown in the singular herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular may include multiple such elements in accordance with the teachings herein.

[0036] The specification uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," which can each refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," etc. used with respect to the embodiments of the present disclosure are synonymous.

[0037] like Figure 5 As shown, a two-frequency divider in an embodiment of the present invention includes: a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, a fourth flip-flop DFF4 and an inverting unit.

[0038] The first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, and the fourth flip-flop DFF4 are cascaded. Specifically, the input terminal D1 of the first flip-flop DFF1 is connected to the third output terminal QB1 of the first flip-flop DFF1, the input terminal D2 of the second flip-flop DFF2 is connected to the third output terminal QB2 of the second flip-flop DFF2, the input terminal D3 of the third flip-flop DFF3 is connected to the third output terminal QB3 of the third flip-flop DFF3, and the input terminal D4 of the fourth flip-flop DFF4 is connected to the third output terminal QB4 of the fourth flip-flop DFF4. The input terminal D1 of the first flip-flop DFF1 is used to receive an input signal, the first output terminal M1 of the first flip-flop DFF1 outputs a first signal and is connected to the input terminal D2 of the second flip-flop DFF2, the first output terminal M2 of the second flip-flop DFF2 outputs a second signal and is connected to the input terminal D3 of the third flip-flop DFF3, the first output terminal M3 of the third flip-flop DFF3 outputs a third signal and is connected to the input terminal D4 of the fourth flip-flop DFF4, the first output terminal M4 of the fourth flip-flop DFF4 outputs a fourth signal, and the first output terminal M4 of the fourth flip-flop DFF4 is not connected to the input terminal D1 of the first flip-flop DFF1.

[0039] An inverting unit (not shown in the figure) is connected to the second output terminal N1 of the first flip-flop DFF1, the second output terminal N2 of the second flip-flop DFF2, the second output terminal N3 of the third flip-flop DFF3, and the second output terminal N4 of the fourth flip-flop DFF4. The inverting unit is configured to invert the first intermediate signal output from the second output terminal of the first flip-flop DFF1, the second intermediate signal output from the second output terminal of the second flip-flop DFF2, the third intermediate signal output from the second output terminal of the third flip-flop DFF3, and the fourth intermediate signal output from the second output terminal of the fourth flip-flop DFF4, respectively, to generate a first result signal, a second result signal, a third result signal, and a fourth result signal.

[0040] In one embodiment, the phase of the first signal leads the phase of the input signal by 90°, the phase of the second signal leads the phase of the first signal by 90°, the phase of the third signal leads the phase of the second signal by 90°, and the phase of the fourth signal leads the phase of the third signal by 90°. The duty cycles of the first result signal, the second result signal, the third result signal, and the fourth result signal are all 25%.

[0041] The first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, and the fourth flip-flop DFF4 are all driven by differential input clock signals CK and CKB. Specifically, the first clock terminal CK1 of the first flip-flop DFF1 is used to receive the first input clock signal CK, the second clock terminal CKB1 of the first flip-flop DFF1 is used to receive the second input clock signal CKB, the first clock terminal CK2 of the second flip-flop DFF2 is used to receive the second input clock signal CKB, the second clock terminal CKB2 of the second flip-flop DFF2 is used to receive the first input clock signal CK, the first clock terminal CK3 of the third flip-flop DFF3 is used to receive the first input clock signal CK, the second clock terminal CKB3 of the third flip-flop DFF3 is used to receive the second input clock signal CKB, the first clock terminal CK4 of the fourth flip-flop DFF4 is used to receive the second input clock signal CKB, and the second clock terminal CKB4 of the fourth flip-flop DFF4 is used to receive the first input clock signal CK.

[0042] In one embodiment, the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3 and the fourth flip-flop DFF4 have the same structure. The following takes the first flip-flop DFF1 as an example for detailed structural description.

[0043] like Figure 6As shown, the first flip-flop DFF1 includes a first-stage circuit 10, a second-stage circuit 20, and a third-stage circuit 30. The first-stage circuit 10 generates a first signal b based on the drive of the differential input clock signals CK and CKB and based on the input signal a. The second-stage circuit 20 is connected to the first-stage circuit 10 to receive the first signal b and generates a first intermediate signal c based on the drive of the first input clock signal CK. The third-stage circuit 30 is connected to the output terminal of the second-stage circuit 20 to receive the first intermediate signal c and generate a corresponding signal (input signal a).

[0044] In one embodiment, the first-stage circuit 10 includes a first transistor M0, a second transistor M2, a third transistor M3, and a fourth transistor M4. A first terminal of the first transistor M0 is connected to a power supply voltage VDD, a second terminal of the first transistor M0 is connected to a first terminal of the second transistor M2, and a second terminal of the second transistor M2 is connected to a second terminal of the third transistor M3, forming a first output terminal M1 of a first flip-flop DFF1 for outputting a first signal b. A first terminal of the third transistor M3 is connected to a second terminal of a fourth transistor M4, and a first terminal of the fourth transistor M4 is connected to a ground voltage VSS. A control terminal of the first transistor M0 and a control terminal of the fourth transistor M4 are connected to form an input terminal D1 of the first flip-flop DFF1 for receiving an input signal a. The control terminals of the second transistor M2 and the third transistor M3 are configured to receive differential input clock signals CK and CKB. In one embodiment, the control terminal of the second transistor M2 is configured to receive the first input clock signal CK, and the control terminal of the third transistor M3 is configured to receive the second input clock signal CKB. Thus, the first input clock signal CK and the second input clock signal CKB constitute a differential input clock signal.

[0045] The second-stage circuit 20 includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. A first terminal of the fifth transistor M5 is connected to a power supply voltage VDD, and a second terminal of the fifth transistor M5 is connected to a second terminal of the sixth transistor M6 to form a second output terminal N1 of the first flip-flop DFF1 for outputting a first intermediate signal c. A first terminal of the sixth transistor M6 is connected to a second terminal of the seventh transistor M7, and a first terminal of the seventh transistor M7 is connected to a ground voltage VSS. Control terminals of the fifth transistor M5 and the sixth transistor M6 are configured to receive a first input clock signal CK. A control terminal of the seventh transistor M7 is connected to a second terminal of the second transistor M2 and a second terminal of the third transistor M3 to receive the first signal.

[0046] The third-stage circuit 30 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. A first terminal of the eighth transistor M8 is connected to a power supply voltage VDD. A control terminal of the eighth transistor M8 is connected to a control terminal of the tenth transistor M10, a second terminal of the fifth transistor M5, and a second terminal of the sixth transistor M6 to receive a first intermediate signal c. A second terminal of the ninth transistor M9 is connected to a second terminal of the eighth transistor M8 to form a third output terminal QB1 of the first flip-flop DFF1 to output a corresponding signal (input signal a). A first terminal of the ninth transistor M9 is connected to a second terminal of the tenth transistor M10. A control terminal of the ninth transistor M9 is used to receive a first input clock signal CK. A first terminal of the tenth transistor M10 is connected to a ground voltage VSS. In other embodiments, the ninth transistor M9 and the tenth transistor M10 may not be provided.

[0047] The control end of the second transistor M2, the control end of the fifth transistor M5, the control end of the sixth transistor M6 and the control end of the ninth transistor M9 are connected to form the first clock end CK1 of the first trigger DFF1, and the control end of the third transistor M3 forms the second clock end CKB of the first trigger DFF1.

[0048] In one embodiment, the first transistor M0, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 are P-channel MOS transistors. The third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are N-channel MOS transistors. The first terminal of each transistor is a source, the second terminal of each transistor is a drain, and the control terminal of each transistor is a gate.

[0049] In other embodiments, the first transistor M0, the second transistor M2, the fifth transistor M5, and the eighth transistor M8 may be N-channel MOS transistors, and the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 may be P-channel MOS transistors.

[0050] In one embodiment, the inverting unit includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The first inverter is connected to the second output terminal of the first flip-flop DFF1 to invert the first intermediate signal c to generate a first result signal, the second inverter is connected to the second output terminal of the second flip-flop to invert the second intermediate signal to generate a second result signal, the third inverter is connected to the second output terminal of the third flip-flop to invert the third intermediate signal to generate a third result signal, and the fourth inverter is connected to the second output terminal of the fourth flip-flop to invert the fourth intermediate signal to generate a fourth result signal.

[0051] like Figure 7 and 6As shown, assuming that the initial voltages of the first input clock signal CK and the input signal a are both 0, and the initial voltage of the second input clock signal CKB is 1, then the initial values ​​of the first signal b and the first intermediate signal c are 1. When the rising edge of the first input clock signal CK arrives, due to the setting of the third transistor M3 and the second input clock signal CKB being 0, the first signal b remains at 1, the first intermediate signal c becomes 0, and the input signal a becomes 1; then the falling edge of the first input clock signal CK arrives, due to the second input clock signal CKB being 1, the first signal b becomes 0, the first intermediate signal c becomes 1, and the input signal a remains, and the cycle continues in sequence. Finally, it can be obtained that the rising edge of the first signal b leads the rising edge of the input signal a by 90°, the duty cycles of the input signal a and the first signal b are both 50%, and the two-way frequency division outputs the first intermediate signal c with a duty cycle of 75%. The first inverter inverts the first intermediate signal c to generate a first result signal with a duty cycle of 25%.

[0052] The cascade connection of the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, and the fourth flip-flop DFF4 forms a divide-by-two circuit. According to the aforementioned analysis, the first signal b leads the input signal a by 90°. Similarly, the second signal leads the first signal b by 90°, and the second signal leads the input signal a by 180°. The third signal leads the second signal by 90°, and the third signal leads the input signal a by 270°. The fourth signal leads the third signal by 90°, and the fourth signal leads the input signal a by 360° (i.e., the phases are the same). The duty cycle of the second, third, and fourth signals is 50%. The duty cycle of the second, third, and fourth intermediate signals is 75%. The second, third, and fourth inverters are used to ensure that the duty cycle of the second, third, and fourth result signals is 25%.

[0053] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed within the present invention. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0054] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A two-way frequency divider, characterized in that: include: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and an inverting unit; The input terminal of the first trigger is connected to the third output terminal of the first trigger, the input terminal of the second trigger is connected to the third output terminal of the second trigger, the input terminal of the third trigger is connected to the third output terminal of the third trigger, and the input terminal of the fourth trigger is connected to the third output terminal of the fourth trigger. The input terminal of the first trigger is used to receive an input signal, the first output terminal of the first trigger outputs a first signal and is connected to the input terminal of the second trigger, the first output terminal of the second trigger outputs a second signal and is connected to the input terminal of the third trigger, the first output terminal of the third trigger outputs a third signal and is connected to the input terminal of the fourth trigger, and the first output terminal of the fourth trigger outputs a fourth signal. The first trigger, the second trigger, the ... first trigger, the second trigger, the first trigger, the second trigger, the first trigger, the second trigger, the first trigger, the first trigger, the second trigger, the first trigger, the second trigger, the The trigger, the third trigger, and the fourth trigger are all driven by a differential input clock signal. The inverting unit is connected to the second output terminal of the first trigger, the second output terminal of the second trigger, the second output terminal of the third trigger, and the second output terminal of the fourth trigger. The inverting unit is used to invert the first intermediate signal output from the second output terminal of the first trigger, the second intermediate signal output from the second output terminal of the second trigger, the third intermediate signal output from the second output terminal of the third trigger, and the fourth intermediate signal output from the second output terminal of the fourth trigger to generate a first result signal, a second result signal, a third result signal, and a fourth result signal. The duty cycle of the first result signal, the second result signal, the third result signal, and the fourth result signal is 25%.

2. The frequency divider according to claim 1, wherein: The first clock end of the first trigger is used to receive a first input clock signal, the second clock end of the first trigger is used to receive a second input clock signal, the first clock end of the second trigger is used to receive the second input clock signal, the second clock end of the second trigger is used to receive the first input clock signal, the first clock end of the third trigger is used to receive the first input clock signal, the second clock end of the third trigger is used to receive the second input clock signal, the first clock end of the fourth trigger is used to receive the second input clock signal, and the second clock end of the fourth trigger is used to receive the first input clock signal.

3. The two-way frequency divider according to claim 1, wherein: The first trigger includes a first-stage circuit, a second-stage circuit and a third-stage circuit. The first-stage circuit generates a first signal based on the drive of a differential input clock signal and based on the input signal. The second-stage circuit is connected to the first-stage circuit to receive the first signal and generates a first intermediate signal based on the drive of the clock input signal. The third-stage circuit is connected to the input end of the second-stage circuit.

4. The two-way frequency divider according to claim 3, wherein: The first-stage circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first end of the first transistor is connected to the power supply voltage, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is connected to the second end of the third transistor to output a first signal, the first end of the third transistor is connected to the second end of the fourth transistor, the first end of the fourth transistor is connected to the ground voltage, the control end of the second transistor and the control end of the third transistor are used to receive a differential input clock signal, and the control end of the first transistor and the control end of the fourth transistor are used to receive an input signal.

5. The two-way frequency divider according to claim 3, wherein: The second-stage circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; the first end of the fifth transistor is connected to the power supply voltage, the second end of the fifth transistor is connected to the second end of the sixth transistor to output the first intermediate signal, the first end of the sixth transistor is connected to the second end of the seventh transistor, the first end of the seventh transistor is connected to the ground voltage, the control end of the fifth transistor and the control end of the sixth transistor are used to receive the input clock signal, and the control end of the seventh transistor is used to receive the first signal.

6. The two-way frequency divider according to claim 3, wherein: The third-stage circuit includes an eighth transistor, a first terminal of the eighth transistor is connected to a power supply voltage, a control terminal of the eighth transistor is used to receive a first intermediate signal, and a second terminal of the eighth transistor is used to output a first result signal.

7. The two-way frequency divider according to claim 6, wherein: The third-stage circuit also includes a ninth transistor and a tenth transistor, the second end of the ninth transistor is connected to the second end of the eighth transistor, the first end of the ninth transistor is connected to the second end of the tenth transistor, the control end of the ninth transistor is used to receive an input clock signal, the control end of the tenth transistor is used to receive a first intermediate signal, and the first end of the tenth transistor is connected to the ground voltage.

8. The two-way frequency divider according to claim 1, wherein: The first trigger, the second trigger, the third trigger and the fourth trigger have the same structure.

9. The two-way frequency divider according to claim 1, wherein: The inverting unit includes a first inverter, a second inverter, a third inverter and a fourth inverter. The first inverter is connected to the second output terminal of the first trigger to invert the first intermediate signal to generate a first result signal. The second inverter is connected to the second output terminal of the second trigger to invert the second intermediate signal to generate a second result signal. The third inverter is connected to the second output terminal of the third trigger to invert the third intermediate signal to generate a third result signal. The fourth inverter is connected to the second output terminal of the fourth trigger to invert the fourth intermediate signal to generate a fourth result signal.

10. The two-way frequency divider according to claim 1, wherein: The phase of the first signal leads the phase of the input signal by 90°, the phase of the second signal leads the phase of the first signal by 90°, the phase of the third signal leads the phase of the second signal by 90°, and the phase of the fourth signal leads the phase of the third signal by 90°.

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