Current steering digital-to-analog converter and layout structure thereof
By optimizing the conversion unit structure and layout of the current-steering digital-to-analog converter and reducing the connection channels, the area and power consumption of the current-steering digital-to-analog converter are optimized, the device frequency is increased and the response time is reduced.
Patent Information
- Application Number
- CN202422820948.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2034-11-19
AI Technical Summary
Existing current-steering digital-to-analog converters have major problems in terms of area and power consumption. As the number of bits increases, the device power consumption and area are difficult to meet design requirements.
A plurality of conversion unit structures are adopted, each conversion unit includes a first transistor, a second transistor, a third transistor and a fourth transistor, which constitute a current source transistor and a switch tube of a common source and common gate structure. By optimizing the layout and layout design of the conversion unit, the connection channels are reduced and the current passing capacity is guaranteed.
The method realizes simple layout, reduces device area, increases device frequency, reduces response time and power consumption, and solves the problems of large area and power consumption of existing current-steering digital-to-analog converters.
Smart Images
Figure CN223334670U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuit design, in particular to a current-steering digital-to-analog converter and a layout structure thereof. Background Art
[0002] A digital-to-analog converter (DAC) is a device that converts digital quantities into analog quantities. There are many types of DACs, categorized by the circuit weighting method: voltage-type, charge-type, and current-type. Current-type DACs, also known as current-steering DACs, are categorized by their structure, including voltage divider, capacitor-weighted current, resistor-weighted current, resistor-capacitor combination, R-2R network, active resistor network, and segmented combination.
[0003] Currently commonly used current-steering DACs require a large device to distribute the current, while also requiring large resistor or capacitor loads at the output, slowing down the conversion speed. Furthermore, the number of required resistors and capacitors increases exponentially with the number of bits. Consequently, as the number of bits increases, the power consumption and area overhead of commonly used current-steering DACs become difficult to meet design requirements. Utility Model Content
[0004] The purpose of the utility model is to provide a current-steering digital-to-analog converter and its layout structure, so as to solve the problems of large area and power consumption of existing current-steering digital-to-analog converters.
[0005] In order to solve the above technical problems, the utility model provides a current-steering digital-to-analog converter, comprising a plurality of conversion units, each of which comprises a first transistor, a second transistor, a third transistor and a fourth transistor; the drain of the first transistor is connected to the source of the second transistor to form a current source transistor with a common-source and common-gate structure; the source of the third transistor and the source of the fourth transistor are both connected to the drain of the second transistor to form a switching tube.
[0006] Optionally, in the current-steering digital-to-analog converter, the sources of the first transistors in all the conversion units are connected, the gates of the first transistors are connected, the drains of the third transistors are connected, and the drains of the fourth transistors are connected.
[0007] Optionally, in the current-steering digital-to-analog converter, the first transistor, the second transistor, the third transistor and the fourth transistor are all NMOS.
[0008] Optionally, in the current-steering digital-to-analog converter, each of the conversion units further includes a decoder, and the decoder is connected to the switch tube.
[0009] In order to solve the above technical problems, the present invention also provides a layout structure of a current-steering digital-to-analog converter, wherein a plurality of the conversion units are arranged in a straight line at intervals along a first direction, and the current source transistors and the switch tubes are arranged along a second direction, wherein the first direction is perpendicular to the second direction.
[0010] Optionally, in the layout structure of the current-steering digital-to-analog converter, the layout width of each conversion unit is determined by the channel size of the current source transistor, the channel size of the switch tube, and the connection width that meets design requirements.
[0011] Optionally, in the layout structure of the current-steering digital-to-analog converter, in each of the conversion units, the first transistor and the second transistor are arranged in sequence along the second direction, and a connection is arranged between the drain and gate of the first transistor and the source of the second transistor; the third transistor and the fourth transistor are symmetrically arranged along the second direction, and a connection is arranged between the source of the third transistor and the source of the fourth transistor and the drain of the second transistor.
[0012] Optionally, in the layout structure of the current-steering digital-to-analog converter, the low-order conversion unit in all the conversion units is located in the middle position of the plurality of conversion units arranged in a line at intervals.
[0013] Optionally, in the layout structure of the current-steering digital-to-analog converter, the source of the first transistor in all the conversion units is penetrated by the upper metal layer, the gate of the first transistor is penetrated by the upper metal layer, the drain of the third transistor is penetrated by the upper metal layer, and the drain of the fourth transistor is penetrated by the upper metal layer.
[0014] Optionally, in the layout structure of the current-steering digital-to-analog converter, each conversion unit is also provided with a decoder according to the layout width of the conversion unit, and the decoder is located on the side of the switching tube away from the current source transistor, and a connection is arranged between the switching tube.
[0015] The present invention provides a current-steering digital-to-analog converter and its layout structure, comprising a plurality of conversion units, each of which includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the drain of the first transistor is connected to the source of the second transistor to form a current source transistor in a cascode structure; the source of the third transistor and the source of the fourth transistor are both connected to the drain of the second transistor to form a switch transistor. By optimizing the structure and layout of the conversion units, the current flow capacity is guaranteed while reducing the number of wiring channels, thereby simplifying the layout and reducing the device area, improving the device frequency, reducing the response time, and reducing the power consumption, thereby resolving the large area and power consumption issues of existing current-steering digital-to-analog converters. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic structural diagram of a conversion unit provided in this embodiment;
[0017] Figure 2 A schematic diagram of a circuit of a conversion unit provided in this embodiment;
[0018] Figure 3 A circuit schematic diagram of a current-steering digital-to-analog converter provided in this embodiment;
[0019] Figure 4 A schematic diagram of the circuit structure of the current source transistor provided in this embodiment;
[0020] Figure 5 This is a flow chart of the design process of the layout structure of the current-steering digital-to-analog converter provided in this embodiment. DETAILED DESCRIPTION
[0021] The following is a further detailed description of the current-steering digital-to-analog converter and its layout structure proposed by the present invention, in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, different drawings may need to show different focuses and sometimes use different scales.
[0022] It should be noted that the terms "first", "second", etc. in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, and are not used to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products, or apparatuses.
[0023] This embodiment provides a current steering type digital-to-analog converter, including a plurality of conversion units, such as Figure 1 As shown, each of the conversion units includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first transistor is connected to the second transistor to form a current source transistor with a common source and common gate structure; the third transistor and the fourth transistor constitute a switching tube, and the third transistor and the fourth transistor are both connected to the second transistor.
[0024] The current-steering digital-to-analog converter provided in this embodiment optimizes the structure and layout of the conversion unit, thereby reducing the routing channels while ensuring the current passing capacity, thereby not only simplifying the layout and reducing the device area, but also improving the device frequency, reducing the response time and power consumption, and solving the problems of large area and power consumption of existing current-steering digital-to-analog converters.
[0025] Specifically, in this embodiment, Figure 2 As shown, the drain of the first transistor Q1 is connected to the source of the second transistor Q2 to form a current source transistor with a common source and common gate structure; the source of the third transistor Q3 and the source of the fourth transistor Q4 are both connected to the drain of the second transistor Q2 to form a switch tube.
[0026] In a specific embodiment, the first transistor Q1 , the second transistor Q2 , the third transistor Q3 , and the fourth transistor Q4 are all NMOS transistors.
[0027] In order to realize the digital-to-analog conversion function of the current-steering digital-to-analog converter, each conversion unit further includes a decoder, which is connected to the switch tube. The specific method of connecting the decoder and the switch tube is well known to those skilled in the art and will not be described in detail in this application.
[0028] Furthermore, in this embodiment, Figure 3As shown, the sources of the first transistors Q1 in all the conversion units are connected, the gates of the first transistors Q1 are connected, the drains of the third transistors Q3 are connected, and the drains of the fourth transistors Q4 are connected.
[0029] In this way, all the first transistors Q1 can be connected to the power supply through the line connected to the source, thereby replicating and distributing the power supply in the form of branches, so that each conversion unit can obtain a stable power input; all the first transistors Q1 can be connected to the bias voltage through the line connected to the gate, so that the current source transistor in the common source and common gate structure (CASCODE) formed by the first transistor Q1 and the second transistor Q2 can effectively reduce the first-order system error (such as doping concentration gradient, oxide layer thickness gradient, voltage drop on the power line) and second-order system error (such as temperature gradient, stress), thereby effectively improving the device performance; the drains of all the third transistors Q3 are connected, and the drains of all the fourth transistors Q4 are connected, which can organically combine the decoders connected thereto, thereby meeting the requirements for high-bit decoding without the need for an exponential increase in the number of components, effectively reducing the power consumption and area of the device.
[0030] In order to realize the process of manufacturing the above-mentioned current steering type digital-to-analog converter, this embodiment also provides a layout structure of a current steering type digital-to-analog converter, such as Figure 3 As shown, the multiple conversion units are arranged in a straight line along the first direction, and the current source transistors (the first transistor Q1 and the second transistor Q2) and the switch transistors (the third transistor Q3 and the fourth transistor Q4) are arranged along the second direction, wherein the first direction is perpendicular to the second direction.
[0031] When designing the actual layout structure, the layout width of the conversion units needs to be considered when the units are arranged in a straight line along the first direction. In this embodiment, the layout width of each conversion unit is determined by the channel size of the current source transistor, the channel size of the switch transistor, the connection width that meets the design requirements, and the layout size required by the decoder. The connection width that meets the design requirements is mainly determined by the design requirements for current, that is, the connection width must meet the overcurrent capability.
[0032] Furthermore, in this embodiment, in each of the conversion units, the first transistor Q1 and the second transistor Q2 are sequentially arranged along the second direction, and a connection is arranged between the drain of the first transistor Q1 and the source of the second transistor Q2 to electrically connect the first transistor Q1 and the second transistor Q2; the third transistor Q3 and the fourth transistor Q4 are symmetrically arranged along the second direction, and a connection is arranged between the source of the third transistor Q3 and the source of the fourth transistor Q4 and the drain of the second transistor Q2 to electrically connect the third transistor Q3 and the fourth transistor Q4 to the second transistor Q2.
[0033] Preferably, in order to reduce the layout area and the complexity of the connections as much as possible, in this embodiment, all the connections are the shortest connections.
[0034] By minimizing wiring, designing symmetrical transistors, and implementing internal wiring, the conversion unit's wiring is simplified, minimizing footprint and effectively reducing device power consumption. Of course, the wiring width must meet the current handling capacity.
[0035] Taking into account the higher matching of the low-order conversion units, and in the current-steering digital-to-analog converter provided in this embodiment, the high- and low-order conversion units can be shuffled as needed without being arranged in sequence and without complicated additional wiring. Therefore, when performing layout design, the low-order conversion unit among all the conversion units is located in the middle position of the multiple conversion units arranged in a straight line.
[0036] In addition, in the actual layout design, if Figure 4 As shown, the wiring between the current source transistors in the common-source common-gate structure is not connected, and the number of split gates of each individual transistor is n. The SPLIT GATE setting can be modified in the LVS (load balancing) setting in the layout design software, which can greatly reduce the number of wiring and thus reduce parasitics.
[0037] Furthermore, in this embodiment, the source of the first transistor Q1 in all the conversion units is penetrated by the upper metal layer, the gate of the first transistor Q1 is penetrated by the upper metal layer, the drain of the third transistor Q3 is penetrated by the upper metal layer, and the drain of the fourth transistor Q4 is penetrated by the upper metal layer.
[0038] In addition, each of the conversion units is also provided with a decoder according to the layout width of the conversion unit. The decoder is located on the side of the switch tube away from the current source transistor, and a connection line is arranged between the switch tube to electrically connect the decoder to the switch tube.
[0039] The following, combined Figure 5 , illustrating the design process of the layout structure of the current-steering digital-to-analog converter provided by this embodiment:
[0040] First, the size of the conversion unit layout structure is determined according to the circuit structure of the conversion unit to obtain a layout block.
[0041] Specifically, since the structure of the conversion unit of the current-steering digital-to-analog converter provided in this embodiment is in the shape of a vertical strip, the width of the conversion unit layout structure needs to be mainly considered when designing the layout structure. This width needs to be determined based on many factors, including but not limited to the channel length and width of the common-gate common-source transistor, the channel length and width of the switch tube, the layout size of the decoder (including the decoding circuit), the metal width that meets the design requirements, etc.
[0042] After the width is determined, the layout can be divided into multiple blocks according to the width. To fully utilize the layout area, when the conversion unit of the current-steering DAC is in the form of a vertical strip, the blocks are arranged in a straight line along the width of the conversion unit.
[0043] Then, the conversion unit layout structure is made within the layout block.
[0044] Specifically, the first transistor and the second transistor constituting the current source transistor are designed with a common source and common gate, the third transistor and the fourth transistor are designed symmetrically, the internal connections of each transistor are well made, the connections of each transistor are shortened, and the width of the connection metal must ensure the overcurrent requirement.
[0045] Of course, since the layout structures of the conversion units in multiple layout blocks are the same, after completing the design of the layout structure of the conversion units in one layout block, the design of the layout structure of the conversion units in all layout blocks can be completed by copying.
[0046] In some design scenarios, the current layout block size does not meet the width of the conversion unit layout structure (such as at the edge of the layout). In this case, the device in the layout block can be made into a dummy device.
[0047] Next, the layout structures of the multiple conversion units are sorted according to circuit requirements.
[0048] Specifically, the low-order units are placed in the middle part. Since this part has a higher matching property, it can be shuffled as needed and does not need to be arranged in sequence. At the same time, there is no complicated additional wiring. In this way, the number of wirings can be reduced, thereby reducing parasitics.
[0049] Afterwards, the upper metal layer is used to organically connect the conversion unit layout structures within all layout blocks.
[0050] Specifically, the sources of all first transistors are penetrated by the upper metal layer, the gates of all first transistors are penetrated by the upper metal layer, the drains of all third transistors are penetrated by the upper metal layer, and the drains of all fourth transistors are penetrated by the upper metal layer.
[0051] Finally, the decoder is arranged according to the layout width of the conversion unit.
[0052] Specifically, a decoding digital circuit is manufactured with a layout width of a single conversion unit to correspond one-to-one with the current source part.
[0053] The layout structure of the current-steering digital-to-analog converter provided in this embodiment greatly reduces the connection channels, thereby reducing parasitics, reducing the layout area, simplifying the layout, and reducing the workload; moreover, the layout structure of the current-steering digital-to-analog converter provided in this embodiment can meet the current passing capacity while maximizing the frequency, reducing the response time, and reducing the device power consumption.
[0054] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and this utility model does not limit this.
[0055] The current-steering digital-to-analog converter and its layout structure provided in this embodiment include multiple conversion units, each of which includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the drain of the first transistor is connected to the source of the second transistor to form a current source transistor in a cascode structure; the source of the third transistor and the source of the fourth transistor are both connected to the drain of the second transistor to form a switch transistor. By optimizing the structure and layout of the conversion units, while reducing the number of wiring channels, the current flow capacity is guaranteed. This not only simplifies the layout and reduces the device area, but also improves the device frequency, reduces the response time and power consumption, and solves the problems of large area and power consumption of existing current-steering digital-to-analog converters.
[0056] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A current-steering digital-to-analog converter, characterized in that: It includes multiple conversion units, each of which includes a first transistor, a second transistor, a third transistor and a fourth transistor; the drain of the first transistor is connected to the source of the second transistor to form a current source transistor with a common source and common gate structure; the source of the third transistor and the source of the fourth transistor are both connected to the drain of the second transistor to form a switching tube.
2. The current-steering digital-to-analog converter according to claim 1, wherein: The sources of the first transistors in all the conversion units are connected, the gates of the first transistors are connected, the drains of the third transistors are connected, and the drains of the fourth transistors are connected.
3. The current-steering digital-to-analog converter according to claim 1, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.
4. The current-steering digital-to-analog converter according to claim 1, wherein: Each of the conversion units further includes a decoder, and the decoder is connected to the switch tube.
5. A layout structure of a current-steering digital-to-analog converter according to any one of claims 1 to 4, characterized in that: The plurality of conversion units are arranged in a line at intervals along a first direction, and the current source transistors and the switch tubes are arranged along a second direction, wherein the first direction is perpendicular to the second direction.
6. The layout structure of the current-steering digital-to-analog converter according to claim 5, characterized in that: The layout width of each conversion unit is determined by the channel size of the current source transistor, the channel size of the switch tube, and the connection width that meets the design requirements.
7. The layout structure of the current-steering digital-to-analog converter according to claim 5, characterized in that: In each of the conversion units, the first transistor and the second transistor are arranged in sequence along the second direction, and a connection is arranged between the drain of the first transistor and the source of the second transistor; the third transistor and the fourth transistor are symmetrically arranged along the second direction, and a connection is arranged between the source of the third transistor and the source of the fourth transistor and the drain of the second transistor.
8. The layout structure of the current-steering digital-to-analog converter according to claim 5, characterized in that: The low-order conversion unit in all the conversion units is located in the middle of the plurality of conversion units arranged in a line at intervals.
9. The layout structure of the current-steering digital-to-analog converter according to claim 5, wherein: The source of the first transistor in all the conversion units is penetrated by the upper metal layer, the gate of the first transistor is penetrated by the upper metal layer, the drain of the third transistor is penetrated by the upper metal layer, and the drain of the fourth transistor is penetrated by the upper metal layer.
10. The layout structure of the current-steering digital-to-analog converter according to claim 5, characterized in that: Each of the conversion units is further provided with a decoder according to the layout width of the conversion unit. The decoder is located on a side of the switch tube away from the current source transistor and is connected to the switch tube.