Monocrystalline silicon strain gauge

Abstract

The utility model relates to the related technical field of MEMS pressure sensors, and specifically relates to a monocrystalline silicon strain gauge. The monocrystalline silicon strain gauge comprises a silicon substrate and a device layer, the substrate is monocrystalline silicon, the device layer is deposited on the substrate, and the device layer is composed of a piezoresistive strip, a heavily doped region, an insulating layer and a metal layer. The core of the manufacturing method of the monocrystalline silicon strainmeter is that H < + > or He < + > is injected into a silicon substrate by using a high-energy ion implanter to form a damaged layer, then after a device layer is completed, the substrate is stripped from the damaged layer by annealing, and the thickness of the formed substrate is 3-20 [mu] m. The defect that the thickness of the final substrate cannot be guaranteed due to front protection and back thinning corrosion in the manufacturing process of the substrate is overcome. Therefore, the yield of finished products is improved, and the consistency and stability of the glass micro-melting pressure sensor are greatly improved.

Description

Technical Field

[0001] The utility model relates to the technical field related to MEMS pressure sensors, and in particular to a single crystal silicon strain gauge. Background Art

[0002] Single-crystal silicon strain gauges are primarily the core of glass micro-melted pressure sensors. Their primary advantages are excellent media tolerance and strong overload resistance. They are used for high-pressure measurements in automotive and industrial applications, with particular strengths in high-pressure applications such as diesel common rails, loader hydraulics, and fuel pumps. For measurements above 500 kPa, they can replace diffused silicon pressure sensors. They are made by sintering glass powder at high temperatures. After the glass melts above 500°C, the silicon strain gauge is sintered onto a 17-4PH stainless steel sensitive elastomer.

[0003] Conventional silicon strain gauges used for glass micromelting utilize SOI substrates, which are expensive and unsuitable for large-scale production. The main process flow for producing single-crystal silicon strain gauges is as follows: silicon wafer cleaning and drying → photolithography of the resistor area → concentrated boron diffusion → oxide layer and silicon nitride → metallization of leads and pads → alloying → photolithography of the PAD → front protection and backside thinning and etching → chip cleaning and separation. However, the substrate fabrication process involves front protection and backside thinning and etching, and the wet etching process lacks a self-stop layer, making it impossible to guarantee the final substrate thickness, reducing the yield of the finished product and significantly impacting the ultimate performance of the glass micromelting pressure sensor.

[0004] In order to overcome the deficiencies of the prior art, the present invention proposes a single crystal silicon strain gauge. Utility Model Content

[0005] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a single crystal silicon strain gauge, which can ensure the thickness of the final substrate, improve the yield rate of the finished product, and improve the stability of the glass micro-melting pressure sensor.

[0006] The utility model provides a single crystal silicon strain gauge, comprising: a silicon substrate and a device layer, wherein the silicon substrate is single crystal silicon, the device layer is deposited on the silicon substrate, the device layer comprises a piezoresistive strip, a heavily doped region, an insulating layer and a metal layer, and the silicon substrate and the device layer have the same planar dimensions.

[0007] Furthermore, the silicon substrate has a thickness of 3 to 20 μm, and the device layer has a thickness of 1 to 5 μm.

[0008] Furthermore, the thickness of the silicon substrate is 10 μm, and the thickness of the device layer is 3 μm.

[0009] Furthermore, the inner contour, outer contour and chamfer of the silicon substrate and the device layer are all rounded.

[0010] Furthermore, the piezoresistive strips are arranged laterally and embedded in the upper surface of the silicon substrate by diffusion or injection, with a depth of 0.1 μm to 2 μm.

[0011] Furthermore, the heavily doped region is connected to the lateral piezoresistive strip and is embedded in the upper surface of the silicon substrate by diffusion or injection, with a depth of 0.2 μm to 3 μm.

[0012] Furthermore, when the silicon substrate is N-type, the piezoresistive strips and the heavily doped regions are P-type; when the substrate is P-type, the piezoresistive strips and the heavily doped regions are N-type doped.

[0013] Furthermore, the insulating layer covers the piezoresistive strip, and the insulating layer material may be one or a combination of silicon dioxide and silicon nitride.

[0014] Furthermore, the metal layer is located on the heavily doped region, and the metal layer is one or more combinations of aluminum, gold, platinum, chromium, titanium, and copper. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention is further described below with reference to the accompanying drawings and embodiments:

[0016] Figure 1 This is a schematic diagram of the three-dimensional structure of a single crystal silicon strain gauge proposed by the present invention;

[0017] Figure 2 This is a process flow chart for manufacturing a single crystal silicon strain gauge proposed by the present invention. DETAILED DESCRIPTION

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0019] Reference Figure 1 In this embodiment, a single-crystal silicon strain gauge 100 includes a silicon substrate 1 and a device layer 2. The silicon substrate 1 is single-crystal silicon. The device layer 2 is deposited on the silicon substrate 1 and consists of a piezoresistive strip 21, a heavily doped region 22, an insulating layer 23, and a metal layer. The substrate and device layer have identical planar dimensions. The thickness of the silicon substrate 1 is 3 to 20 μm, and the thickness of the device layer 2 is 1 to 5 μm. In this embodiment, the thickness of the silicon substrate 1 is preferably 10 μm, and the thickness of the device layer 2 is preferably 3 μm. The device layer 2 deposited on the silicon substrate 1 achieves the best results.

[0020] The inner and outer corners of the silicon substrate 1 and device layer 2 are rounded. Piezoresistive strips 21 are arranged horizontally and embedded into the substrate surface by diffusion or injection to a depth of 0.1 μm to 2 μm. In this embodiment, a depth of 1 μm is preferred for the piezoresistive strips 21, which is less susceptible to disconnection and achieves the best piezoresistive effect.

[0021] The heavily doped region 22 is connected to the lateral piezoresistive strip 21 and is embedded in the substrate surface by diffusion or implantation to a depth of 0.2 μm to 3 μm. In this embodiment, the heavily doped region 22 preferably has a depth of 1.5 μm, which achieves the best connection between the heavily doped region 22 and the piezoresistive strip 21.

[0022] When the silicon substrate 1 is N-type, the piezoresistive strip 21 and the heavily doped region 22 are P-type; when the substrate 1 is P-type, the piezoresistive strip 21 and the heavily doped region 22 are N-type doped.

[0023] The insulating layer 23 covers the piezoresistive strip 21 . The insulating layer material may be silicon dioxide or silicon nitride, or a combination thereof.

[0024] The metal layer, located above the heavily doped region 22 and serving as the electrical connection between the leads 24 and the pads 25, can be made of one or a combination of aluminum, gold, platinum, chromium, titanium, and copper. This ensures the thickness of the final substrate, improves the yield rate of the finished product, and enhances the ultimate performance of the glass micro-melt pressure sensor.

[0025] Reference Figure 2 , the utility model provides a single crystal silicon strain gauge manufacturing process flow chart:

[0026] 1) Rinse the single crystal silicon substrate with a thickness greater than 500 μm with deionized water, and use a spin dryer to dry the water on the surface of the substrate;

[0027] 2) Use high energy ion implantation machine to inject H + Or He + Implant into the silicon substrate to a depth of 3 to 20 μm to form a damage layer;

[0028] 3) Spin-coat the photoresist and develop the lateral piezoresistive strip pattern with an implantation dose of 1E14 to 5E14 cm -2 , the energy is 60~100KeV, and the glue is removed after the implantation is completed;

[0029] 4) Spin-coat the photoresist and develop the heavily doped area with a dose of 5E15 to 1E16 cm -2 , the energy is 80~120KeV, and the glue is removed after the implantation is completed;

[0030] 5) High temperature annealing to activate the implanted boron ions, using a rapid annealing furnace at an annealing temperature of 950-1100°C;

[0031] 6) Deposition of insulating layer silicon dioxide and silicon nitride with a thickness of 200 to 1000 nm, spin coating of photoresist, patterning by photolithography, etching to form openings in heavily doped areas, and de-resisting;

[0032] 7) A metal layer with a thickness of 500 to 1200 nm is deposited on the insulating film by magnetron sputtering or evaporation, the film is coated with glue, photolithography is performed, leads and pads are etched out, and the glue is removed; 8) Annealing and alloying are performed and excess substrate is peeled off, using a furnace tube annealing temperature of 400 to 450° C. for at least 5 hours to peel the substrate from the damaged layer, and the resulting substrate thickness is 3 to 20 μm.

Claims

1. A single crystal silicon strain gauge, comprising: A silicon substrate and a device layer, wherein the silicon substrate is single crystal silicon and the device layer is deposited on the silicon substrate. The device layer comprises a piezoresistive strip, a heavily doped region, an insulating layer and a metal layer. The silicon substrate and the device layer have the same planar dimensions.

2. The single crystal silicon strain gauge according to claim 1, characterized in that: The thickness of the silicon substrate is 3 to 20 μm, and the thickness of the device layer is 1 to 5 μm.

3. The single crystal silicon strain gauge according to claim 1, characterized in that: The thickness of the silicon substrate is 10 μm, and the thickness of the device layer is 3 μm.

4. The single crystal silicon strain gauge according to claim 1, characterized in that: The inner contour, outer contour and chamfer angle of the silicon substrate and the device layer are all rounded.

5. The single crystal silicon strain gauge according to claim 1, characterized in that: The piezoresistive strips are arranged laterally and embedded in the upper surface of the silicon substrate by diffusion or injection, with a depth of 0.1 μm to 2 μm.

6. The single crystal silicon strain gauge according to claim 1, characterized in that: The heavily doped region is connected to the lateral piezoresistive strip and is embedded in the upper surface of the silicon substrate by diffusion or injection, with a depth of 0.2 μm to 3 μm.

7. The single crystal silicon strain gauge according to claim 1, characterized in that: When the silicon substrate is N-type, the piezoresistive strips and the heavily doped region are P-type; when the substrate is P-type, the piezoresistive strips and the heavily doped region are N-type doped.

8. The single crystal silicon strain gauge according to claim 1, characterized in that: The insulating layer covers the piezoresistive strip, and the insulating layer material is one or a combination of silicon dioxide and silicon nitride.

9. The single crystal silicon strain gauge according to claim 1, characterized in that: The metal layer is located on the heavily doped region, and the metal layer is one or more combinations of aluminum, gold, platinum, chromium, titanium, and copper.

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