Power-off control circuit and electronic equipment

Abstract

The utility model discloses a power-off control circuit and electronic equipment. The power-off control circuit comprises a voltage reduction branch, an energy storage branch, a first switch branch, a second switch branch and at least one delay discharge branch. The step-down branch outputs a first voltage. The energy storage branch is charged when the first switch branch is switched off and is discharged when the first switch branch is switched on. The first switch branch is switched on when the difference value between the voltage of the energy storage branch and the voltage of the input power supply is larger than a first preset threshold value, and is switched off when the difference value between the voltage of the energy storage branch and the voltage of the input power supply is smaller than or equal to the first preset threshold value. The second switch branch is conducted when the first switch branch is conducted so as to output a low-level signal, and is disconnected when the first switch branch is disconnected. And the delay discharge branch discharges when receiving the low-level signal and charges when not receiving the low-level signal. Through the mode, the risk that the power supply chip is powered off abnormally can be reduced, so that the probability that elements in the electronic equipment are damaged is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic circuits, and in particular to a power-off control circuit and an electronic device. Background Art

[0002] With the popularization of electronic devices, data loss and hardware damage caused by abnormal power outages have become common problems. Specifically, during the normal operation of an electronic device, when the input power of the electronic device is abnormally cut off, the motherboard in the electronic device cannot normally execute the shutdown sequence due to the short voltage drop time. Subsequently, the enable pin of the power chip in the electronic device cannot receive the normal power-off signal, causing the power chip on the motherboard to abnormally power off, that is, the power-off process of the power chip is uncontrolled, and even causes the output voltage of some power chips to abnormally surge and then decrease. When the output voltage surge is large, the probability of components in the electronic device being damaged is high. Utility Model Content

[0003] The embodiments of the present application provide a power-off control circuit and an electronic device, which can reduce the risk of abnormal power-off of a power chip, thereby reducing the probability of damage to components in the electronic device.

[0004] In a first aspect, an embodiment of the present application provides a power-off control circuit, configured to be connected to at least one power chip to control power-off of the at least one power chip, the power-off control circuit comprising:

[0005] a step-down branch, connected to an input power source, configured to step down the voltage of the input power source and output a first voltage;

[0006] an energy storage branch and a first switch branch, the energy storage branch being connected to the step-down branch and the first switch branch respectively, the energy storage branch being configured to be charged by the first voltage to store electrical energy when the first switch branch is disconnected, and being configured to discharge electrical energy when the first switch branch is turned on;

[0007] The first switch branch is further connected to the input power supply and is configured to be turned on when the difference between the voltage on the energy storage branch and the voltage of the input power supply is greater than a first preset threshold, and is configured to be turned off when the difference between the voltage on the energy storage branch and the voltage of the input power supply is less than or equal to the first preset threshold;

[0008] a second switch branch connected to the first switch branch, configured to be turned on in response to the voltage discharged by the energy storage branch when the first switch branch is turned on to output a low-level signal, and configured to be turned off when the first switch branch is turned off to stop outputting the low-level signal;

[0009] At least one delayed discharge branch, the delayed discharge branch corresponding to the power chip one-to-one, the delayed discharge branch connected between the first switch branch and the enable pin of the power chip, the delayed discharge branch being configured to discharge upon receiving the low-level signal and control the discharge time, and being configured to be charged by the high-level signal on the enable pin of the power chip when the low-level signal is not received.

[0010] In one or more embodiments, the voltage-reducing branch includes a first resistor, a second resistor, and a first diode;

[0011] The first resistor and the second resistor are connected in series between the input power supply and the ground, the connection point between the first resistor and the second resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the energy storage branch and the first switch branch respectively.

[0012] In one or more embodiments, the energy storage branch includes a first capacitor;

[0013] The first capacitor is connected to the voltage-reducing branch and the first switch branch respectively.

[0014] In one or more embodiments, the first switch branch includes a first switch tube and a third resistor;

[0015] The first end of the first switch tube is connected to the input power supply through the third resistor, the second end of the first switch tube is connected to the energy storage branch and the step-down branch respectively, and the third end of the first switch tube is connected to the second switch branch.

[0016] In one or more embodiments, the first switch tube is a PNP transistor;

[0017] The first end of the first switch tube is the base of the PNP transistor, the second end of the first switch tube is the emitter of the PNP transistor, and the third end of the first switch tube is the collector of the PNP transistor.

[0018] In one or more embodiments, the second switch branch includes a second switch tube and a fourth resistor;

[0019] The first end of the second switch tube is connected to the first switch branch through the fourth resistor, the second end of the second switch tube is grounded, and the third end of the second switch tube is connected to the delayed discharge branch.

[0020] In one or more embodiments, the second switch tube is an NPN transistor;

[0021] The first end of the second switch tube is the base of the NPN transistor, the second end of the second switch tube is the emitter of the NPN transistor, and the third end of the second switch tube is the collector of the NPN transistor.

[0022] In one or more embodiments, the delayed discharge branch includes a fifth resistor and a second capacitor;

[0023] The fifth resistor and the second capacitor are connected in series between the second switch branch and the ground, and a connection point between the fifth resistor and the second capacitor is connected to the power chip.

[0024] In a second aspect, an embodiment of the present application provides an electronic device, comprising at least one power chip and the power-off control circuit as described above.

[0025] The present application has the beneficial effect of providing a power-off control circuit connected to at least one power supply chip to control the power-off of the at least one power supply chip. The power-off control circuit includes a step-down branch, an energy storage branch, a first switch branch, a second switch branch, and at least one delayed discharge branch. The step-down branch steps down the voltage of the input power supply and outputs a first voltage. When the input power supply is not disconnected, the difference between the voltage on the energy storage branch and the voltage of the input power supply is less than a first preset threshold, causing the first switch branch to disconnect. The first voltage is maintained to charge the energy storage branch. Simultaneously, the second switch branch also disconnects and stops outputting a low-level signal to the delayed discharge branch. The delayed discharge branch is charged by a high-level signal on the enable pin of the power supply chip. When the input power supply experiences an abnormal power-off, the voltage on the energy storage branch remains constant for a short period of time, while the voltage of the input power supply rapidly decreases. This causes the difference between the voltage on the energy storage branch and the voltage of the input power supply to exceed the first preset threshold, causing the first switch branch to turn on. The voltage on the energy storage branch acts on the second switch branch through the first switch branch, turning it on and outputting a low-level signal to the delayed discharge branch. The delayed discharge branch then discharges, controlling the discharge duration. This pulls the signal on the enable pin of the power chip to a low level, allowing the power chip to power down normally. This process reduces the risk of abnormal power-off of the power chip, thereby reducing the likelihood of damage to components in the electronic device containing the power chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by the figures in the accompanying drawings, which are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0027] Figure 1 is a schematic diagram of a block diagram of a power-off control circuit provided in an embodiment of the present application;

[0028] Figure 2 is with Figure 1 The circuit structure diagram corresponding to the composition block diagram shown;

[0029] Figure 3 It is a schematic diagram of a block diagram of the composition of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0031] It should be noted that, when an element is referred to as being “connected to” another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0032] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as there is no structural conflict between them.

[0033] In the related art, during the normal operation of an electronic device, when the input power of the electronic device is abnormally powered off, the mainboard in the electronic device cannot execute the shutdown sequence normally due to the short voltage drop time. Subsequently, the enable pin of the power chip in the electronic device cannot receive the normal power-off signal, causing the power chip on the mainboard to power off abnormally, that is, the power-off process of the power chip is uncontrolled, and even causes the output voltage of some power chips to abnormally surge and then decrease. The main reason for the abnormal voltage surge when the power chip is abnormally powered off is that in the internal design of some DC power chips, the power supply end powers off faster than the enable end, which causes internal abnormalities in the power chip and the output voltage first surges abnormally and then decreases. When the output voltage surge amplitude is large, the probability of components in the electronic device being damaged is high.

[0034] Based on this, an embodiment of the present application provides a power-off control circuit that can provide a stable power-off signal to the power chip when the input power supply is abnormally powered off, so that the power chip can be powered off normally, thereby avoiding the abnormal situation where the output voltage of the power chip abnormally rises and then decreases, thereby reducing the chance of damage to components in electronic equipment.

[0035] In the embodiments of the present application, a power chip refers to a chip having an enable pin and capable of normal operation when the signal on the enable pin is a high-level signal. When the power chip is in operation, it can convert one form of electrical energy into another form to meet the specific voltage and current requirements of different components within the electronic device. For example, in some embodiments, the power chip is a DC-DC converter chip, which can convert one DC voltage into another DC voltage.

[0036] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the power-off control circuit provided in the embodiment of the present application. Figure 1 As shown, the power-off control circuit 100 is used to connect to at least one power chip to control the power-off of the at least one power chip. The at least one power chip includes a first power chip B1, a second power chip B2, ..., and an Nth power chip BN, where N is an integer greater than or equal to 1.

[0037] The power-off control circuit 100 includes a step-down branch 10, an energy storage branch 20, a first switch branch 30, a second switch branch 40, and at least one delayed discharge branch. Each delayed discharge branch corresponds to a power chip, i.e., the at least one delayed discharge branch includes a first delayed discharge branch A1, a second delayed discharge branch A2, ..., and an Nth delayed discharge branch AN.

[0038] The step-down branch 10 and the first switch branch 30 are both connected to the input power supply V1 N, the energy storage branch 20 is connected to the step-down branch 10 and the first switch branch 30, the second switch branch 40 is connected to the first switch branch 30, and any delayed discharge branch is connected between the first switch branch 30 and the enable pin of the corresponding power chip. Specifically, the first end of the step-down branch 10 and the first end of the first switch branch 30 are both connected to the input power supply V1 N, the second end of the step-down branch 10 is connected to the first end of the energy storage branch 20 and the second end of the first switch branch 30, the third end of the first switch branch 30 is connected to the first end of the second switch branch 40, and the second end of the second switch branch 40 is connected to the first end of the first delayed discharge branch A1, the first end of the second delayed discharge branch A2, ..., and the first end of the Nth delayed discharge branch AN. The second end of the first delayed discharge branch A1 is connected to the first power chip B1, the second end of the second delayed discharge branch A2 is connected to the second power chip B2, ..., the second end of the Nth delayed discharge branch AN is connected to the Nth power chip BN.

[0039] Specifically, the step-down branch 10 is configured to step down the voltage of the input power source V1 N and output a first voltage. The energy storage branch 20 is configured to be charged by the first voltage to store electrical energy when the first switch branch 30 is off, and is further configured to discharge the energy when the first switch branch 30 is on. The first switch branch 30 is configured to turn on when the difference between the voltage on the energy storage branch 20 and the voltage of the input power source V1 N is greater than a first preset threshold, and is further configured to turn off when the difference between the voltage on the energy storage branch 20 and the voltage of the input power source V1 N is less than or equal to the first preset threshold. The first preset threshold can be set based on actual application scenarios and is not specifically limited in this embodiment of the present application. The second switch branch 40 is configured to turn on in response to the voltage discharged by the energy storage branch 20 when the first switch branch 30 is on, thereby outputting a low-level signal, and is configured to turn off when the first switch branch 30 is off, thereby stopping outputting the low-level signal. Any delayed discharge branch is configured to discharge when it receives a low-level signal and control the discharge time, and is configured to be charged by a high-level signal on the enable pin of the corresponding power chip when no low-level signal is received. Specifically, the first delayed discharge branch A1 is configured to discharge when it receives a low-level signal and control the discharge time. The first delayed discharge branch A1 is also configured to be charged by a high-level signal on the enable pin of the first power chip B1 when no low-level signal is received; the second delayed discharge branch A2 is configured to discharge when it receives a low-level signal and control the discharge time. The second delayed discharge branch A2 is also configured to be charged by a high-level signal on the enable pin of the second power chip B2 when no low-level signal is received; ...; the Nth delayed discharge branch AN is configured to discharge when it receives a low-level signal and control the discharge time. The Nth delayed discharge branch AN is also configured to be charged by a high-level signal on the enable pin of the Nth power chip BN when no low-level signal is received.

[0040] In actual applications, when the input power supply V1 N is not powered off (i.e., the input power supply V1 N is supplying power normally), the difference between the voltage on the energy storage branch 20 and the voltage of the input power supply V1 N is less than a first preset threshold, and the first switch branch 30 is disconnected. After the input power supply V1 N is reduced to the first voltage by the step-down branch 10, it continues to charge the energy storage branch 20. At the same time, the second switch branch 40 is disconnected due to the disconnection of the first switch branch 30 and stops outputting low-level signals to each delayed discharge branch (including the first delayed discharge branch A1, the second delayed discharge branch A2, ..., the Nth delayed discharge branch AN). Each delayed discharge branch is charged by a high-level signal on the enable pin of the corresponding power chip. For example, the first delayed discharge branch A1 is charged by a high-level signal on the enable signal of the first power chip B1. It should be noted that in the embodiment of the present application, when the input power supply VIN is supplying power normally, the signal on the enable pin of each power chip (including the first power chip B1, the second power chip B2, ..., the Nth power chip BN) remains a high-level signal by default.

[0041] When the input power supply V1 N experiences an abnormal power outage, the voltage on the energy storage branch 20 remains unchanged for a short period of time, while the voltage of the input power supply V1 N decreases rapidly. As a result, the difference between the voltage on the energy storage branch 20 and the voltage of the input power supply V1 N becomes greater than a first preset threshold, and the first switch branch 30 turns on. The voltage on the energy storage branch 20 acts on the second switch branch 40 through the first switch branch 30, turning on the second switch branch 40 and outputting a low-level signal to each delayed discharge branch. Subsequently, each delayed discharge branch discharges and controls the discharge time (the discharge time of each delayed discharge branch is determined by its characteristics, for example, the discharge time of the first delayed discharge branch A1 is determined by the characteristics of the first delayed discharge branch A1). The signal on the enable pin of each power chip is pulled down to a low-level signal, so that each power chip can be powered off normally.

[0042] As can be seen, through the above process, when the input power supply unexpectedly loses power, the signal on the enable pin of each power chip can be pulled down from a high-level signal to a low-level signal, providing a stable power-off signal for each power chip. As a result, each power chip can be powered off normally, reducing the risk of abnormal power-off of each power chip and thus reducing the probability of damage to components in the electronic device containing each power chip.

[0043] Please refer to Figure 2 , Figure 2 An example is shown with Figure 1 A circuit structure corresponding to the block diagram shown in FIG. Figure 2 As shown, the voltage-reducing branch 10 includes a first resistor R1 , a second resistor R2 , and a first diode D1 .

[0044] The first resistor R1 and the second resistor R2 are connected in series between the input power supply V1 N and the ground GND. The connection point between the first resistor R1 and the second resistor R2 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to the first end of the energy storage branch 20 and the second end of the first switch branch 30, respectively.

[0045] Specifically, the first resistor R1 and the second resistor R2 are used to divide the input power supply VIN. The divided voltage of the input power supply VIN across the second resistor R2 minus the forward voltage drop of the first diode D1 is the first voltage, thereby reducing the voltage of the input power supply VIN to the first voltage. The first diode D1 can also prevent current from flowing back into the input power supply VIN.

[0046] In this embodiment, the energy storage branch 20 includes a first capacitor C1.

[0047] The first capacitor C1 is connected to the second end of the step-down branch 10 and the second end of the first switch branch 30 respectively.

[0048] In this embodiment, the first switch branch 30 includes a first switch Q1 and a third resistor R3 .

[0049] The first end of the first switch tube Q1 is connected to the input power source V1 N via the third resistor R3, the second end of the first switch tube Q1 is connected to the first end of the energy storage branch 20 and the second end of the step-down branch 10 respectively, and the third end of the first switch tube Q1 is connected to the first end of the second switch branch 40.

[0050] In this embodiment, the first switch tube Q1 is a PNP transistor. The first end of the first switch tube Q1 is the base of the PNP transistor, the second end of the first switch tube Q1 is the emitter of the PNP transistor, and the third end of the first switch tube Q1 is the collector of the PNP transistor.

[0051] In addition, the first switch tube Q1 can be any controllable switch, such as an insulated gate bipolar transistor (IGBT) device, an integrated gate-commutated thyristor (IGCT) device, a gate-turn-off thyristor (GTO) device, a silicon-controlled rectifier (SCR) device, a junction-gate field-effect transistor (JFET) device, a MOS-controlled thyristor (MCT) device, etc.

[0052] In this embodiment, the second switch branch 40 includes a second switch transistor Q2 and a fourth resistor R4.

[0053] Among them, the first end of the second switch tube Q2 is connected to the first switch branch 30 through the fourth resistor R4, the second end of the second switch tube Q2 is grounded GND, and the third end of the second switch tube Q2 is respectively connected to the first end of the first delayed discharge branch A1, the first end of the second delayed discharge branch A2, ..., and the first end of the Nth delayed discharge branch AN.

[0054] In this embodiment, the second switch tube Q2 is an NPN transistor. The first end of the second switch tube Q2 is the base of the NPN transistor, the second end of the second switch tube Q2 is the emitter of the NPN transistor, and the third end of the second switch tube Q2 is the collector of the NPN transistor.

[0055] In addition, the first switch tube Q1 can be any controllable switch, such as an insulated gate bipolar transistor (IGBT) device, an integrated gate-commutated thyristor (IGCT) device, a gate-turn-off thyristor (GTO) device, a silicon-controlled rectifier (SCR) device, a junction-gate field-effect transistor (JFET) device, a MOS-controlled thyristor (MCT) device, etc.

[0056] In this embodiment, each delayed discharge branch includes a fifth resistor R5 and a second capacitor C2.

[0057] Among them, the fifth resistor R5 and the second capacitor C2 are connected in series between the second end of the second switch branch 40 and the ground GND, and the connection point between the fifth resistor R5 and the second capacitor C2 is connected to the enable pin of the corresponding power chip. For example, the connection point between the fifth resistor R5 and the second capacitor C2 in the first delayed discharge branch A1 is connected to the enable pin of the first power chip B1.

[0058] The following Figure 2 The principle of the circuit shown is explained.

[0059] When the input power supply VIN is not powered off, the input power supply VIN is divided by the first resistor R1 and the second resistor R2, and is reduced to a first voltage after passing through the forward-conducting first diode D1. The first voltage is used to charge the first capacitor C1. At this time, the base of the first switch tube Q1 is connected to the input power supply VIN through the third resistor R3, and the voltage of the base of the first switch tube Q1 is the voltage of the input power supply VIN; the voltage of the emitter of the first switch tube Q1 is the voltage on the first capacitor C1. When the voltage on the first capacitor C1 is fully charged, that is, when the voltage on the first capacitor C1 is stable, the voltage on the first capacitor C1 is the first voltage. It can be seen that the difference between the voltage on the first capacitor C1 and the voltage of the input power supply VIN is less than zero and less than the first preset threshold value (in this embodiment, the first preset threshold value is the minimum on-state voltage drop of the first switch tube Q1. For example, when the first switch tube Q1 is made of silicon material, the minimum on-state voltage drop V of the first switch tube Q1 is 0. BE ≈0.6V or 0.7V), the first switch Q1 remains off. The second switch Q2 also remains off and stops outputting low-level signals to each delayed discharge branch (including the first delayed discharge branch A1, the second delayed discharge branch A2, ..., the Nth delayed discharge branch AN). Each delayed discharge branch is charged by the high-level signal on the enable pin of the corresponding power chip. For example, the first delayed discharge branch A1 is charged by the high-level signal on the enable pin of the first power chip B1. Each power chip also maintains normal operation.

[0060] When the input power supply V1 N experiences an abnormal power outage, the voltage on the first capacitor C1 remains constant for a short period of time, while the voltage of the input power supply V1 N decreases rapidly until the difference between the voltage on the first capacitor C1 and the voltage of the input power supply V1 N exceeds a first preset threshold, causing the first switch Q1 to turn on. The voltage on the first capacitor C1 acts on the second switch Q2 through the first switch Q1 and the fourth resistor R4, turning on the second switch Q2 and establishing a connection between each delayed discharge branch and ground GND, corresponding to outputting a low-level signal to each delayed discharge branch based on ground GND. Subsequently, each delayed discharge branch discharges, and the discharge time is controlled, wherein the discharge time of each delayed discharge branch is determined by the corresponding fifth resistor R5 and the second capacitor C2. The signal on the enable pin of each power chip is pulled down to a low-level signal, allowing each power chip to power off normally.

[0061] As can be seen, through the above process, when the input power source V1 N abnormally loses power, the signal on the enable pin of each power chip can be pulled down from a high-level signal to a low-level signal, thereby providing a stable power-off signal for each power chip. As a result, each power chip can be powered off normally, reducing the risk of abnormal power-off of each power chip, thereby reducing the probability of damage to components in the electronic device including each power chip.

[0062] Please refer to Figure 3 , Figure 3 Schematic diagram of the composition block diagram of the electronic device provided in the embodiment of the present application. Figure 3 As shown, the electronic device 1000 includes at least one power chip and the power-off control circuit 100 in any embodiment of the present application.

[0063] The at least one power chip includes a first power chip B1, a second power chip B2, ..., and an Nth power chip BN, where N is an integer greater than or equal to 1. The power-off control circuit 100 is connected between the input power supply V1 N and the first power chip B1; the power-off control circuit 100 is connected between the input power supply V1 N and the second power chip B2; ... the power-off control circuit 100 is connected between the input power supply V1 N and the Nth power chip BN.

[0064] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0065] The above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them. Based on the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, and the steps may be implemented in any order. A person skilled in the art should understand that the technical solutions described in the above embodiments may be modified, or some of the technical features may be replaced by equivalents. However, such modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A power-off control circuit, characterized in that: Used to connect to at least one power chip to control the power-off of the at least one power chip, the power-off control circuit includes: a step-down branch, connected to an input power source, configured to step down the voltage of the input power source and output a first voltage; an energy storage branch and a first switch branch, the energy storage branch being connected to the step-down branch and the first switch branch respectively, the energy storage branch being configured to be charged by the first voltage to store electrical energy when the first switch branch is disconnected, and being configured to discharge electrical energy when the first switch branch is turned on; The first switch branch is further connected to the input power supply and is configured to be turned on when the difference between the voltage on the energy storage branch and the voltage of the input power supply is greater than a first preset threshold, and is configured to be turned off when the difference between the voltage on the energy storage branch and the voltage of the input power supply is less than or equal to the first preset threshold; a second switch branch connected to the first switch branch, configured to be turned on in response to the voltage discharged by the energy storage branch when the first switch branch is turned on to output a low-level signal, and configured to be turned off when the first switch branch is turned off to stop outputting the low-level signal; At least one delayed discharge branch, the delayed discharge branch corresponding to the power chip one-to-one, the delayed discharge branch connected between the first switch branch and the enable pin of the power chip, the delayed discharge branch being configured to discharge upon receiving the low-level signal and control the discharge time, and being configured to be charged by the high-level signal on the enable pin of the power chip when the low-level signal is not received.

2. The power-off control circuit according to claim 1, characterized in that: The voltage-step-down branch includes a first resistor, a second resistor and a first diode; The first resistor and the second resistor are connected in series between the input power supply and the ground, the connection point between the first resistor and the second resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the energy storage branch and the first switch branch respectively.

3. The power-off control circuit according to claim 1, characterized in that: The energy storage branch includes a first capacitor; The first capacitor is connected to the voltage-reducing branch and the first switch branch respectively.

4. The power-off control circuit according to claim 1, wherein: The first switch branch includes a first switch tube and a third resistor; The first end of the first switch tube is connected to the input power supply through the third resistor, the second end of the first switch tube is connected to the energy storage branch and the step-down branch respectively, and the third end of the first switch tube is connected to the second switch branch.

5. The power-off control circuit according to claim 4, characterized in that: The first switching tube is a PNP type transistor; The first end of the first switch tube is the base of the PNP transistor, the second end of the first switch tube is the emitter of the PNP transistor, and the third end of the first switch tube is the collector of the PNP transistor.

6. The power-off control circuit according to claim 1, characterized in that: The second switch branch includes a second switch tube and a fourth resistor; The first end of the second switch tube is connected to the first switch branch through the fourth resistor, the second end of the second switch tube is grounded, and the third end of the second switch tube is connected to the delayed discharge branch.

7. The power-off control circuit according to claim 6, characterized in that: The second switching tube is an NPN transistor; The first end of the second switch tube is the base of the NPN transistor, the second end of the second switch tube is the emitter of the NPN transistor, and the third end of the second switch tube is the collector of the NPN transistor.

8. The power-off control circuit according to claim 1, wherein: The delayed discharge branch includes a fifth resistor and a second capacitor; The fifth resistor and the second capacitor are connected in series between the second switch branch and the ground, and a connection point between the fifth resistor and the second capacitor is connected to the power chip.

9. An electronic device, characterized in that: The device comprises at least one power chip and the power-off control circuit according to any one of claims 1 to 8.

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