Low-stray low-jitter frequency synthesizer circuit

Abstract

The utility model discloses a low-stray low-jitter frequency synthesizer which is composed of a phase error averaging circuit, a notch filter circuit and a local oscillator and feedback clock generating circuit. According to the circuit, a notch filter is added behind a loop filter, and notch is carried out at a reference frequency to suppress periodic modulation of the reference frequency on a voltage-controlled oscillator, so that reference spurious is suppressed; meanwhile, the utility model provides a phase error averaging circuit for averaging quantization errors generated by the error summation modulator module in an instantaneous state, and suppressing quantization noise, thereby reducing decimal stray and decimal jitter.

Description

Technical Field

[0001] The utility model relates to a frequency synthesizer circuit, belongs to the technical field of integrated circuits, and specifically refers to a low-spurious and low-jitter frequency synthesizer circuit. Background Art

[0002] With the rapid development of communication systems and the increasing use of integrated circuits, systems-on-chip (SoCs) have become ubiquitous. Clock generation modules play a crucial role in communication systems, determining the bit error rate (BER) of the entire system. Frequency synthesizers, with their high frequency accuracy, wide adjustable range, and narrow frequency step size, have been widely used in communication systems.

[0003] In traditional frequency synthesizer circuits, an external reference clock is generally connected, and the frequency synthesizer is periodically adjusted at this clock frequency. This will cause the voltage-controlled oscillator to be periodically modulated, resulting in reference spurious signals, which in turn cause interference with adjacent channels.

[0004] Fractional frequency division is typically achieved by periodically modulating the frequency divider using an error summing modulator. However, within each reference clock cycle, the frequency divider's division factor remains an integer, not a true fractional number. This leads to phase errors with the reference clock, resulting in significant jitter and fractional spurious output at the frequency synthesizer. Utility Model Content

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings and provide a low-spurious and low-jitter frequency synthesizer circuit, which has the advantages of low integer spurious, fractional spurious, low integer jitter and fractional jitter.

[0006] In view of the existing technology and the above-mentioned shortcomings, the present invention adopts the following design scheme to achieve:

[0007] A low-spurious, low-jitter frequency synthesizer circuit includes a local oscillator and feedback clock generation circuit, a notch filter circuit, and a local oscillator and feedback clock generation circuit. The phase error averaging circuit has an input connected to the output of the local oscillator and feedback clock generation circuit and an output connected to the input of the notch filter circuit. The circuit is used to retain 32 divided phases and compare the 32 divided phases with a reference clock via a frequency and phase detector array to generate corresponding lead and lag signals, control the charging and discharging of a charge pump array, and ultimately average the signals at a loop filter to generate a control signal for a voltage-controlled oscillator. The notch filter circuit has an input connected to the output of the phase error averaging circuit and an output connected to the input of the local oscillator and feedback clock generation circuit. The circuit is used to suppress periodic modulation of the voltage-controlled oscillator by the reference clock, thereby suppressing reference spurious signals. The local oscillator and feedback clock generation circuit has an input connected to the output of the notch filter circuit and an output connected to the input of the local oscillator and feedback clock generation circuit. The circuit is used to generate an oscillation signal and implement the fractional frequency division function of the overall circuit.

[0008] Furthermore, the phase error averaging circuit includes a fixed delay unit DF, a coarse adjustment delay unit DL1, a DL2 unit, a two-to-one selector MUX1, fine adjustment delay units D1, D2, D3, D4, D5, D6, D7, D8, an eight-to-one selector MUX2, and a reference clock delay unit Dref composed thereof, 32 reference clock delay units forming a 32-bit matrix cyclic right shift circuit, a frequency detector array, a charge pump array, and a loop filter; the input of the fixed delay unit DF is connected to the output of the frequency divider, and the output end of DF is connected to the input end of the coarse adjustment delay unit DL1; the output end of DL1 is connected to the 1 input end of the two-to-one selector MUX1, and is connected to the output end of the coarse adjustment delay unit DL2. The output of DL2 is connected to the input of the selector MUX1; the output of MUX1 is connected to the fine-tuning delay unit D1; the output of the fine-tuning delay unit D1 is connected to the input of the fine-tuning delay unit D2, and is also connected to the input 1 of the eight-choose-one selector MUX2; the output of the fine-tuning delay unit D2 is connected to the input of the fine-tuning delay unit D3, and is also connected to the input 2 of the eight-choose-one selector MUX2; the output of the fine-tuning delay unit D3 is connected to the input of the fine-tuning delay unit D4, and is also connected to the input 3 of the eight-choose-one selector MUX2; the output of the fine-tuning delay unit D4 is connected to the input of the fine-tuning delay unit D5, and is also connected to the input 4 of the eight-choose-one selector MUX2 ; The output end of the fine-tuning delay unit D5 is connected to the input end of the fine-tuning delay unit D6, and is also connected to the 5 input end of the eight-choose-one selector MUX2; the output end of the fine-tuning delay unit D6 is connected to the input end of the fine-tuning delay unit D7, and is also connected to the 6 input end of the eight-choose-one selector MUX2; the output end of the fine-tuning delay unit D7 is connected to the input end of the fine-tuning delay unit D8, and is also connected to the 7 input end of the eight-choose-one selector MUX2; the output end of the fine-tuning delay unit D8 is connected to the 8 input end of the eight-choose-one selector MUX2; fixed delay unit DF, coarse delay unit, fine delay unit DL1, DL2 unit, two-choose-one selector MUX1, fine delay unit D1, D2, D3, D4, D5, D6, D7, D8, and the eight-to-one selector MUX2 form a reference clock delay unit Dref; 32 Dref inputs and outputs are connected, and the connection point serves as an output port. The entire circuit is a 32-bit matrix cyclic right shift circuit with a total of 32 output ports. The output terminals Fdiv<31:0> of the 32-bit matrix cyclic right shift circuit are respectively connected to the DIV terminals of the frequency detector array; the Fref terminal of the frequency detector array is connected to the external reference clock, the output terminal UP is connected to the upper input terminal of the charge pump array, and the output terminal DN is connected to the lower input terminal of the charge pump array; the output terminals of the charge pump array are short-circuited together and connected to the input terminal of the loop filter; the output terminal of the loop filter is connected to the input terminal of the notch filter.

[0009] Furthermore, the notch filter circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, and a third capacitor C3; one end of the first resistor R1 is connected to the output end of the loop filter, and the other end is interconnected with the first resistor R2 and the third capacitor C3; one end of the second resistor R2 is connected to one end of the first resistor R1, interconnected with the third capacitor C3, and the other end is connected to the second capacitor C2, and interconnected with the input end of the voltage-controlled oscillator; one end of the third resistor R3 is connected to one end of the first capacitor C1, interconnected with the second capacitor C2, and the other end is connected to the ground terminal GND; one end of the first capacitor C1 is connected to the output end of the loop filter, and the other end is connected to the second capacitor C2, and interconnected with the third resistor R3; one end of the second capacitor C2 is connected to the first capacitor C1, interconnected with the third resistor R3, and the other end is connected to the second resistor R2, and interconnected with the input end of the voltage-controlled oscillator; one end of the third capacitor C3 is connected to the first resistor R1, interconnected with the second resistor R2, and the other end is connected to the third resistor R3, and interconnected with the ground terminal GND.

[0010] Furthermore, the local oscillator and feedback clock generating circuit includes a voltage-controlled oscillator, a high-speed buffer, a PS frequency divider, an error sum modulator module, and a divide-by-seven remainder circuit; the input end of the voltage-controlled oscillator is connected to the second resistor R2 of the notch filter and is interconnected with the second capacitor C2 of the notch filter, and the output end is connected to the input end of the high-speed buffer and is interconnected with the input end of the PS frequency divider; the input end of the high-speed buffer is connected to the output end of the voltage-controlled oscillator and is interconnected with the input end of the PS frequency divider, and the output end serves as the output of the frequency synthesizer; the input end of the PS frequency divider The input end is connected to the input end of the high-speed buffer, connected to the output end of the voltage-controlled oscillator, interconnected with the output end of the division-by-seven remainder circuit, and the output end is connected to the input end of the 32-bit matrix cyclic circuit; the first input end of the error sum modulator module is the 7-bit integer control word Integer<6:0>, the second input end is the 4-bit integer control word Fraction<3:0>, and the output end is connected to the output end of the division-by-seven remainder circuit; the input of the division-by-seven remainder circuit is connected to the output end of the error sum modulator module, and the output end is connected to the lower input end of the PS divider.

[0011] The present invention has the following advantages: first, the present invention adopts a notch filter at the reference clock to suppress the periodic modulation of the reference clock on the voltage-controlled oscillator, which can significantly improve the reference spurious performance of the frequency synthesizer; second, the present invention proposes a phase error averaging circuit for averaging the phase error between the feedback clock and the reference clock, which can significantly reduce the fractional jitter and fractional spurious of the frequency synthesizer; third, the present invention proposes a digitally controlled adjustable delay unit for adjusting the delay fluctuation caused by temperature process changes to accurately delay a reference clock cycle, which can significantly improve the accuracy of the delay unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The utility model is a circuit structure diagram of a low-spurious and low-jitter frequency synthesizer circuit.

[0013] Figure 2 This is a diagram of integer jitter simulation results of the low-spurious and low-jitter frequency synthesizer circuit of the utility model.

[0014] Figure 3 This is a diagram of integer spurious simulation results of the low-spurious and low-jitter frequency synthesizer circuit of the utility model.

[0015] Figure 4 This is a diagram of fractional jitter simulation results of the low-spurious and low-jitter frequency synthesizer circuit of the utility model.

[0016] Figure 5 This is a diagram of the fractional spurious simulation results of the low-spurious and low-jitter frequency synthesizer circuit of the utility model. DETAILED DESCRIPTION

[0017] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in and described with reference to the accompanying drawings are merely exemplary and are not intended to limit the present invention to these embodiments.

[0018] In addition, it should be noted that in order to avoid obscuring the present invention due to unnecessary details, only the structures and / or processing steps closely related to the scheme according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0019] Furthermore, in the description of this utility model, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this utility model. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] See also Figures 1 to 5 , the embodiments of the present utility model include:

[0021] like Figure 1 As shown, an embodiment of the present invention includes: a low-spurious and low-jitter frequency synthesizer provided by the present invention includes a phase error averaging circuit, a notch filter circuit, a local oscillator and feedback clock generation circuit, and their functions and implementation methods are described below.

[0022] The phase error averaging circuit is used to average the phase error between the frequency-divided signal and the reference signal to reduce digital jitter and fractional spurious signals and provide a control voltage for the voltage-controlled oscillator; the notch filter circuit is used to suppress the energy at the reference clock frequency, thereby reducing the periodic modulation of the voltage-controlled oscillator by the reference clock and thus reducing the reference spurious signals; the local oscillator and feedback clock generation are used to generate an oscillation signal and realize the fractional frequency division function of the overall circuit.

[0023] Continue reading Figure 1As shown, in an embodiment of the present invention, the phase error averaging circuit includes a fixed delay unit DF, a coarse delay unit, a fine delay unit DL1, a DL2 unit, a two-to-one selector MUX1, fine delay units D1, D2, D3, D4, D5, D6, D7, D8, an eight-to-one selector MUX2, and a reference clock delay unit Dref composed thereof, 32 reference clock delay units forming a 32-bit matrix cyclic right shift circuit, a frequency detector array, a charge pump array, and a loop filter; the input of the fixed delay unit DF is connected to the output of the frequency divider, the output end of DF is connected to the input end of the coarse delay unit DL1; the output end of DL1 is connected to the 1 input end of the two-to-one selector MUX1, And connected to the input end of the coarse adjustment delay unit DL2; the output end of DL2 is connected to the 2 input end of the selector MUX1; the control end of the selector MUX1 is controlled by the outside world, and the output end of MUX1 is connected to the fine adjustment delay unit D1; the output end of the fine adjustment delay unit D1 is connected to the input end of the fine adjustment delay unit D2, and is also connected to the 1 input end of the eight-choose-one selector MUX2; the output end of the fine adjustment delay unit D2 is connected to the input end of the fine adjustment delay unit D3, and is also connected to the 2 input end of the eight-choose-one selector MUX2; the output end of the fine adjustment delay unit D3 is connected to the input end of the fine adjustment delay unit D4, and is also connected to the 3 input end of the eight-choose-one selector MUX2; the output end of the fine adjustment delay unit D4 is connected to the fine adjustment delay unit D 5 is connected to the input end of the 8-selector MUX2, and is also connected to the 4 input end of the 8-selector MUX2; the output end of the fine-tuning delay unit D5 is connected to the input end of the fine-tuning delay unit D6, and is also connected to the 5 input end of the 8-selector MUX2; the output end of the fine-tuning delay unit D6 is connected to the input end of the fine-tuning delay unit D7, and is also connected to the 6 input end of the 8-selector MUX2; the output end of the fine-tuning delay unit D7 is connected to the input end of the fine-tuning delay unit D8, and is also connected to the 7 input end of the 8-selector MUX2; the output end of the fine-tuning delay unit D8 is connected to the 8 input end of the 8-selector MUX2; the fixed delay unit DF, the coarse delay unit, the fine delay unit DL1, DL2 unit, the two-selector MUX1, fine-tuning delay units D1, D2, D3, D4, D5, D6, D7, D8, and eight-to-one selector MUX2 form a reference clock delay unit Dref; 32 Dref inputs and outputs are connected, and the connection point serves as an output port. The entire circuit is a 32-bit matrix cyclic right shift circuit with a total of 32 output ports (Fdiv<31:0>). The output terminals Fdiv<31:0> of the 32-bit matrix cyclic right shift circuit are respectively connected to the DIV terminals of the phase frequency detector array; the Fref terminal of the phase frequency detector array (PFD) is connected to the external reference clock, the output terminal UP is connected to the upper input terminal of the charge pump array (CP), and the output terminal DN is connected to the lower input terminal of the charge pump array (CP);The output terminals of the charge pump array (CP) are short-circuited together and connected to the input terminal of the loop filter (LPF); the output terminal of the loop filter (LPF) is connected to the input terminal of the notch filter (Notch Filter).

[0024] The notch filter circuit of the present invention includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, and a third capacitor C3; one end of the first resistor R1 is connected to the output end of the loop filter, and the other end is interconnected with the first resistor R2 and the third capacitor C3; one end of the second resistor R2 is connected to one end of the first resistor R1 and the third capacitor C3, and the other end is connected to the second capacitor C2 and the input end of the voltage-controlled oscillator (VCO); one end of the third resistor R3 is connected to one end of the first capacitor C1, The first capacitor C1 is connected to the output terminal of the loop filter (LPF), and the other end is connected to the second capacitor C2, and the third resistor R3 is connected to the first capacitor C1; the second capacitor C2 is connected to the first capacitor C1, and the third resistor R3 is connected to the second resistor R2, and the input terminal of the voltage-controlled oscillator (VCO); the third capacitor C3 is connected to the first resistor R1, and the second resistor R2 is connected to the other end, and the third resistor R3 is connected to the ground GND.

[0025] The utility model discloses a local oscillator and feedback clock generating circuit comprising a voltage controlled oscillator (VCO), a high-speed buffer (Buffer), a PS divider (PSdivider), an error sum modulator module (DSM), and a division by seven remainder circuit; the input end of the voltage controlled oscillator (VCO) is connected to a second resistor R2 of a notch filter (Notch Filter) and is interconnected with a second capacitor C2 of the notch filter (Notch Filter); the output end is connected to an input end of a high-speed buffer (Buffer) and is interconnected with an input end of the PS divider (PSdivider); the input end of the high-speed buffer (Buffer) is connected to an output end of the voltage controlled oscillator (VCO) and is interconnected with an input end of the PS divider (PSdivider); the output end serves as an output of a frequency synthesizer; the input end of the PS divider (PSdivider) is connected to the high-speed buffer (Buffer) The input end of the error sum modulator module (DSM) is connected to the output end of the voltage controlled oscillator (VCO), and is interconnected with the output end of the division by seven remainder circuit, and the output end is connected to the input end of the 32-bit matrix cyclic circuit; the first input end of the error sum modulator module (DSM) is the 7-bit integer control word Integer<6:0>, the second input end is the 4-bit integer control word Fraction<3:0>, and the output end is connected to the output end of the division by seven remainder circuit; the input of the division by seven remainder circuit is connected to the output end of the error sum modulator module (DSM), and the output end is connected to the lower input end of the PS divider (PSdivider).

[0026] Below Figure 1 The specific working principle and performance of the low spurious and low jitter frequency synthesizer shown are introduced in detail.

[0027] The present invention's phase error averaging circuit is used to average the phase difference from the reference frequency generated by the frequency divider caused by quantization error in a DSM (error summing modulator module). The phase error averaging circuit comprises a fixed delay unit DF, coarse delay units DL1 and DL2, a two-to-one selector MUX1, fine delay units D1, D2, D3, D4, D5, D6, D7, and D8, an eight-to-one selector MUX2, and a reference clock delay unit Dref composed of these units. Thirty-two reference clock delay units form a 32-bit matrix cyclic right shift circuit, a frequency and phase detector array, a charge pump array, and a loop filter. The fixed delay unit DF provides a fixed delay. The coarse and fine delay units DL1 and DL2 offer a wide delay adjustment range. The two-to-one selector MUX1 selects whether to output at the coarse delay unit DL1 or the coarse delay unit DL2. Fine-delay units D1, D2, D3, D4, D5, D6, D7, and D8 provide a narrow delay adjustment range. An eight-to-one selector (MUX2) selects the outputs of fine-delay units D1 through D8. The reference clock delay unit Dref, which is composed of the fixed delay unit DF, coarse delay units DL1 and DL2, the two-to-one selector (MUX1), fine-delay units D1, D2, D3, D4, D5, D6, D7, and D8, and the eight-to-one selector (MUX2), provides a reference clock delay and outputs it to each sub-phase frequency detector (PFD). The 32 reference clock delay units form a 32-bit matrix cyclic right shift circuit, delaying the waveform generated by the PS divider by 32 reference clock cycles. The phase frequency detector (PFD) array compares the phase difference between the signal at the 32-bit output port (Fdiv<31:0>) of the 32-bit matrix cyclic right shift circuit and the reference clock signal (Fref). If the reference signal (Fref) leads the 32-bit matrix cyclic right shift circuit signal, the UP signal in the PFD array is 1 and the DN signal is 0. If the reference signal leads the 32-bit matrix cyclic right shift circuit signal, the UP signal in the PFD array is 0 and the DN signal is 1. The charge pump (CP) array charges and discharges the loop filter (LPF). If the input UP signal is 1 and the DN signal is 0, the charge pump (CP) array charges the loop filter (LPF). If the input UP signal is 0 and the DN signal is 1, the charge pump (CP) array discharges the loop filter (LPF). The loop filter (LPF) adjusts the loop parameters of the entire frequency synthesizer to ensure loop stability.

[0028] The notch filter of this utility model is used to suppress the periodic modulation of a voltage-controlled oscillator (VCO) by a reference frequency, thereby reducing reference spurious signals. The notch filter is composed of resistors R1-R3 and capacitors C1-C3. Resistors R1, R2, and C1 form a low-pass filter, while resistors R1, C1, and C2 form a high-pass filter. The low-pass and high-pass filters are combined to form a notch filter. The notch filter's notch frequency is the reference frequency, thereby suppressing the periodic modulation of the voltage-controlled oscillator (VCO) by the reference frequency.

[0029] The utility model discloses a local oscillator and feedback clock generation circuit for generating local oscillator signals and frequency-divided signals. The circuit comprises a voltage-controlled oscillator (VCO), a high-speed buffer (Buffer), a PS divider (PS divider), an error sum modulator module (DSM), and a divide-by-seven remainder circuit. The voltage-controlled oscillator (VCO) generates a local oscillator signal under a VTUNE control signal. The high-speed buffer (Buffer) serves as an output buffer to prevent external load capacitance from affecting the voltage-controlled oscillator (VCO). The PS divider (PS divider) divides the local oscillator signal. The error sum modulator module (DSM) generates a dynamic frequency-dividing coefficient. The average value of the dynamic frequency-dividing coefficient is a set Integer<6:0> + Fraction<3:0>, where Integer<6:0> serves as the integer portion of the frequency-dividing coefficient and Fraction<3:0> serves as the decimal portion of the frequency-dividing coefficient. The divide-by-seven remainder circuit converts the dynamic frequency-dividing coefficient generated by the error sum modulator module (DSM) into a control signal for the PS divider (PS divider).

[0030] Figure 2 This is the integer jitter simulation result of a low-spurious and low-jitter frequency synthesizer circuit of the utility model. As can be seen from the figure, in integer mode, the fractional root mean square jitter (RMS Jitter) of the frequency synthesizer is 130fs.

[0031] Figure 3 This is a graph showing the reference spurious signal simulation results for a low-spurious, low-jitter frequency synthesizer circuit according to the utility model. As can be seen from the graph, when the frequency synthesizer operates at 1.571 GHz, the difference in frequency energy between the reference frequency (16.368 MHz) and the center oscillation frequency is 83.9 dB, meaning the reference spurious signal is -83.9 dBc.

[0032] Figure 3This is the fractional jitter simulation result of a low-spurious and low-jitter frequency synthesizer circuit of the utility model. As can be seen from the figure, in fractional mode, the fractional root mean square jitter (RMS Jitter) of the frequency synthesizer is 537.59fs.

[0033] Figure 4 This figure shows the integer spurious simulation results for a low-spurious, low-jitter frequency synthesizer circuit according to the utility model. As can be seen from the figure, when the frequency synthesizer operates at 1.572346 GHz, the difference in frequency energy between the fractional frequency (1.0000061 MHz) and the center oscillation frequency is approximately 65.29 dB, meaning the fractional spurious is -65.29 dBc.

[0034] In addition, it should be noted that, in this specification, "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus comprising a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or apparatus comprising the element.

[0035] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A low spurious and low jitter frequency synthesizer circuit, characterized in that: The invention comprises a phase error averaging circuit, a notch filter circuit, and a local oscillator and feedback clock generation circuit. The phase error averaging circuit has an input connected to the output of the local oscillator and feedback clock generation circuit, and an output connected to the input of the notch filter circuit. The phase error averaging circuit is used to retain 32 divided phases and compare the 32 divided phases with a reference clock through a frequency and phase detector array to generate corresponding lead and lag signals, control the charging and discharging of a charge pump array, and finally average the signals at a loop filter to generate a control signal for a voltage-controlled oscillator. The notch filter circuit has an input connected to the output of the phase error averaging circuit and an output connected to the input of the local oscillator and feedback clock generation circuit. The notch filter circuit is used to suppress periodic modulation of the voltage-controlled oscillator by the reference clock, thereby suppressing reference spurious signals. The local oscillator and feedback clock generation circuit has an input connected to the output of the notch filter circuit and an output connected to the input of the local oscillator and feedback clock generation circuit. The notch filter circuit is used to generate an oscillation signal and realize the fractional frequency division function of the overall circuit.

2. The low-spurious and low-jitter frequency synthesizer circuit according to claim 1, wherein: The phase error averaging circuit includes a fixed delay unit DF, a coarse delay unit DL1, a DL2 unit, a two-to-one selector MUX1, fine delay units D1, D2, D3, D4, D5, D6, D7, D8, an eight-to-one selector MUX2, and a reference clock delay unit Dref composed of the same. 32 reference clock delay units Dref form a 32-bit matrix cyclic right shift circuit, a frequency detector array, a charge pump array, and a loop filter. The input of the fixed delay unit DF is connected to the output of the frequency divider, and the output end of DF is connected to the input end of the coarse delay unit DL1. The output end of DL1 is connected to the input end 1 of the two-to-one selector MUX1 and to the input end of the coarse delay unit DL2. The output end of L2 is connected to the 2-input end of the selector MUX1; the control end of the selector MUX1 is controlled by the outside world, and the output end of MUX1 is connected to the fine-tuning delay unit D1; the output end of the fine-tuning delay unit D1 is connected to the input end of the fine-tuning delay unit D2, and is also connected to the 1-input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D2 is connected to the input end of the fine-tuning delay unit D3, and is also connected to the 2-input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D3 is connected to the input end of the fine-tuning delay unit D4, and is also connected to the 3-input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D4 is connected to the input end of the fine-tuning delay unit D5, and is also connected to the 4 input terminals; the output terminal of the fine-tuning delay unit D5 is connected to the input terminal of the fine-tuning delay unit D6, and is also connected to the 5 input terminal of the eight-choose-one selector MUX2; the output terminal of the fine-tuning delay unit D6 is connected to the input terminal of the fine-tuning delay unit D7, and is also connected to the 6 input terminal of the eight-choose-one selector MUX2; the output terminal of the fine-tuning delay unit D7 is connected to the input terminal of the fine-tuning delay unit D8, and is also connected to the 7 input terminal of the eight-choose-one selector MUX2; the output terminal of the fine-tuning delay unit D8 is connected to the 8 input terminal of the eight-choose-one selector MUX2; the fixed delay unit DF, the coarse delay unit, the fine delay unit DL1, DL2 units, the two-choose-one selector MUX1, the fine delay units D1, D2, D3, D4, D 5, D6, D7, D8, and the eight-to-one selector MUX2 form a reference clock delay unit Dref; the 32 Dref inputs and outputs are connected end to end, and the connection point serves as an output port. The entire circuit is a 32-bit matrix cyclic right shift circuit with a total of 32 output ports. The output terminals Fdiv<31:0> of the 32-bit matrix cyclic right shift circuit are respectively connected to the DIV terminals of the frequency detector array; the Fref terminal of the frequency detector array is connected to the external reference clock, the output terminal UP is connected to the upper input terminal of the charge pump array, and the output terminal DN is connected to the lower input terminal of the charge pump array; the output terminals of the charge pump array are short-circuited together and connected to the input terminal of the loop filter; the output terminal of the loop filter is connected to the input terminal of the notch filter.

3. The low-spurious and low-jitter frequency synthesizer circuit according to claim 1, wherein: The notch filter circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, and a third capacitor C3; one end of the first resistor R1 is connected to the output end of the loop filter, and the other end is interconnected with the first resistor R2 and the third capacitor C3; one end of the second resistor R2 is connected to one end of the first resistor R1, interconnected with the third capacitor C3, and the other end is connected to the second capacitor C2 and the input end of the voltage-controlled oscillator; one end of the third resistor R3 is connected to one end of the first capacitor C1, interconnected with the second capacitor C2, and the other end is connected to the ground terminal GND; one end of the first capacitor C1 is connected to the output end of the loop filter, and the other end is connected to the second capacitor C2 and the third resistor R3; one end of the second capacitor C2 is connected to the first capacitor C1, interconnected with the third resistor R3, and the other end is connected to the second resistor R2 and the input end of the voltage-controlled oscillator; one end of the third capacitor C3 is connected to the first resistor R1, interconnected with the second resistor R2, and the other end is connected to the third resistor R3 and the ground terminal GND.

4. The low-spurious and low-jitter frequency synthesizer circuit according to claim 1, wherein: The local oscillator and feedback clock generation circuit includes a voltage-controlled oscillator, a high-speed buffer, a PS frequency divider, an error summing modulator module, and a divide-by-seven remainder circuit; the input end of the voltage-controlled oscillator is connected to the second resistor R2 of the notch filter and is interconnected with the second capacitor C2 of the notch filter, and the output end is connected to the input end of the high-speed buffer and is interconnected with the input end of the PS frequency divider; the input end of the high-speed buffer is connected to the output end of the voltage-controlled oscillator and is interconnected with the input end of the PS frequency divider, and the output end serves as the output of the frequency synthesizer; the input end of the PS frequency divider is connected to the input end of the high-speed buffer, to the output end of the voltage-controlled oscillator, and is interconnected with the output end of the divide-by-seven remainder circuit, and the output end is connected to the input end of the 32-bit matrix cyclic circuit; the first input end of the error summing modulator module is a 7-bit integer control word Integer<6:0>, the second input end is a 4-bit integer control word Fraction<3:0>, and the output end is connected to the output end of the divide-by-seven remainder circuit; the input of the divide-by-seven remainder circuit is connected to the output end of the error summing modulator module, and the output end is connected to the lower input end of the PS frequency divider.

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