Silicon carbide diode

Abstract

The silicon carbide diode comprises a substrate, and a buffer layer, an n-type drift region, a contact metal layer and an outer side metal layer are sequentially arranged on the substrate in the vertical direction. Wherein a plurality of p-type doped regions are embedded in the drift region of the n-type drift region at intervals. The contact metal layer is in contact with the n-type drift region and the p-type doped region, and the width of the contact region of the p-type doped region and the contact metal layer is gradually increased from the edge to the center. According to the utility model, the non-uniform distribution rule that the width of the contact region of the p-type doped region is gradually increased from the edge to the center of the region is utilized, so that the higher junction temperature of the central region of the device is reduced, the temperature distribution of the device is more uniform, and the reliability of the SiC diode is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of microelectronics, in particular to a silicon carbide diode. Background Art

[0002] The performance of traditional silicon-based semiconductor devices has gradually approached the physical limits of the material, while devices made of third-generation semiconductor materials represented by silicon carbide have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance.

[0003] As a representative of SiC devices, SiC MOSFET has many excellent characteristics such as low conduction loss, fast switching speed, and high operating frequency. It has gradually been promoted and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible direct current transmission. Since silicon carbide devices need to challenge some extreme environments in different working scenarios, such as being used in high temperature and high pulse current environments, the reliability of silicon carbide devices also needs to be improved.

[0004] A common approach to improving reliability is to enhance the surge current capability of Schottky diodes. Ordinary Schottky diodes are arranged in an alternating PN array. In the forward direction, the n-region Schottky lowers the turn-on voltage and forward voltage drop, thereby reducing the on-resistance at elevated temperatures. Furthermore, a PN junction is formed in the p-region, utilizing the reverse blocking characteristics of the PN junction to reduce reverse leakage current and increase the breakdown voltage. However, because the p-region of an ordinary Schottky diode does not form an ohmic contact in the forward direction, the potential barrier is high, and the PN junction does not conduct in the forward state. Therefore, the high surge current capability of ordinary Schottky diodes cannot be demonstrated. Furthermore, when SiC diode chips are operating, temperature gradients will occur between different regions of the chip due to varying heat dissipation efficiencies. The central region of the chip often exhibits a higher junction temperature, which can lead to the risk of high-temperature failure even when the junction temperature in some regions does not reach the limit, adversely affecting the reliability of the SiC diode chip.

[0005] In summary, the design needs to be optimized to utilize the pn junction to enhance surge current capability, improve temperature distribution, and reduce heat accumulation to enhance overall reliability. Utility Model Content

[0006] The utility model provides a silicon carbide diode with an improved structure to solve the above problems.

[0007] The present invention adopts the following technical solutions to solve the above technical problems:

[0008] The utility model provides a silicon carbide diode, which includes a substrate;

[0009] A buffer layer, an n-type drift region, a contact metal layer, and an outer metal layer are sequentially provided on the substrate in a vertical direction;

[0010] The n-type drift region is provided on the upper surface of the buffer layer; a plurality of p-type doped regions are embedded in the drift region of the n-type drift region;

[0011] The contact metal layer is provided on the upper surface of the n-type drift region; the contact metal layer contacts the n-type drift region and the p-type doped region respectively; the width of the contact region between the p-type doped region and the contact metal layer increases sequentially from the outer edge to the center of the n-type drift region;

[0012] The outer metal layer is provided on the upper surface of the contact metal layer.

[0013] Optionally, the p-type doping region includes a p-type low-doping region and a p-type high-doping region;

[0014] The p-type highly doped region forms an ohmic contact region with the contact metal layer;

[0015] The adjacent p-type doped region and the contact metal layer form a Schottky contact region.

[0016] Optionally, the doping width of the p-type low-doping region ranges from 0.1 μm to 10 μm;

[0017] The depth of the p-type low-doping region ranges from 0.5 μm to 10 μm;

[0018] The doping concentration of the p-type low-doping region is in the range of 1×10 15 cm -3 -1×10 19 cm -3 .

[0019] Optionally, the doping width of the p-type highly doped region is in a range of 0.1 μm to 10 μm;

[0020] The depth of the p-type high-doping region ranges from 0.5 μm to 10 μm;

[0021] The doping concentration of the p-type high-doping region is in the range of 1×10 19 cm -3 -1×10 20 cm -3 .

[0022] Optionally, a width of a contact region between the p-type doped region at the outer edge of the n-type drift region and the contact metal layer is in a range of 0.1 μm to 3 μm;

[0023] The width of the contact region between the p-type doping region at the center of the n-type drift region and the contact metal layer is in the range of 1 μm to 10 μm.

[0024] Optionally, the width of the contact region between the p-type doping region and the contact metal layer increases in a gradient range of 1 μm to 10 μm per micron.

[0025] Optionally, a distance between an upper surface of the p-type doping region and an upper surface of the n-type drift region is in a range of 0-100 μm.

[0026] Optionally, the surface profile of the p-type doping region is at least one of a stripe shape, an alternate stripe shape, a regular quadrilateral, and a regular hexagon;

[0027] The width of the contact region between the p-type doping region and the contact metal layer is the maximum width of the surface profile of the p-type doping region.

[0028] Optionally, the contact metal layer is a titanium metal layer or a nickel metal layer, or a titanium-nickel alloy layer.

[0029] Optionally, a back metal layer is further provided on the lower surface of the substrate.

[0030] Compared with the prior art, the above technical solution adopted by the present invention has the following technical effects:

[0031] The utility model utilizes the non-uniform distribution law that the width of the contact area of ​​the p-type doped region increases from the edge to the center of the region, thereby reducing the higher junction temperature in the central area of ​​the device, making the temperature distribution of the device more uniform, and improving the reliability of the silicon carbide diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a schematic structural diagram of a silicon carbide diode in a specific embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of a mask in a specific embodiment of the present invention;

[0035] Figure 3 This is a flow chart of a method for manufacturing a silicon carbide diode in a specific embodiment of the present invention.

[0036] In the figure, 1. substrate, 2. buffer layer, 3. n-type drift region, 4. p-type low-doped region, 5. p-type high-doped region, 6. contact metal layer, 7. outer metal layer. DETAILED DESCRIPTION

[0037] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0039] In the description of the present invention, it is necessary to understand that the relative relationships indicated by the terms "upper" and "lower" are based on the order of contact with the material in the direction of rotation in actual applications. They are for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the equipment or components referred to must have a specific position. Therefore, they cannot be understood as limitations on the present invention.

[0040] In the description of the present invention, “plurality” means two or more, unless otherwise clearly defined.

[0041] It should be noted that the methods used in the present invention are all conventional methods unless otherwise specified; the raw materials and devices used are all conventional commercially available products unless otherwise specified.

[0042] This embodiment provides a silicon carbide diode, such as Figure 1 As shown, it includes a substrate 1. The substrate 1 is a 4H-SiC substrate, on which a buffer layer 2, an n-type drift region 3, a contact metal layer 6 and an outer metal layer 7 are sequentially arranged along a vertical direction.

[0043] An n-type drift region 3 is provided on the upper surface of the buffer layer 2. Multiple p-type doped regions are interspersed in the upper drift region of the n-type drift region 3. A contact metal layer 6 is provided on the upper surface of the n-type drift region 3. The contact metal layer 6 can be made of a variety of materials, including titanium, nickel, or a titanium-nickel alloy. The lower surface of the contact metal layer 6 contacts the n-type drift region and the p-type doped region. The p-type doped region includes a low-p-type doped region 4 and a high-p-type doped region 5. The high-p-type doped region 5 forms a quasi-ohmic contact with the contact region of the upper contact metal layer 6. A quasi-ohmic contact refers to a region exhibiting characteristics similar to an ohmic contact. Ohmic contact is an ideal contact state characterized by very low resistance at the contact interface and a linear relationship between current and voltage. While quasi-ohmic contact regions cannot fully achieve the ideal ohmic contact state, they exhibit lower contact resistance and a more linear current-voltage characteristic. Schottky contacts are formed between adjacent p-type doped regions and the contact metal layer 6. This embodiment increases the implantation concentration of the doped region to form a quasi-ohmic contact between the p-type region and the contact metal, thereby turning on the PN junction in the Schottky diode when the forward voltage is large, thereby exhibiting a high surge current resistance characteristic.

[0044] Furthermore, the doping width of the p-type low-doping region 4 is in the range of 0.1 μm-10 μm, and the depth of the p-type low-doping region 4 is in the range of 0.5 μm-10 μm; the doping concentration of the p-type low-doping region 4 is in the range of 1×10 15 cm -3 -1×10 19 cm -3 .

[0045] Furthermore, the doping width of the p-type high-doping region 5 is in the range of 0.1 μm-10 μm, and the depth of the p-type high-doping region is in the range of 0.5 μm-10 μm; the doping concentration of the p-type high-doping region is in the range of 1×10 19 cm -3 -1×10 20 cm -3 .

[0046] The surface profile of each p-type doped region is a combination of one or more of the following shapes: strips, spaced strips, regular quadrilaterals, and regular hexagons. In this embodiment, a regular quadrilateral is used as an example for illustration, and the width of the contact area between the p-type doped region and the contact metal layer 6 is the maximum width of the surface profile of the p-type doped region. Therefore, in this embodiment, its width is the side length of the p-type doped region; this should not be understood as the diagonal length. Although the diagonal is the maximum point, the width should be understood as a direction parallel to at least one side length.

[0047] The width of the contact area between the multiple p-type doping regions on the n-type drift region 3 and the contact metal layer 6 increases in sequence from the edge of the n-type drift region 3 to the center of the n-type drift region 3. Figure 2 As shown in the mask, the side length of the regular quadrilateral contact area at the edge is relatively small, and the side length gradually increases as it approaches the center area; specifically, the contact area width between the p-type doped region and the contact metal layer 6 increases in a gradient range of 1μm-10μm per micron; for example: if the distance (gradient direction distance) between the center of the second circle of regular quadrilateral contact areas on the center side and the center of the regular quadrilateral contact areas of the adjacent outer circle (third circle) is n microns, then the side length of the second circle of regular quadrilateral contact areas is n-10n longer than the side length of the third circle of regular quadrilateral contact areas, in microns. On this basis, this embodiment also designs the contact area width range of the p-type doped regions at the edge to be 0.1μm-3μm; and the contact area width range of the p-type doped region at the center to be 1μm-10μm. This design can reduce the higher junction temperature in the central area of ​​the chip, make the temperature distribution of the chip more uniform, and improve the reliability of the SiC diode.

[0048] Optionally, the distance between the upper surface of the p-type doping region and the upper surface of the n-type drift region is in the range of 0-100 μm, that is, they may be aligned, or the p-type doping region may have a small amount of sinking structure.

[0049] An outer metal layer 7 is provided on the upper surface of the contact metal layer 6 , and a back metal layer (not shown) is also processed on the lower surface of the substrate 1 .

[0050] On the basis of the above embodiments, the present invention also provides a method for manufacturing a silicon carbide diode. Figure 3 As shown, for ease of understanding, a relatively clear process sequence (S1-S6) is used for explanation, which should not be understood as a restrictive condition. In specific scenarios, technicians can adjust the sequence of process steps according to actual needs.

[0051] Therefore, the main steps of the method in this embodiment include:

[0052] S1. Pre-treat the substrate; select a 6-inch SiC substrate material with a processing thickness of 350μm, and perform surface cleaning and other surface treatment work;

[0053] S2. Preparing an epitaxial layer on the substrate, the epitaxial layer including a buffer layer and an n-type drift region; specifically, sequentially growing an N+ buffer layer and an N-drift layer (region) on the Si surface of a 6-inch SiC substrate;

[0054] S3, preparing a silicon dioxide mask on the epitaxial layer through a mask plate;

[0055] S4, based on photolithography and dry etching method to process the mask structure of p-type doping area, such as Figure 2As shown, the p-type doping region is doped twice by a high-temperature ion implantation method, thereby forming a p-type low-doping region and a p-type high-doping region;

[0056] S5, sequentially processing the contact metal layer 6 and the outer metal layer 7 on the epitaxial layer by a deposition method;

[0057] Furthermore, it also includes:

[0058] S6. Perform a thinning process below the substrate 1 and process a back metal layer on the processed lower surface by a deposition method.

[0059] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A silicon carbide diode, characterized in that: The method comprises a substrate; a buffer layer, an n-type drift region, a contact metal layer, and an outer metal layer are sequentially arranged on the substrate in a vertical direction; The n-type drift region is provided on the upper surface of the buffer layer; a plurality of p-type doped regions are embedded in the drift region of the n-type drift region; The contact metal layer is provided on the upper surface of the n-type drift region; the contact metal layer contacts the n-type drift region and the p-type doped region respectively; the width of the contact region between the p-type doped region and the contact metal layer increases sequentially from the outer edge to the center of the n-type drift region; The outer metal layer is provided on the upper surface of the contact metal layer.

2. The silicon carbide diode according to claim 1, characterized in that The p-type doping region includes a p-type low-doping region and a p-type high-doping region; The p-type highly doped region forms an ohmic contact region with the contact metal layer; The adjacent p-type doped region and the contact metal layer form a Schottky contact region.

3. The silicon carbide diode according to claim 2, characterized in that The doping width of the p-type low-doping region is in the range of 0.1 μm to 10 μm; The depth of the p-type low-doping region ranges from 0.5 μm to 10 μm.

4. The silicon carbide diode according to claim 2, characterized in that The doping width of the p-type high-doping region is in the range of 0.1 μm to 10 μm; The depth of the p-type high-doping region ranges from 0.5 μm to 10 μm.

5. The silicon carbide diode according to claim 3 or 4, characterized in that: The width of the contact region between the p-type doped region at the outer edge of the n-type drift region and the contact metal layer is in the range of 0.1 μm to 3 μm; The width of the contact region between the p-type doping region at the center of the n-type drift region and the contact metal layer is in the range of 1 μm to 10 μm.

6. The silicon carbide diode according to claim 5, characterized in that The width of the contact area between the p-type doping area and the contact metal layer increases gradually in a range of 1 μm to 10 μm per micron.

7. The silicon carbide diode according to claim 1, characterized in that The distance between the upper surface of the p-type doping region and the upper surface of the n-type drift region is in the range of 0-100 μm.

8. The silicon carbide diode according to claim 1, characterized in that The surface profile of the p-type doping region is at least one of a stripe, an alternate stripe, a regular quadrilateral, and a regular hexagon; The width of the contact region between the p-type doping region and the contact metal layer is the maximum width of the surface profile of the p-type doping region.

9. The silicon carbide diode according to claim 1, characterized in that The contact metal layer is a titanium metal layer or a nickel metal layer, or a titanium-nickel alloy layer.

10. The silicon carbide diode according to claim 1, characterized in that The lower surface of the substrate is further provided with a back metal layer.

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