Vacuum system

Abstract

A vacuum system comprising one or more vacuum chambers, a coating region disposed in the one or more vacuum chambers; a sputtering device having a storage device for storing one or more sputtering targets (404) and adapted to sputter the sputtering targets (404) into a coating region; wherein the sputtering target (404) comprises a semiconductor material; wherein the sputtering target (404) further comprises a dopant of the semiconductor material, the dopant content being greater than the solubility limit of the dopant in the semiconductor material and / or a mass fraction of the dopant of 0.15%; disposing (305) the solar cell precursor (402) inserted in the substrate carrier in the coating region (401) while atomizing the sputtering target (404) into the coating region (401) such that the face faces the sputtering target (404); wherein the base carrier is configured such that an edge (510k, 512k) of the solar cell precursor (402), which extends along the self-contained path, is shielded by the base carrier from fogging with respect to the sputtering target (404).

Description

Background Art

[0001] Since the development and commercialization of solar cells for power generation, their efficiency has been one of the key optimization parameters. Since then, various solar cell technologies have been developed to increase efficiency without compromising the benefit-to-manufacturing cost ratio. One such solar cell technology is so-called PERC technology ("Passivated Emitter and Rear Cell"), which uses a dielectric film to passivate the rear surface, thereby increasing light yield. However, it has been discovered that recombination losses left behind by the metal contacts that penetrate the rear passivation layer of PERC technology still significantly limit efficiency.

[0002] According to various embodiments, as a further development of PERC technology, so-called passivation contacts can reduce these recombination losses. A characteristic feature of such passivation contacts is that their metallization is dielectrically separated from the semiconductor junction of the solar cell. In one exemplary implementation, the passivation contact is designed as a tunneling oxide passivation contact (so-called TOPCon), which comprises a thin stack, for example a 1-3 nm (nanometer) thick tunneling oxide layer (e.g. made of SiOx), on top of which is a layer of SiOx, on top of which is a polycrystalline doped silicon film, an optional dielectric layer of suitable thickness and refractive index (e.g. made of SiNx:H) to improve light coupling in bifacial photovoltaic modules and to provide hydrogen, and a metallization layer on top. TOPCon technology is expected to enable, for example, silicon-based solar cells to achieve efficiencies greater than 24%.

[0003] According to various embodiments, it has been recognized that the processes used to date for producing solar cells would result in high costs if also used for the production of passivating contacts. From a technical perspective, doped silicon thin films can be produced using existing chemical vapor deposition (CVD) processes, such as plasma-enhanced CVD (PECVD) or low-pressure CVD (LPCVD). However, CVD uses toxic gases and its scalability is also limited. In addition, after the CVD process, post-processing of the solar cell is generally required, as the deposition is performed on all sides, resulting in a destructive coating of at least part (i.e., part or all) of the wafer edges (also known as edge wrapping) or side surfaces, as well as the side of the wafer facing away from the coating process. Due to this edge wrapping, the conductive connection between the usually p-type doped region on the front side of the solar cell and the usually n-type doped region on the back side is advantageous, which causes an electrical short circuit in the solar cell and permanently impairs its efficiency and reverse current characteristics.

[0004] To remove this edge wrapping, additional process steps, such as wet chemical etching, are required. These additional process steps incur additional costs and increase the risk of additional scrap in the production process. Consequently, the costs of implementation quickly outweigh the benefits, and an economically viable approach for large-scale production has yet to emerge. In addition to the associated costs, currently available process technologies for removing excess deposited material also result in prohibitively high scrap losses (both electrical and optical), which hinders profitable use in large-scale production.

[0005] In this context, despite the potential improvements in efficiency offered by passivated contacts, they have not yet been used in the large-scale production of solar cells. Summary of the Invention

[0006] According to various embodiments, a process is provided for improving the economic efficiency of solar cell production or facilitating its manufacture. It is clearly recognized that most of the aforementioned obstacles can be overcome, inter alia, by using physical vapor deposition (PVD), preferably sputtering, for example in combination with a shield and / or low coating temperature. These measures significantly improve coating properties, for example with respect to stoichiometry, use of toxic volatile substances, and / or tendency to form edge wrapping. For example, lower coating temperatures help save energy, inhibit the formation of toxic volatile substances, and reduce the risk of layer flaking.

[0007] According to various embodiments, a vacuum apparatus (e.g., a vacuum system) is further provided for coating a silicon wafer with a layer stack for producing a passivation contact by a PVD process (e.g., for mass production of silicon solar cells with passivation contacts). For example, a passivation contact based on a tunneling oxide layer and a doped polysilicon layer is provided. The required dopant in the silicon layer, such as phosphorus in the case of n-doping, can also be incorporated in a subsequent high-temperature step to generate a polysilicon layer from the deposited amorphous or semi-crystalline silicon layer. This results in the required conductive layer stack for forming the passivation contact (referred to as TOPCon).

[0008] A vacuum system comprises one or more vacuum chambers, wherein a coating area is arranged in the one or more vacuum chambers; a sputtering device, wherein the sputtering device has a storage device for storing one or more sputtering targets and is suitable for sputtering the sputtering targets into the coating area; wherein the sputtering target comprises a semiconductor material, and the sputtering target also comprises a dopant for the semiconductor material, and the content of the dopant is greater than 0.15at% of the material content fraction of the dopant; a conveying system, wherein the conveying system has a substrate carrier and is configured to convey a solar cell precursor, and when the sputtering target is sputtered into the coating area, the solar cell precursor inserted into the substrate carrier is arranged in the coating area; wherein the substrate carrier is configured in such a way that an edge of the solar cell precursor extending along a closed path blocks the sputtering of the sputtering target through the substrate carrier.

[0009] In some embodiments, the substrate carrier includes a shield, by which the edge is shielded and / or by which the sputtering target is atomized.

[0010] In some embodiments, the substrate carrier has an opening that exposes the solar cell precursor to the sputtering target, the opening being defined by a convex surface of the substrate carrier.

[0011] In some embodiments, the target state of the vacuum system during operation is set so that when the solar cell precursor is inserted into the coating area, the temperature of the solar cell precursor is lower than about 200° C. and / or lower than the temperature of the sputtering target.

[0012] In some embodiments, the vacuum system further comprises a gas transfer device comprising a quick connector, the gas transfer device being adapted to supply and / or extract gas components to the coating area through the quick connector; and a single-walled pipe, the coating area being connected to the gas transfer device through the single-walled pipe.

[0013] In some embodiments, when sputtering the sputtering target into the coating region occurs, the solar cell precursor is disposed in the coating region such that a side of the solar cell precursor coated with at least one dielectric faces the sputtering target.

[0014] In some embodiments, the temperature of the solar cell precursor is less than about 100° C. when the solar cell precursor is inserted into the coating region.

[0015] In some embodiments, the sputtering device is configured to form a layer on the solar cell precursor by sputtering the sputtering target, wherein a quantity ratio of the dopant to the semiconductor material in the layer is smaller than or the same as that of the sputtering target.

[0016] In some embodiments, the layer is at least partially amorphous and / or has a sheet resistance of at least 1000 ohms.

[0017] In some embodiments, when the solar cell precursor is disposed in the coating region, the substrate carrier is configured such that the edge of the solar cell precursor is substantially uncoated. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] It shows

[0019] Figure 1 and Figure 2 Schematic cross-sectional views are used to illustrate solar cells of different embodiments;

[0020] Figure 3 The process according to various embodiments is shown in a schematic flow chart;

[0021] Figure 4 shows in schematic cross-sectional view a vacuum apparatus in a sputter-up configuration according to various embodiments;

[0022] Figure 5A and Figure 5B Different views are shown of solar cell precursors according to different embodiments;

[0023] Figure 6 A schematic cross-sectional view shows a vacuum apparatus in a sputter-down configuration according to various embodiments;

[0024] 7A to 7C Different views are shown of solar cell precursors according to different embodiments;

[0025] Figure 8 Schematic diagrams show working results according to different embodiments;

[0026] Figure 9 and Figure 10 Schematic cross-sectional views of vacuum devices according to different embodiments are shown;

[0027] Figure 11A and Figure 11B shows substrate carriers according to different embodiments in different views; and

[0028] Figure 12 Coating devices according to various exemplary embodiments are shown in schematic side views or in cross-sectional views. DETAILED DESCRIPTION

[0029] In the following detailed description, reference is made to the accompanying drawings, which are an integral part of the present invention and, for purposes of illustration, illustrate specific embodiments of the invention. In this regard, directional terms such as "top," "bottom," "front," "rear," "front," and "rear" are used with reference to the orientation of the figures being described. Because components in embodiments of the present invention can be positioned in a variety of different orientations, the directional terms are used for illustrative purposes only and are not limiting. It goes without saying that other embodiments may be used and structural or logical changes may be made without departing from the scope of the present invention. It should be understood that, unless otherwise specifically stated, the features of the various exemplary embodiments described herein may be combined with one another. Therefore, the following detailed description is not limiting and the scope of the present invention is defined by the appended claims.

[0030] In this specification, the terms "connect", "connection" and "coupling" are used to describe direct and indirect connections (e.g., ohmic connections and / or conductive connections, such as conductive connections), direct or indirect connections, and direct or indirect couplings. In the drawings, identical or similar elements are denoted by identical reference symbols where appropriate.

[0031] With respect to compounds explained herein, such as oxides, carbides and / or nitrides, it is understood that these compounds may be stoichiometric or substoichiometric (i.e., have vacancies). For example, substoichiometric silicon oxide may be represented as SiO 2-y (y>1), or simply called SiOx(x=2-y).

[0032] The material content mentioned in this article can be expressed in various ways, such as

[0033] - the amount relative to a reference material (also called the quantity ratio, for example specified as the doping intensity (e.g. atomic number ratio) or mass ratio;

[0034] - a proportion, such as a proportion to the total mass of a reference substance (also called a mass proportion, such as wt%), a proportion to the total volume of a reference substance (also called a volume proportion, such as vol%), or a proportion to the substance content of a reference substance (also called a substance content proportion, such as at%), wherein the reference substance contains the material, or

[0035] - concentration (e.g., specified as the number of atoms per unit volume, such as at / cm 3 ).

[0036] For example, a body containing the material (e.g., a sputtering target or layer) or a material mixture containing the material (e.g., a semiconductor material and a dopant) can serve as a reference. For example, a material mixture can be a mixture of two materials. For example, a reference material can be a material other than the material, such as a semiconductor material.

[0037] The purity of the material in the reference (also called material purity) is also mentioned here, such as a material mixture (also including materials with less contamination), such as a solid in a material mixture. Purity is specified as the substance content of the material in the reference, for example 99.9at%. For high-purity materials, the purity is usually greater than 99at%. The value with one or more decimal places is usually 9. For simplicity, only the sum of 9 digits z (before and after the decimal point) of the purity value is given, followed by the letter N (z is a natural number), for example, if z = 6, it means "6N". Purity is (10 z -1) / 10 (z-2) at%. Therefore, purity 6N means a purity value of at least 99.9999 at%. The optional additional digits after N represent the numbers after the 9 series. For example, purity 3N5 means 99.95 at%.

[0038] Reference is made herein to a method and a vacuum apparatus (e.g., a vacuum system), e.g., a vacuum apparatus suitable for performing the method, for treating a solar cell precursor (also referred to as a solar cell substrate or a partially treated solar cell) as an example substrate. It will be understood that the description of the solar cell precursor is applicable to any other substrate coated with one or more dielectrics, the dielectric preferably being an oxide (e.g., a semiconductor oxide, such as silicon oxide). With respect to coating and / or treatment, it will be further understood that the description of a particular side (e.g., the back side or the front side) of a solar cell precursor (or substrate) is analogously applicable to the respective opposite side (then the front side or the back side) of the solar cell precursor (or substrate). In other words, the treatment of a solar cell precursor (or substrate) described herein may apply only to its front side, only to its back side, or to each of the two sides (e.g., one after the other), i.e., the front side and the back side.

[0039] Traditionally, the polycrystalline doped silicon layer of the passivation contact is produced by chemical vapor deposition (CVD), such as low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or atmospheric pressure CVD deposition (APCVD). Unlike PVD, CVD separates the gaseous starting compounds (also called precursor gases or reactants) into at least two reaction products, at least one of which is incorporated into the coating and the other is removed from the coating process as excess (e.g., by a pump). Alternatively, CVD can be performed using a plasma, where the precursors are separated (also called PECVD).

[0040] The processes described herein may include, for example, forming a passivating contact or a precursor thereof on the back side of a solar cell and / or on the front side of a solar cell (ie, the side facing the sun).

[0041] Regarding layer formation processes, this article will mention so-called sputtering as an example. The term "sputtering" refers to the atomization of a material (also called coating material or target material) by means of a plasma. The atomized components of the coating material (e.g., individual atoms and / or ions) are separated from one another and can be deposited elsewhere, for example, to form a layer. Sputtering can be performed using a so-called sputtering device, which can have one or more magnet systems (also called magnetrons). The coating material can be provided by a so-called sputtering target (also simply called target), which can be, for example, tubular (also called tube target) or plate-shaped (also called plate target or planar target). To generate the plasma, a voltage (also called sputtering voltage) can be applied to the sputtering target (also simply called target), causing it to operate as a cathode. Even though the sputtering voltage is an alternating voltage, the term cathode is often retained.

[0042] For sputtering, the sputtering target can be arranged in a vacuum processing chamber (also referred to as a processing chamber for short) so that sputtering is carried out in a vacuum. For this purpose, the environmental conditions (process parameters) (e.g., process pressure, temperature, gas composition, etc.) in the vacuum processing chamber can be adjusted or controlled during the sputtering process. For example, a working gas, which means a plasma-forming gas or a plasma-forming gas mixture, can be provided in the processing chamber. For example, the processing chamber can be or can be made airtight, dust-proof and / or vacuum-tight, so that a gas environment (also referred to as a working environment), such as a vacuum, with a predetermined composition or predetermined pressure (also referred to as a working pressure or process pressure) can be provided in the processing chamber (e.g., according to a set value).

[0043] A plasma can be formed using a so-called working gas (also called a plasma-forming gas). Depending on the embodiment, the working gas may comprise an inert gaseous material, in other words, one that participates in little or no chemical reaction. The working gas may be or be defined by the target material being used and may be or be adapted to the target material. For example, the working gas may be a gas or gas mixture that does not react with the target material to form a solid, or may even be inert to the target material. For example, the working gas may comprise an inert gas (e.g., helium, neon, argon, krypton, xenon, radon) or a combination of inert gases. For example, a plasma may be formed using a working gas, which essentially atomizes the target material. If a reactive gas is used, its chemical reactivity may be higher than that of the working gas, e.g., with respect to the target material. In other words, the atomized target material may react faster with the reactive gas (if present) than with the working gas (e.g., if it chemically reacts with the working gas) (i.e., forming more reaction products per reaction). The reactive gas and working gas may be supplied together or separately as process gases (e.g., as a gas mixture), e.g., via a gas supply device.

[0044] It is understood that the sputtering described herein is analogously applicable to any other coating process, such as physical vapor deposition. Physical vapor deposition (e.g. sputtering) involves the transfer of the chemical composition of the target or coating material to the The formed layer , for example, the sputtered target does not interact (e.g., react) with the reactive gas, which is also known as reactive PVD. When a reactive gas is used, a layer composed of the reaction products of the target and the reactive gas can be formed. For example, a SiNx:H layer can be formed using a Si target and NH3 (ammonia) as the reactive gas.

[0045] Unlike CVD, in PVD (e.g., sputtering), a solid material is first converted into a gas phase (also called a vapor phase or vapor), which is then used to form a layer. In PVD, the gas phase of the target material can selectively (e.g., in reactive PVD) chemically react with a reactive gas (also called reactive PVD or sputtering) to form a compound, which is then incorporated into a layer or formed into a layer. In the chemical reaction of PVD, two or more materials are thus combined to form a compound.

[0046] For example, sputtering can be used to form semi-crystalline to amorphous silicon films, which are then doped and / or crystallized in a high temperature step (referred to as solid phase crystallization).

[0047] To simplify understanding, this document will refer to n-doping as an example of the first type (e.g., n-type or donor type) doping, and p-doping as an example of the second type (e.g., p-type or acceptor type) doping. For example, the physical structure of a solar cell (e.g., a solar cell in TOPCon technology) can be explained using an n-doped base layer (e.g., comprising a silicon wafer) and a p-doped emitter layer (e.g., boron doped). It is generally understood that the description of these example doping methods can be applied analogously to the opposite doping method.

[0048] In general, a passivation contact (e.g., TOPCon) can have a layer stack consisting of doped semiconductor layers (also called interposers). The interposer matches the base layer in terms of doping type (e.g., n-type or p-type) and differs from the emitter layer in terms of doping type. In an exemplary implementation, the solar cell has a p-type doped emitter layer on the side facing the sun (i.e., the front side of the solar cell) and an n-type doped passivation contact on the side facing away from the sun (i.e., the back side of the solar cell). Therefore, what is described also applies to solar cells with a p-doped base layer and an n-doped emitter layer or a p-doped passivation contact.

[0049] Other examples of solar cells that can use passivated contacts include: solar cells with passivated contacts on both sides (a variant of heterojunction solar cells), either covering the entire surface or limited to the area below the metal contact where the passivating contact layer stack is used; and solar cells with contacts only on the back side facing away from the sun, where both types of charge carriers (electrons and holes) are discharged outward via electrical contacts on one side of the solar cell.

[0050] It also refers to a metallization layer (e.g., a backside metallization layer or a frontside metallization layer), for example, as part of a passivation contact. Such a metallization layer can also, but not necessarily, be formed after the solar cell precursor is transported from the coating area, for example, after being ejected from a vacuum apparatus (e.g., a vacuum is provided therein). For example, the metallization layer can be formed by screen printing or other printing processes such as inkjet printing, rotary printing, or extrusion printing, or by electroplating.

[0051] Regarding passivation contacts, this article uses the tunneling oxide passivation contact (TOPCon) as an example. The description of TOPCon is analogously applicable to any other type of passivation contact, for example, it does not necessarily require a tunneling oxide layer and can also include other oxide layers or nitride layers.

[0052] In the context of dopants in semiconductor materials, the term "solubility limit" refers to the upper limit of the dopant content in a solid mixture (dopant and semiconductor material) within which the mixture forms a homogeneous mixture during solidification and / or under normal conditions (293.15 Kelvin and 1.01325 bar). If the dopant content in the semiconductor material is greater than the solubility limit, the mixture will separate, for example, when the mixture is cooled from a melting temperature (for example, which can be close to the melting temperature of the semiconductor material (i.e., less than 10%)) to normal conditions. In general, the solubility limit in this article is related to normal conditions. For example, if the dopant is boron, phosphorus, arsenic or antimony and the semiconductor material is silicon, the solubility limit SG can be less than about 10 20 at / cm 3 (Here also expressed as 1E20at / cm 3 ), for example, less than 5.10 19 at / cm 3 .

[0053] Figure 1 A schematic cross-sectional view of a solar cell according to various embodiments 100 is shown. The structure shown here relates to a finished solar cell, which (for example, together with one or more additional solar cells) can be further processed to form a module (also referred to as a solar cell module or solar module) by electrically connecting its metallization layers 110, 112 to connection terminals and / or additional solar cells. A solar cell precursor refers to a precursor of a solar cell, which, as described below, may already have some, but not necessarily all, components of a solar cell.

[0054] The solar cell precursor comprises a doped (e.g., n-doped) first semiconductor layer 102 (also referred to as a base layer), such as a wafer, disposed between the front side 100v and the back side 100r of the solar cell precursor. The front side 100v of the solar cell precursor may optionally be textured and / or structured. This may enhance light absorption.

[0055] The solar cell precursor further comprises a doped (e.g., p-doped) second semiconductor layer 104 (also referred to as emitter layer 104), adjacent to the base layer 102 and / or facing the front side 100v. The base layer 102 and the emitter layer 104 can form a (e.g., bipolar) semiconductor junction (also referred to as pn junction), for example, if their doping types are different from each other (e.g., n-type or p-type).

[0056] The solar cell precursor also has one or more dielectric layers (also called passivation layers or simply passivation) (see also Figure 2), for example, the dielectric layer comprises or consists of one or more dielectrics (also referred to as passivation dielectrics). Examples of the one or more passivation layers include: a first passivation layer 106v (also referred to as front passivation 106v, see also front side passivation 106v) on the front side 100v (also referred to as passivation front side 100v); Figure 2 ) and / or a second passivation layer 106r (also referred to as back side passivation 106r) on the back side 100r (also referred to as passivation back side 100r).

[0057] The base layer 102 is disposed between the back passivation 106r (if present) and the emitter layer 104. For example, the back passivation 106r can form a tunneling oxide layer. For example, its thickness can be less than about 5 nanometers (nm), such as less than about 2 nanometers (nm) and / or in the range of about 1 nm to about 2 nm.

[0058] The passivation dielectric may include, for example, a semiconductor material (e.g., silicon), for example, in a compound and / or composed of the semiconductor material of the base layer 102. Examples of one or more passivation dielectrics include chemical compounds of a semiconductor material and oxygen, compounds of a semiconductor material and carbon, compounds of a semiconductor material and nitrogen, oxides, carbides, nitrides, or mixtures thereof. For example, the backside passivation 106r comprises or consists of a semiconductor oxide (e.g., silicon oxide).

[0059] The processing of the solar cell precursor described herein may include processing the passivation surface (e.g., the back surface 100r and / or the front surface 100v) of the solar cell precursor, for example, by coating it with an amorphous and / or doped layer (also referred to as an interposer), the amorphous and / or doped layer being in (e.g., electrical and / or physical) contact with the passivation layer on that surface. The processing of the passivation surface (e.g., the back surface 100r and / or the front surface 100v) of the solar cell precursor may be performed by physical vapor deposition (PVD), as will be described in detail below.

[0060] With reference to the solar cell illustrated herein, processing of the solar cell precursor may include processing of the passivated back side 100r, for example, coating it with an amorphous and / or doped (e.g., n-doped) interposer 108r (also referred to as back side interposer 108r), which is in (e.g., electrical and / or physical) contact with the back side passivation 106r.

[0061] In subsequent processing, the back-side interposer 108r may optionally be coated with a conductive material (e.g., including a metal or at least a metal) that is in (electrical and / or physical) contact with the back-side interposer 108r. The conductive material may form a back-side metallization layer 112 (also referred to as metallization). The metallization may, but is not necessarily, performed in a vacuum.

[0062] The coated back side 100r thus comprises a layer stack 112, 114r, 108r, 106r (also referred to as a passivation contact layer stack), comprising a back side metallization layer 112, an optional dielectric layer 114r formed thereunder (e.g., a light coupling layer, as described in greater detail below), an interposer 108r formed thereunder, and a back side passivation layer 106r formed thereunder. The contact layer stack 112, 114r, 108r, 106r can form or at least be part of a passivation contact, which, when the back side interposer 108r is a tunneling oxide layer, is referred to as a back side tunneling oxide passivation contact (TOPCon). The back side TOPCon described herein can be designed as an n-type passivation back side contact (TOPCon). For simplicity, the initial stage of the passivation contact, e.g., without metallization and / or without an anti-reflective coating (e.g., also referred to as a light coupling layer), is also referred to as TOPCon. The description of TOPCon is analogously applicable to any other type of passivation contact, e.g., not necessarily including a tunneling oxide layer.

[0063] The formation of a single-sided TOPCon (e.g. its metallization layer, e.g. metal contact), e.g. on the rear side 100r, can be grid-shaped and / or realized by a grid (e.g. double-sided TOPCon) (also referred to as grid TOPCon) and / or does not necessarily have to be over the entire surface. In this regard, it should be noted that the entire contact layer stack of the grid TOPCon does not necessarily have to be grid-shaped. For example, at least the passivation and / or intermediate layer (e.g. aSi / polySi layer) and / or the optical coupling layer of the TOPCon can also be formed over the entire surface. For example, if the TOPCon is arranged on the front side 100v, or the solar cell precursor (or finished solar cell product) is only contacted on one side, the intermediate layer (e.g. aSi / polySi layer) of the TOPCon can be formed alternatively or additionally only below the grid-shaped metallization layer.

[0064] In one exemplary implementation, an interposer layer of a TOPCon composed of aSi (e.g., n-doped) and / or polySi (e.g., n-doped) can be formed or formed as a grid. For example, the interposer layer can be formed only below the grid-like metal contacts of the solar cell. The passivation of the TOPCon can also be formed over the entire surface.

[0065] The solar cell precursor optionally has an anti-reflection coating 114v (e.g., dielectric and / or transparent) on the front side 100v (also referred to as a front anti-reflection coating 114v), the anti-reflection coating 114v having one or more anti-reflection layers (e.g., a stack of multiple anti-reflection layers). For example, the thickness of the front anti-reflection coating 114v can be in a range of about 50 nanometers to about 500 nanometers. For example, the refractive index of the front anti-reflection coating 114v can be less than about 2.2, for example, less than about 1.5, for example, less than about 1.4. For example, the front anti-reflection coating 114v can include a dielectric, such as a nitride (e.g., a semiconductor nitride such as silicon nitride). For example, the anti-reflection coating 114v includes silicon nitride.

[0066] The solar cell precursor (e.g., its contact layer stack) optionally includes an (e.g., dielectric and / or transparent) anti-reflection coating 114r (also referred to as a backside anti-reflection coating 114r) on the backside 100r, the anti-reflection coating 114r comprising one or more anti-reflection layers (e.g., a stack of multiple anti-reflection layers). The thickness of the backside anti-reflection coating 114r can, for example, be in a range of about 50 nanometers to about 500 nanometers. The backside anti-reflection coating 114r can, for example, have a refractive index of less than about 2.2, such as less than about 1.5, such as less than about 1.4. The backside anti-reflection coating 114r can, for example, be disposed between the backside metallization layer 112 (if present) and the backside passivation 106r (if present), for example, in physical contact with the interposer layer 108r and / or the backside metallization layer 112 (if present). If backside anti-reflective coating 114r is present and dielectric, the stack of backside passivation 106r, interposer 108r (if present) and backside anti-reflective coating 114r may also provide, for example, backside passivation or provide at least a portion of a backside TOPCon layer stack.

[0067] For example, the backside anti-reflection coating 114r may include a dielectric, such as a nitride (e.g., a semiconductor nitride such as silicon nitride). For example, the backside anti-reflection coating 114r includes silicon nitride. For example, the backside anti-reflection coating 114r may include SiNx:H or at least consist of SiNx:H.

[0068] Optionally, the backside anti-reflective coating 114r may include hydrogen. This allows hydrogen to be provided from the backside anti-reflective coating 114r, thereby improving the passivation performance of the TOPCon by reducing the recombination of free charge carriers at the interface, for example, by saturating free bonds at the interface between the substrate 102 and the tunneling oxide layer 106r.

[0069] Optionally, the front anti-reflective coating 114v (if present) may have one or more through-holes, each of which exposes a highly doped portion 104l (also referred to as a local emitter 104l) of the emitter layer 104. Alternatively or additionally, the through-hole or each through-hole of the front anti-reflective coating 114v may be filled with a conductive material (e.g., including a metal or at least a metal) that is in (electrical and / or physical) contact with the emitter layer 104. The conductive material may be part of the front metallization 110 (also referred to as the front metallization layer 110) and / or at least protrude beyond the anti-reflective coating 114v.

[0070] The emitter layer 104 is located between the base layer 102 and the front side metallization layer 110 (if present) and / or the front side anti-reflective coating 114v (if present).

[0071] Figure 2 A schematic cross-sectional view of a solar cell according to various embodiments 200 is shown, which is similar to embodiment 100 except that (instead of or in addition to the back surface 100r) the front surface 100v is passivated (via a front surface passivation 106v) or a TOPCon (or at least a portion thereof) is formed thereon. The emitter layer 104 is disposed between the front surface passivation 106v and the base layer 102.

[0072] In this case, processing of a solar cell precursor comprising, for example, a passivated back side 100r may include forming an amorphous and / or doped (e.g., p-doped) interposer 108v (also referred to as front interposer 108v) on the front side passivation 106v, which interposer 108v is in (e.g., electrical and / or physical) contact with the front side passivation 106v.

[0073] For example, the front side passivation 106v may form a tunnel oxide layer, and its thickness may be less than about 5 nanometers, such as less than about 2 nanometers and / or in the range of about 1 nanometer to about 2 nanometers.

[0074] In subsequent processing, the front interposer 108v is optionally coated with a front anti-reflective coating 114v and / or a conductive material (e.g., comprising a metal or at least a metal), which is in (electrical and / or physical) contact with the front interposer 108v and / or the front anti-reflective coating 114v. The conductive material may form a front metallization layer 110. The front interposer 108v thus formed may be disposed between the emitter layer 104 and the front anti-reflective coating 114v (if present) and / or the front metallization layer 110 (if present).

[0075] Optionally, the front anti-reflective coating 114 v may have one or more through-holes, each of which exposes a portion of the front interposer 108 v. Alternatively or additionally, the through-hole or each through-hole of the front anti-reflective coating 114 v may be filled with a conductive material (e.g., including metal or at least metal) of the front metallization layer 110, which is in (electrical and / or physical) contact with the emitter layer 104.

[0076] The coated front side 100v thus comprises a contact layer stack 110, 114v, 108v, 106v, comprising the front side metallization layer 110, an anti-reflective coating 114v formed thereunder, an interposer 108v formed thereunder, and a front side passivation 106v formed thereunder. When the front side interposer 108v is a tunneling oxide layer, the contact layer stack 110, 114v, 108v, 106v is also referred to as a front side tunneling oxide passivation contact (TOPCon). The front side TOPCon illustrated here can be designed as a p-type passivated front side contact.

[0077] In subsequent processing, the back-side interposer 108r (if present) may optionally be coated with a (e.g., dielectric) anti-reflective coating 114r (also referred to as back-side anti-reflective coating 114r) on the back side 100r. Alternatively or additionally, the back-side interposer 108r (if present) may be coated with a conductive material (e.g., including a metal or at least a metal) that is in (electrical and / or physical) contact with the interposer 108r and / or the anti-reflective coating 114r. The conductive material may form a back-side metallization layer 112 or at least a portion of the back-side metallization layer 112.

[0078] The back surface 100r of the solar cell precursor may optionally be textured and / or structured (not shown), which may improve light absorption.

[0079] In the following, reference will be made to the treatment of the passivated side (also referred to as the passivation side) of the solar cell precursor. Examples of passivation sides include: the back side 100r of the solar cell precursor coated with a back passivation 106r; and / or the front side 100v of the solar cell precursor coated with a front passivation 106v. The treatment of the passivation side can be applied analogously to the treatment of the passivation back side 100r, the passivation front side 100v, or both passivation sides (preferably consecutively). For example, both sides can be coated in the same treatment chamber (e.g., coating can also be performed from above and below simultaneously).

[0080] Figure 3A schematic flow chart illustrates a process 300 according to various embodiments. The process 300 includes, at 303, atomizing a sputtering target into a coating region (e.g., forming a vacuum in the region); and, at 305, placing a solar cell precursor in the coating region with the passivated surface of the solar cell precursor facing the sputtering target. The process 300 may optionally include, at 301, bringing the solar cell precursor into the vacuum formed in the coating region; and, at 303, removing the solar cell precursor from the vacuum formed in the coating region.

[0081] For example, when the solar cell precursor is arranged in the coating area and / or when the sputtering target material is atomized into the coating area, the solar cell precursor can be arranged in a substrate holder, for example in a recess thereof (also called a substrate receiving recess), as will be described in more detail later.

[0082] For example, when the solar cell precursor is arranged in the coating area and / or the sputtering target is atomized into the coating area, the temperature of the solar cell precursor (also referred to as the coating temperature) can be less than about 200° C., preferably less than about 100° C., and / or less than the temperature of the sputtering target. This has the advantage of improving the coating properties, such as the coating properties of the (e.g. front or back) interlayer, saving energy, inhibiting the formation of toxic volatiles and / or inhibiting flaking of the interlayer. For example, if the solar cell precursor is located in the coating area and / or the sputtering target is atomized into the coating area, the coating area can be unheated (except for the heat input of the sputtering itself).

[0083] For example, the sputtering target may include a semiconductor material (e.g., the semiconductor material of the base layer 102 and / or the back passivation 106r) and a dopant (e.g., an n-dopant) of the semiconductor material (e.g., a binary and / or homogeneous mixture). The sputtering target may be a so-called highly doped sputtering target. The doping amount of the highly doped sputtering target (e.g., relative to the semiconductor material) may be greater than the solubility limit SG of the dopant in the semiconductor material (also referred to as a highly doped target) and / or greater than 0.15 wt % (e.g., if the dopant is phosphorus and the semiconductor material is silicon (e.g., 0.15 wt % P in silicon corresponds to approximately 0.14 at % or 7E19 at / cm 3 )).

[0084] The plasma formed by the sputtering target or the layer formed therefrom (eg, an interlayer) may have a chemical composition similar to that of the sputtering target, eg, the ratio of the amount of dopant to the semiconductor material is substantially the same as that of the sputtering target.

[0085] It is well known that, although the target materials used in sputtering (also called sputtering targets) can be produced efficiently and cost-effectively from a melt (also called cast targets), this production process is subject to narrow restrictions in terms of material selection. If the target material is to form a solid homogeneous mixture, it may have a solubility limit SG, above which the mixture segregates, thus forming a heterogeneous mixture, etc. This segregation leads to the formation of precipitates and thus to an inhomogeneous chemical composition of the target material. An example of a solubility limit SG is a target material consisting of cast silicon (Si) in which phosphorus is dissolved. The maximum doping concentration Dmax of phosphorus (P) in silicon solids produced by commercial processes and sold on the market is about 0.15 at% P in silicon (equivalent to about 7·10 19 at / cm 3 ) or lower. If the solubility of P in silicon is greater than 0.15 at%, this cost-effective production method cannot be used. Then, according to different embodiments, the target material is produced by spraying and / or sintering.

[0086] According to various embodiments, sputtering (also referred to as plasma sputtering) of a homogeneous silicon / phosphorus mixture with a phosphorus content greater than 0.5 at % phosphorus can be achieved. According to various embodiments, by sputtering the silicon / phosphorus mixture, an amorphous phosphorus-doped silicon layer (also referred to as an aSiP layer) can be obtained as an interposer. After further treatment in a high-temperature step (e.g., at a temperature >900° C., >850° C., or >800° C., for example, for 1-5 minutes, >5 minutes, >15 minutes), for example, in a tube furnace to crystallize the deposited layer and simultaneously electrically activate the dopant (e.g., by incorporating the dopant into the silicon lattice), the interposer formed in this manner can have particularly good properties, for example, a sheet resistance of less than 1.5%, for example, a sheet resistance of less than 1000 (or 200) ohms (also referred to as a sheet resistance of 1000 ohms / square) and / or a (e.g., active) concentration (also referred to as dopant concentration) of the (e.g., electrically active) dopant (e.g., phosphorus) greater than 7.10 19 at / cm 3 , preferably greater than 1·10 20 at / cm 3 The dopant concentration may be related to the portion of the dopant that is active (also referred to as active dopant), such as the dopant that is incorporated into the crystal lattice. Optionally, the total dopant concentration of the interlayer may be greater than 7·10 19 at / cm 3 (For example, greater than 5.10 20 at / cm 3 or greater than 1.10 21 at / cm 3 , or for example 5·10 20 at / cm3 ), the vast majority of this dopant is inactive immediately after application (also referred to as inactive dopant). For example, the concentration of inactive dopant remaining after activation of the dopant (also referred to as reserve concentration) is greater or less than the dopant concentration (e.g., after performing a high temperature step). If the reserve concentration is greater than zero (e.g., greater than 1·10 20 at / cm 3 ), which will facilitate the incorporation of metal impurities (also known as decarburization). For example, the interposer can be formed in a manner that it has more grain boundaries than the back passivation 106r and / or the anti-reflective coating 114r. For example, by PVD, the grains of the interposer (diameter D of about 10-50 nm, compared to diameter D>100 nm) can be two to ten times smaller than other CVD-based processes (such as LPCVD, PECVD). Compared to polysilicon layers with diameters D>100 nm, the grain diameter of the interposer is two to ten times smaller, thereby introducing many grain boundaries, allowing phosphorus and metal impurities (from the target, wafer, or process) to be removed, for example, to be locally incorporated / fixed in the polysilicon layer, thereby inhibiting these impurities from causing a decrease in solar cell efficiency by contaminating the base layer 102 in subsequent process steps. These impurities are precisely the metal impurities from the entire process chain.

[0087] Optionally, the solar cell precursor may be heated before being transported to the coating area and / or after being transported out of the coating area, for example in a vacuum (e.g. vacuum equipment) and / or by a heating device 1010 (see Figure 9 and Figure 10 ). For example, the solar cell precursor can be cooled during transport into the coating area.

[0088] The passivation surface can be formed by coating a passivation (e.g., front passivation 106v or rear passivation 106r) on the surface of the solar cell precursor (also referred to as a passivation process). The passivation process can be performed before the solar cell precursor is transported to the coating area, for example, before it is introduced into the vacuum equipment (e.g., before entering the vacuum provided therein).

[0089] For example, the passivation process may include forming a passivation (e.g., including a tunneling oxide layer and / or silicon oxide) by a wet chemical process, by a plasma-assisted process in a vacuum (e.g., PECVD, LPCVD, PVD, ALD, etc.), and / or by a thermal reaction (e.g., oxidation). The thermal reaction may include exposing the side of the solar cell precursor to be passivated to a reactive gas (e.g., oxygen or even ozone) when the temperature reaches or exceeds the temperature at which the side of the solar cell precursor to be passivated reacts with the reactive gas (also referred to as the reaction temperature) (e.g., above 300° C.). The thermal reaction may also alternatively or additionally be performed in a tube furnace.

[0090] Optionally, method 300 may include one or more of the following:

[0091] - The formed interlayer (eg, silicon thin film) has an n-doped dopant concentration (eg, phosphorus as a dopant) greater than about 7.10 19 at / cm 3 , preferably greater than about 1·10 20 at / cm 3 , for example based on a semiconductor material such as silicon. This dopant concentration corresponds approximately to a dopant mass fraction (also specified as weight percent) of 0.15% (at 7.10 19 at / cm 3 ) or 0.22% (at 1.10 20 at / cm 3 when, for example, based on semiconductor materials (e.g., silicon);

[0092] - the dopant (also called dopant) is provided by at least one homogeneous solid (e.g. silicon / dopant target);

[0093] - no doping of the interposer from the molecular gas phase by sputtering of mosaic targets, dopant targets (so-called intermediate sputtering) and / or dopant slurries;

[0094] - The solar cell precursor is not exposed to molecular gases and / or hydrogen-containing gases, for example, not exposed to gases containing SiH4 and / or PH3, or not exposed to gases supplying SiH4 and / or PH3 during the formation of the intermediate layer, etc.;

[0095] - The interposer (e.g. silicon thin film) is deposited only on the passivation surface;

[0096] The intermediate layer (e.g., a silicon thin film) is spaced apart from, or is not in (electrical and / or physical) contact with, the side of the solar cell precursor opposite to the passivation side and facing the sputtering target;

[0097] The intervening layer (eg silicon thin film) formed in the coating area remains unchanged until the solar cell is graded and / or the intervening layer is not etched.

[0098] In short, forming the interposer by sputtering (compared to CVD) allows for lower coating temperatures and / or reduced hydrogen exposure of the solar cell precursor. The absence of hydrogen helps to avoid so-called blistering, i.e. localized flaking of the interposer due to the formation of bubbles (e.g., hydrogen bubbles). Consequently, there is no need to heat the substrate to high temperatures exceeding 300°C, such as approximately 350°C or greater than 400°C, to reduce the risk of blistering, which significantly reduces technical complexity and simplifies the choice of materials, such as substrate carriers. This makes it possible to coat the solar cell precursor with an unheated or only slightly heated (approximately 100°C-200°C, or at least below 300°C) interposer without the risk of blistering (e.g., compared to using PH3 as a doping gas).

[0099] Alternatively or additionally, the interposer may also have a plurality (eg two or more) of independent layers with different doping concentrations.

[0100] Figure 4 A schematic cross-sectional view (looking transversely toward the transport direction 111) illustrates a vacuum apparatus in a sputter-up configuration (also referred to as a sputter-up configuration) according to various embodiments 400. In the sputter-up configuration, a sputtering target 404 is arranged below a transport path along which a solar cell precursor 402 is transported in a coating region 401.

[0101] As described above, when the solar cell precursor 402 is disposed in the coating area 401 and / or when the sputtering target 404 is sputtered 303 into the coating area 401, the solar cell precursor 402 can be transported by the substrate carrier 406. The substrate carrier 406 can have a substrate receiving recess 406v in which the solar cell precursor 402 is disposed.

[0102] Each substrate receiving recess 406 v of the substrate carrier 406 may have a (e.g., frame-shaped) substrate support 406 a that defines the substrate receiving recess 406 v (e.g., in the direction of gravity 105). The substrate support 406 a may be penetrated by an opening 406 o (also referred to as a coating opening 406 o) that exposes the passivation surface (front side or back side) of the solar cell precursor 402 relative to the sputtering target 404.

[0103] The substrate support 406a has, for example, a planar support surface 610 surrounding the coating opening 406o on which the solar cell precursor 402 can rest. For example, the width 610b of the support surface 610 (see also Figure 6 ) (also referred to as support width) can be greater than about 0.5 millimeters (mm), such as greater than about 1 mm, such as greater than about 2 mm, such as greater than about 3 mm.

[0104] The substrate holder 406a (e.g., its support surface 610) can continuously surround (i.e., extend along a separate path) the coating hole 406o. This can prevent the edges of the solar cell precursor 402 (or adjacent side surfaces and / or edges thereof) from being coated. The substrate holder 406a illustratively provides a shield to protect the edges of the solar cell precursor 402 from coating material that is atomized 303 from below and enters the coating area 401.

[0105] The coating material atomized 303 to the coating region 401 may have atomic nuclei of semiconductor material (eg, Si) and dopant (eg, P), for example, a mass ratio of dopant atomic nuclei to semiconductor material atomic nuclei greater than 0.15%.

[0106] It will be appreciated that a loose shield may be used (eg, in addition to the substrate holder 406a being formed as a shield), for example, which may be positioned between the substrate holder 406a and the solar cell precursor 402 .

[0107] Figure 5A A solar cell precursor 402 according to various embodiments 500 is illustrated in a schematic top view (processing side), Figure 5B 500b is a schematic cross-sectional view. The interposer 108 formed by sputtering may be, for example, a back-side interposer 108r or a front-side interposer 108v.

[0108] As shown, the distance between the interposer 108 and one or more circumferential edges 510k, 512k or sidewalls 510 of the adjacent solar cell precursor 402 (also referred to as precursor sidewalls 510) can be, for example, greater than about 0.5 millimeters (mm), for example, greater than about 1 mm, for example, greater than about 2 mm, for example, greater than about 3 mm. In this way, the or each circumferential edge 510k, 512k or sidewall 510 of the solar cell precursor 402 can be separated from the interposer 108, and the passivation 106 (front passivation 106v or rear passivation 106r) can be exposed protruding from the interposer 108.

[0109] For example, the exposed edges of the passivation 106 (also referred to as edge exclusion) may continuously wrap around the interposer 108. For example, the interposer 108 may be an amorphous silicon layer (also referred to as a silicon layer).

[0110] The circumferential edge or sidewall 510 of the solar cell precursor 402 can be adjacent to or covered by the passivation 106 (eg, edge exclusion). For example, the oxide or passivation can have an edge perimeter.

[0111] Figure 6A schematic cross-sectional view (looking transversely toward the transport direction 111) illustrates a vacuum apparatus in a downward sputtering configuration (also referred to as a downward sputtering configuration) according to various embodiments 600. In the downward sputtering configuration, the sputtering target 404 is positioned above the path along which the solar cell precursor 402 is transported. For example, the transport direction 111 can be perpendicular to the direction of gravity 105.

[0112] As described above, when the solar cell precursor 402 is disposed in the coating area 401 and / or the sputtering target 404 is atomized 303 into the coating area 401, the solar cell precursor 402 can be transported by the substrate carrier 406. The substrate carrier 406 can have a substrate receiving recess 406v in which the solar cell precursor 402 is disposed.

[0113] Each substrate receiving recess 406v of the substrate carrier 406 may have a (e.g., frame-shaped) sidewall 602 (also referred to as a recess wall) that circumferentially defines the substrate receiving recess 406v. The substrate receiving recess 406v may have an opening 416o (also referred to as an upper coating opening 416o) that exposes the passivation surface (front side or back side) of the solar cell precursor 402 relative to the sputtering target 404.

[0114] The recess wall 602 (e.g., its edge) can continuously surround the upper coating opening 416o. This prevents the (illustrated lower) edge of the solar cell precursor 402 (or the side surface adjacent thereto) opposite the passivation surface from being coated. To this end, the geometric extent of the substrate receiving recess 406v (also referred to as a recess) or recess wall 602 can be adapted to the solar cell precursor 402.

[0115] For example, the recess wall 602 can have a height 602h (also referred to as wall height 602h) and can optionally taper toward the substrate support 406a. In this example, the height is measured from the apex of the side angle 602w to the upper edge of the recess wall 602 and is therefore greater than the depth of the substrate-receiving recess 406v (also referred to as recess depth 602t), which is measured from the apex of the angle 602w along the direction 105 to the support surface 610 of the substrate support 406a.

[0116] For example, the angle 602w (also referred to as the side angle) can be less than 160°, such as 130°. The height 602h and / or the recess depth can be greater than 1 mm, such as greater than 3 mm. For example, the height 602h and / or the recess depth can be greater than t times the distance 610c between the substrate 402 and the circumferential insertion angle 406e of the substrate carrier 406 (measured in the transport direction 111), where t can be greater than about 1, greater than about 3, greater than about 5 (for the recess depth 602t), or greater than about 2, or greater than about 5, or greater than about 10 (for the height 602h), and / or t can be in the range of about 0.5 to about 10.

[0117] More generally, the substrate holder can be configured to at least partially shield one or more circumferential edges of the solar cell precursor 402 (adjacent to the sidewall) from the sputtering target 404. This can be better achieved if an angle 608 (also referred to as shielding angle 608) is provided. The vertex of the shielding angle 608 can be located at the (exemplary upper) edge of the sidewall facing the sputtering target 404. The shielding angle 608 can be located in a plane spanned by the transport direction 111 and the gravity direction 105.

[0118] The first chord line 608 a of the shielding angle 608 may satisfy one or more of the following conditions: linearly continuing the sidewall (ie, extending parallel to the sidewall); being perpendicular to the conveying direction 111 ; and / or being parallel to the gravity direction 105 .

[0119] The second chord 608 b of the blocking angle 608 may satisfy one or more of the following conditions: being tangential to (e.g., not intersecting) the recess wall 602 and contacting a portion of the recess wall 602 that is adjacent to the substrate receiving recess 406 v in the transport direction 111. For example, the portion of the recess wall 602 that contacts the second chord 608 b may be disposed on an edge of the recess wall 602 that faces the sputtering target 404.

[0120] The blocking angle 608 may be less than about 45°, eg, less than about 30°, eg, less than about 20°, eg, less than about 10°.

[0121] Illustratively, the circumferential recess wall 602 acts as a shield including the upper coating opening 416o. It will be appreciated that (e.g., in addition to the substrate holder 406a configured as a shield), a loose shield may also be used, for example, a loose shield may be disposed between the substrate holder 406a and the solar cell precursor 402.

[0122] Figure 7A A solar cell precursor 402 according to various embodiments 700 is illustrated in a schematic top view (processing side), Figure 7B is a schematic cross-sectional view 700b, Figure 7C Detailed view 700c is shown. The interposer 108 formed by sputtering may be, for example, a back-side interposer 108r or a front-side interposer 108v. For example, the interposer 108 may be an amorphous silicon layer (also referred to as an aSi layer).

[0123] As shown, the interposer 108 can be kept at a certain distance from the circumferential edge 510k of the solar cell precursor 402, which is opposite to the passivation surface 101 of the solar cell precursor or facing away from the target. For example, if the edge area of ​​the passivation surface 101 is also blocked, the distance can be greater than about one-quarter of the substrate thickness (the thickness of a conventional silicon solar cell wafer is about 200 μm), such as about 50 μm, such as greater than about 0.1 mm, such as greater than about 0.5 mm, such as greater than about 1 mm. In this way, the precursor sidewall 510 is only partially covered by the interposer 108 or is not covered at all by the interposer 108. In this way, the continuous circumferential portion of the precursor sidewall 510 disposed adjacent to the interposer 108 can be unaffected by the interposer 108.

[0124] Figure 8 The results of work according to various embodiments 800 are illustrated in a schematic diagram, in which the course of the electroactive phosphorus concentration over the layer thickness of a (e.g. polycrystalline) silicon layer formed by sputtering is shown as an exemplary intermediate layer, for example after a high-temperature step of crystallization and doping has been performed. A working example of a high-temperature step is performed in a tube furnace above 800° C. for about 10 minutes. In this regard, reference is made to a coating material. The sputtering target and / or the intermediate layer formed by the sputtering target can consist of or mainly consist of the coating material. The silicon layer can be amorphous (e.g. mostly) immediately after formation and can only be at least partially (e.g. mostly) converted into a polycrystalline silicon layer by a crystallization process (e.g. above 800° C.) (also called crystallization).

[0125] In one exemplary implementation, the doping concentration (also referred to as dopant concentration) of the coating material may be greater than about 7.10 19 at / cm 3 (atoms / cm3), for example, greater than about 1.10 20 at / cm 3 , for example greater than about 3·10 20 at / cm 3 This reduces costs because the interposer does not necessarily need to be doped subsequently, for example, by an additional process step, which involves the aforementioned risk of damaging the interposer during the process. Of course, if desired, the interposer can also be exposed to a gas containing a dopant (e.g., a phosphine, preferably phosphine) and brought to a certain temperature (e.g., 200°C or higher) at which the dopant is introduced into the interposer from the gas (also known as gas phase doping).

[0126] In one exemplary implementation, the dopant of the coating material can be n-type and / or phosphorus. This can reduce costs because the required materials are very common.

[0127] According to various preferred embodiments, the intermediate layer is formed on the passivation surface 101 by PVD (preferably sputtering) without gas-phase doping, so that the dopant (e.g., n-type), preferably consisting of phosphorus, is provided by a solid body, such as a sputtering target. For example, the solid body can be configured as a planar target or a tubular target. It is understood that what is described herein with respect to a single sputtering target is analogously applicable to multiple sputtering targets, for example, if a greater layer thickness is to be achieved.

[0128] For phosphorus and other n-type dopants, the aforementioned doping concentrations are above the solubility limit SG in silicon and can be achieved through crystallization processes (e.g., casting, Czochralski method, etc.). Therefore, sputtering targets can be produced through methods such as powder sintering and / or spraying and / or plasma spraying. This makes it easier to achieve the aforementioned doping concentrations and, of course, can also be applied to other dopants depending on the material system.

[0129] In conventional process technologies, interfering edge wrapping occurs (when one or more circumferential edges are coated with an intermediate layer) because the deposition cannot easily be confined to the wafer side to be coated. In the case of LPCVD, the process gases can also flow between the two wafers standing in the boat within the process pressure range, and the chemical reactions for the silicon layer growth can also take place here. The silicon layer thus grows wherever the process gases can reach, so that the dopant concentration can be adjusted via the process flow of the process gases used. The same applies to the alternative or supplementary use of shielding masks in in-line concepts. Even with APCVD and PECVD technologies, due to the non-directional nature of CVD and conformal layer growth, undesirable layer growth always occurs at and around the wafer edge on the side of the wafer substrate facing away from the coating process.

[0130] For example, the interposer layer can be formed in a vacuum apparatus, such as a horizontally arranged inline vacuum system, for example within its vacuum chamber. Due to the directional growth of the layer, edge wrapping can be suppressed, preferably using a shield. This prevents the doped silicon film from extending around the circumferential sidewalls (and / or two adjacent circumferential edges) of the solar cell precursor and / or from (electrically and / or physically) contacting the side of the solar cell precursor opposite the passivation side.

[0131] The graphs shown show the correlation of electrochemical capacitance voltage (eCV) measurements of different interposers formed according to different embodiments. The thickness of the interposer layer without reactive gas sputtering was 100 nm. The capacitance voltage measurements showed that the electroactive phosphorus content over the layer thickness was greater than 1.10 within the target range. 20 at / cm 3 The total phosphorus content, including non-electroactive phosphorus, was even higher.

[0132] According to various embodiments, a system technique is provided for sputter-depositing sufficiently high in-situ doping (p-type > 1·10 19 at / cm 3 , n type>7·10 19 at / cm 3 The amorphous silicon film is formed entirely on the surface of the substrate to be coated, thus avoiding the formation of short circuits. This means that the required polysilicon layer can be produced in the subsequent annealing step without edge wrapping and the formation of efficiency-reducing electrical shorts. The subsequent additional process step of removing portions of the silicon film is not absolutely necessary.

[0133] In this regard, it should be noted that TOPCon has a relatively thin layer thickness on the front side. For example, the front side interposer 108v may have a thickness less than 60 nanometers, such as in the range of about 4 nanometers to about 20 nanometers.

[0134] Figure 9 A vacuum apparatus according to various embodiments 900 is illustrated in a schematic cross-sectional view, comprising a plurality of vacuum chambers 802 , wherein one or more vacuum chambers 802 (also referred to as process chambers) provide a coating area 401 .

[0135] The processing apparatus may include one or more vacuum chambers 802, and a pumping system P (including at least one rough vacuum pump and optionally at least one high vacuum pump) in an operative state, the pumping system being fluidically coupled to the interior of the vacuum chamber 802 (also referred to as the chamber interior). According to various embodiments, the or each vacuum chamber 802 may include a chamber housing configured to provide a target pressure within the vacuum chamber interior. The target pressure may be in the range of about 10 mbar to about 1 mbar (in other words, a rough vacuum) or less, for example, in the range of about 1 mbar to about 10 mbar. -3 mbar (in other words, a fine vacuum) or less, for example, in the range of about 10 -3 mbar to about 10 -7 The pump system may be arranged to extract gas from the interior of the chamber so that at least a vacuum (ie a pressure of less than 0.3 bar) can be or can be provided therein, for example a target pressure.

[0136] For example, one process chamber or at least one compartment in a process chamber may be provided for each sputtering target 404 that is atomized into the coating region 401 .

[0137] According to various embodiments, a vacuum apparatus may be adapted to perform method 300 as described herein, for example, to coat one or more solar cell precursors, such as one or more silicon wafers (preferably partially processed silicon wafers). Method 300 may provide a portion of a solar cell manufacturing process. Method 300 may be used to form a doped amorphous (or at least partially crystalline) interposer (e.g., a silicon thin film). For example, the solar cell precursor may have one or more sides (also referred to as passivation sides) coated with a passivation dielectric (e.g., a tunneling oxide layer), which is coated by method 300.

[0138] For example, the vacuum apparatus is configured as a sputtering configuration to coat the interposer on one side of the solar cell precursor. Alternatively, however, the solar cell precursor can be coated on both sides, such that the interposer is formed on each of its opposing sides and then the two sides are spaced apart (or non-overlapping).

[0139] Optionally, the vacuum system can have at least one vacuum chamber configured as a lock chamber on the gas inlet side and / or one vacuum chamber configured as a lock chamber on the gas outlet side, with the coating area being arranged between these two vacuum chambers. Optionally, the coating area can be gas-separated, for example, divided into several sections and / or separated from the surrounding environment.

[0140] Alternatively, the vacuum apparatus may be configured as an online system (e.g., with two airlocks), wherein at least one processing chamber is used to coat more than 3,000 solar cell precursors per hour, preferably more than 6,000 solar cell precursors per hour, and more preferably more than 8,000 solar cell precursors per hour, with an amorphous and / or doped intermediary layer (e.g., a silicon thin film). For example, the intermediary layer may be a thin film, i.e., a film thickness between about 5 nm (or less) and about 300 nm (or less). The intermediary layer may be formed without edge coating while in situ doping (in at least one processing chamber) with more than 7.10 19 at / cm 3 of phosphorus.

[0141] In the coating region 401 or downstream of forming the interposer, the solar cell precursor may be heated to a certain temperature (also referred to as a crystallization temperature) in a device separate from the vacuum apparatus to promote an increase in the crystalline content in the interposer (also referred to as a crystallization process or solid-phase crystallization). The crystallization temperature may be greater than about 500°C, for example, about 800°C. The duration of the crystallization process may be greater than 1 minute, thereby converting the amorphous interposer (e.g., a silicon layer) into a polycrystalline interposer (e.g., a polysilicon layer). The crystallization process may selectively promote the diffusion of dopants through the tunnel oxide layer into the base layer.

[0142] For example, the intermediary layer is formed without heating. Alternatively or additionally, the solar cell precursor can be heated before being transported to the coating area and / or after being transported out of the coating area, for example, by heating the solar cell precursor using a heating device 1010 in a corresponding vacuum chamber 802 (also referred to as a heating chamber). For example, heating can reduce the moisture content of the solar cell precursor and / or the substrate carrier.

[0143] The duration of time that the solar cell precursor is in the coating area (also referred to as process duration) can be less than about 5 minutes, such as less than about 1 minute, such as less than about 40 seconds. For example, an interposer can be formed within the process duration.

[0144] Figure 10 A vacuum apparatus according to various embodiments 1000 is illustrated in a schematic cross-sectional view, comprising a plurality of vacuum chambers 802 , wherein one or more of the processing chambers 802 are arranged to perform the process 300 in a sputter-down configuration and / or wherein one or more of the processing chambers 802 are arranged to perform the process 300 in a sputter-up configuration.

[0145] In one exemplary implementation, method 300 can be configured, for example, by a mask, so that when forming an interposer (e.g., a Si thin film), a circumferential edge of the wafer surface (e.g., at least a circumferential portion having at least one circumferential edge or at least one circumferential portion of a sidewall adjacent thereto) is kept free of the interposer. In an upward sputtering configuration, the mask can provide an edge exclusion of approximately 1 mm.

[0146] In an exemplary implementation, the method 300 may be configured as follows to prevent the interposer (e.g., Si thin film) from being deposited on the side 101 (e.g., wafer surface) facing away from the deposition process:

[0147] - through appropriate design of the substrate support and / or

[0148] - by appropriate delivery of the solar cell precursor throughout the coating area and / or

[0149] By suitable arrangement of the solar cell precursor in the coating process (eg Pockettiefe and / or side angles), directional deposition, for example the trajectory of sputtered ballistic particles, is limited.

[0150] In one exemplary implementation, method 300 may be performed in an online PVD system having at least one process chamber for double-sided coating of more than 3,000 solar cell precursors per hour with amorphous silicon thin films (5 nm < thickness < 300 nm) without edge wrapping, while simultaneously in situ doping (in at least one process chamber) with a first dopant of a first polarity on one side of the substrate (e.g., n-doping in at least one process chamber), e.g., n-doping in the range of >7·10 19 at / cm 3 , and doping a second dopant of a second polarity on a second opposite surface of the substrate, the range of which is >1·10 19 at / cm 3 .

[0151] In one exemplary implementation, the method 300 can be configured to shield the edge region of the steam vane to reduce the P and O content in the layer. For example, this can be accomplished by a stationary shield (eg, an orifice device).

[0152] In an exemplary implementation, the process 300 may be configured to provide one or more layer stacks of n-doped layers and undoped Si layers, followed by a homogeneous doping (e.g., >1·10 20 at / cm 3 ).

[0153] In one exemplary implementation, process 300 may be performed in a sputtering system.

[0154] In one exemplary implementation, the interposer is a silicon thin film and / or an amorphous silicon thin film.

[0155] In one exemplary implementation, the interposer layer has a layer thickness d of 5 nm. <d<300nm。

[0156] In one exemplary implementation, the dopant of the interposer is phosphorus.

[0157] In one exemplary implementation, the sputtering target forming the intermediate layer is not produced based on solidification of a doped melt (e.g., a silicon melt), but rather by sintering or spraying powders such as silicon and red phosphorus or silicon and a suitable phosphorus-containing solid, such as silicon phosphide.

[0158] In one exemplary implementation, the thickness of one or more dielectric passivation layers of a solar cell precursor (eg, a tunneling oxide layer) is in a range of about 0.5 nm to about 5 nm, preferably in a range of about 1 nm to about 2.5 nm.

[0159] In one exemplary implementation, the thickness of one or more dielectric passivation layers of the solar cell precursor is preferably a SiOx layer. Alternatively or additionally, one or more dielectric passivation layers have a (e.g., low) carbon and / or nitrogen ratio (e.g., lower than the ratio of the dopant).

[0160] In one exemplary implementation, the doping concentration of the interposer is greater than 1.10 20 at / cm 3 , preferably greater than 3·10 20 at / cm 3 .

[0161] In one exemplary implementation, the solar cell precursor has: a side length greater than 160 mm, a doped (e.g., n- or p-doped) base layer (which may be part of a semiconductor junction). Alternatively or additionally, the solar cell precursor has a wafer size of

[0162] The chip sizes are M2, M4, M6, M10, G10, M12 or G12.

[0163] In one exemplary implementation, the sputtering target has a purity greater than about 4N (based on silicon and dopant). Alternatively or additionally, the sputtering target has a purity greater than about 3N (based on silicon and dopant).

[0164] According to various embodiments, process 300 can perform doping and deposition in a single step without vapor phase doping, thereby avoiding edge wrapping, which is expensive and requires additional waste removal in the process sequence. This saves costs and improves the cost-effectiveness of the process, thereby increasing the efficiency of solar cells, for example, by using TOPCon as a passivation contact.

[0165] Figure 11A In schematic plan view 1100a and cross-sectional view 1100b and Figure 11B A substrate carrier 406 is shown in perspective view according to various embodiments. By appropriately selecting dimensions a, b, c and the two angles d and e, directional deposition can be achieved during the PVD process, thereby achieving target coating without edge wrapping. For example, the two angles d and e can be configured to provide a convex surface that limits the opening. This facilitates shielding. Numerical examples may include:

[0166] - distance from base to recess wall: a = 0.2 to 2 mm, preferably 0.4 mm,

[0167] - difference between Pocket depth and wall height: b = 0.2 to 2 mm, preferably 0.7 mm,

[0168] - Pocket depth: c = 1 to 5 mm, preferably 3 mm

[0169] - side angle of the lower section of the recess wall: d=0.1° to 10°, preferably 5°;

[0170] - Side angle of the upper section of the recess wall: e=10° to 45°, preferably 25°.

[0171] For example, the recess may be designed to accommodate an M6 size substrate (ie, a wafer side length of approximately 166 mm).

[0172] Figure 12 A coating apparatus 1200 according to various embodiments is shown in a schematic side view or cross-sectional view. The coating apparatus 1200 comprises a conveying device (not shown), a sputtering device 1205, and an aperture device 1210 for providing a shield. The conveying device (not shown) is configured to convey a solar cell substrate 1202 along a conveying path 111p in a conveying direction 111.

[0173] Generally speaking, the sputtering device 1205 (also referred to as a magnetron) may include a storage device (not shown) for (e.g., rotatably) storing one or more target materials 1205t. In operation, the sputtering device 1205 also includes one or more targets 1205t, which are supported (e.g., rotatably) by a bearing device. In the case of two targets shown here, the magnetron is also referred to as a dual magnetron. In other words, one or more targets 1205t may or may not be installed. In addition, the sputtering device 1205 may also have a magnet system.

[0174] The orifice device 1210 (e.g., its shield 1212) has an orifice opening 1210o arranged between the conveyor path 111p and the sputtering device 1205 (e.g., its bearing device and / or its magnet system). The orifice opening 1210o (also called a coating window) can expose the conveyor path 111p relative to the sputtering device 1205. The orifice opening 1210o has an extension 1210d (also called a window length) along the conveyor path 111p. The orifice opening 1210o or the window length 1210d can be or be limited by one or more orifices 1210b of the orifice device 1210. The closer the distance between the orifices 1210b, the smaller the orifice opening 1210o or the window length 1210d. The orifice device can be configured in such a way that at least a portion of the coating material ejected in the direction of the conveyor path 111p is retained by the orifice device 1210 at the edge of the coating area. This can reduce oxygen incorporation into the layer formed by the coating material on the solar cell substrate 1202 .

[0175] For example, the velocity of the coating material ejected toward delivery path 111p decreases as angle 1213 increases, or decreases toward the edge of the coating region (above the coating window), resulting in a maximum velocity within the coating region 1215. The lower the velocity, the more reactions and particle collisions with residual gas elements (e.g., N, O, H, and C from air and entrained moisture) in the vacuum chamber occur. More generally, interactions between the coating material and molecular gases (or their ions) are greater near orifice 1210b than within the coating region 1215, resulting in greater incorporation of these elements into the deposited layer if the edges of the coating region were unobstructed.

[0176] For example, less than 30% (e.g., less than 10%) of the atomized coating material may be captured by the orifice device. For example, more than 5% (e.g., more than 25%) of the atomized coating material may be collected by the diaphragm device. For example, under operating conditions (i.e., actual window length = target window length), a proportion of the coating material in the range of about 5% to about 40% (compared to the total sprayed coating material) may be captured by the orifice device.

[0177] The effectiveness of the orifice device 1210 in suppressing the incorporation of elements in the residual gas (e.g., N, O, H, or C) is further improved if the edge of the orifice opening 1210o or the orifice 1210b is arranged as close as possible to the transport path (also referred to as close to the substrate). For example, the orifice 1210b or each orifice 1210b may have a plate that is removably and / or lockably mounted by the frame of the orifice device 1210. The orifice 1210b herein may also be understood as any restriction of the orifice opening 1210o (also referred to as the sputtering window), for example by one or more L-shaped shields and / or by a chamber wall (also referred to as the chamber restriction) of the vacuum chamber 802. The distance between the orifice 1210b and the transport path 111p (also referred to as the substrate plane) may be arranged as small as possible, for example, the higher the process pressure used, the smaller the distance, thereby suppressing the diffusion of stray vapors behind the orifice. For example, the distance between the or each orifice 1210b and the delivery path 111p may be less than about 3 cm (centimetres), such as less than about 1 cm, such as less than about 0.5 cm, such as less than about 0.25 cm.

[0178] According to various embodiments, coating apparatus 1200 may be used to facilitate atomization and coating of aSi:X, or more generally, to facilitate atomization and coating of low-oxygen or oxygen-free (eg, highly reactive) materials.

[0179] Various embodiments related to the above description and illustrations will be introduced below.

[0180] Embodiment 1 is a method for processing a solar cell precursor (e.g., by a vacuum system), the solar cell precursor comprising a dielectric covered (e.g., preferably coated and / or preferably uncoated) by at least one (i.e., one or more) dielectric (preferably at least one oxide (e.g., semiconductor oxide, such as silicon oxide)), preferably comprising a coated and / or passivated face. The method comprises sputtering a sputtering target into a coating region, the sputtering target comprising a semiconductor material and a dopant for the semiconductor material; when sputtering the sputtering target into the coating region, the solar cell precursor (optionally inserted into a substrate carrier) is arranged in the coating region so that the face faces the sputtering target (and / or the dielectric faces the sputtered sputtering target, such as the semiconductor material and the dielectric face the sputtered sputtering target, such as the semiconductor material and the dielectric face the sputtered sputtering target), characterized in that the sputtering target (e.g., the semiconductor material and the dopant therein) is inserted into the coating region. The substrate carrier is preferably further configured such that at least one (i.e., one or more) edges of the solar cell precursor extending along the self-contained path are shielded by the substrate carrier from sputtering of the sputtering target (e.g., such that the substrate carrier remains free from sputtering of the sputtering target (e.g., semiconductor material and its dopant). For example, the surface can be coated with a dielectric by depositing the dielectric and / or forming the dielectric by a chemical reaction (e.g., CVD and / or oxidation).

[0181] Embodiment 2 is a method (e.g., by a vacuum system) for processing a solar cell precursor (e.g., according to embodiment 1), wherein the solar cell precursor comprises a dielectric covered (e.g., preferably coated and / or preferably formed by a chemical reaction) by at least one (i.e., one or more) dielectric (preferably at least one oxide (e.g., semiconductor oxide, such as silicon oxide)), preferably comprising a coated and / or passivated surface. The method comprises sputtering a sputtering target toward one side of the sputtering target, the sputtering target comprising a semiconductor material and a dopant for the semiconductor material; forming a layer on one side by sputtering the sputtering target, the amount ratio of the dopant and the semiconductor material in the layer being smaller than or the same as the amount ratio of the sputtering target; wherein the solar cell precursor is preferably inserted into a substrate carrier, and preferably the substrate carrier is further configured in such a way that an edge of the solar cell precursor extending along a closed path is shielded from sputtering by the substrate carrier.

[0182] Example 3 is a vacuum system (such as the vacuum system of Example 1 or 2) or its use, wherein the vacuum system includes a coating area and a sputtering target, and an optional conveying system, and / or wherein the vacuum system is configured or used to perform the method according to Example 1 or 2.

[0183] Example 4 is a vacuum system according to Example 3, further comprising: a conveying system, through which the solar cell precursor is placed, preferably the solar cell precursor is conveyed along a conveying path inside the vacuum system by the conveying system.

[0184] Embodiment 5 is a vacuum system according to embodiment 3 or 4, wherein the conveying system includes, for example, a substrate carrier, and / or the conveying system is configured to convey the solar cell precursor (preferably inserted into the substrate carrier) in the coating area when sputtering of the sputtering target occurs to the coating area, preferably so that the surface of the solar cell precursor coated with at least one dielectric faces the sputtering target, wherein preferably the substrate carrier is also configured so that the edge of the solar cell precursor extending along the closed path is shielded from sputtering of the sputtering target by the substrate carrier.

[0185] Embodiment 6 is a vacuum system according to any one of embodiments 3 to 5, further comprising: a first vacuum chamber, in which the coating area is arranged; and a second vacuum chamber, adjacent to the first vacuum chamber (for example, upstream or downstream thereof), wherein when the solar cell precursor is transported through the first vacuum chamber and the second vacuum chamber along the transport path, the second vacuum chamber on each transport path has a heating power greater than that of the first vacuum chamber.

[0186] Embodiment 7 is a vacuum system according to any one of embodiments 3 to 6, further comprising: one or more vacuum chambers (for example, a first vacuum chamber and / or a second vacuum chamber), wherein the coating area is disposed in the vacuum chamber.

[0187] Embodiment 8 is the vacuum system according to any one of embodiments 3 to 7, further comprising: a sputtering device with a sputtering target, wherein, for example, the sputtering device is configured to atomize the sputtering target into the coating region.

[0188] Embodiment 9 is a vacuum system according to any one of embodiments 3 to 8, further comprising: wherein the sputtering target comprises a semiconductor material, and / or wherein the sputtering target comprises a dopant of the semiconductor material, the content of the dopant being greater than the solubility limit SG of the dopant in the semiconductor material, and / or greater than a material content fraction of the dopant of 0.15%.

[0189] Embodiment 10 is a vacuum system according to any one of embodiments 3 to 9, further comprising: a coating device adapted to form a dielectric on the solar cell precursor side in an additional coating region provided in one or more vacuum chambers upstream of the coating region.

[0190] Embodiment 11 is a vacuum system according to any one of embodiments 3 to 10, wherein the target state of the vacuum system during operation (for example, the vacuum system is operated according to the target state) is configured so that when the solar cell precursor is set in or becomes in the coating area, preferably when it reaches the coating area, the temperature of the solar cell precursor is less than about 200°C, preferably less than about 100°C, and / or less than the temperature of the sputtering target.

[0191] Embodiment 12 is a vacuum system according to any one of embodiments 3 to 11, further comprising: a gas transfer device adapted to supply and / or extract a gas component to the coating region (e.g., via a quick connector); wherein the gas transfer device preferably comprises a quick connector, a pump, and / or a gas source (e.g., comprising a gas component) (e.g., exposed to a gas cost). For example, the gas component: comprises an inert gas, or preferably consists of an inert gas, preferably a noble gas; and / or comprises a dopant in a smaller mass fraction than the sputtering target, preferably substantially free of dopants; and / or comprises a smaller mass fraction of hydrogen than the coating region, preferably substantially free of hydrogen. The quick connector reflects that such a gas component can be used (e.g., without danger). However, if the gas component is relatively hazardous (e.g., contains hydrogen and / or dopants), the quick connector is omitted.

[0192] Embodiment 13 is a vacuum system according to embodiment 12, further comprising: single-walled tubing through which the coating region is connected to the gas transfer device; and / or additional quick-connect fittings through which the coating region is connected to the gas transfer device. The single-walled tubing reflects the ability to use non-hazardous gas compositions. If the gas composition is hazardous (e.g., containing hydrogen and / or dopants), the tubing is at least double-walled. The quick-connect fitting reflects the ability to use such gas compositions (e.g., non-hazardous). If the gas composition is hazardous (e.g., containing hydrogen and / or dopants), the quick-connect fitting is omitted.

[0193] Example 14 is arranged according to any one of Examples 1 to 13, wherein the temperature of the solar cell precursor when it is located in the coating area and / or sputtering the sputtering target into the coating area is less than about 200°C, preferably less than about 100°C, and / or less than the temperature of the sputtering target.

[0194] Embodiment 15 is configured according to one of embodiments 1 to 14, wherein sputtering of the sputtering target into the coating area occurs when the solar cell precursor is arranged in the coating area and / or transported into the coating area and / or transported out of the coating area.

[0195] Embodiment 16 is arranged according to one of embodiments 1 to 15, wherein the solar cell precursor includes: a first (continuous) circumferential edge (e.g., adjacent to the face), a second (continuous) circumferential edge (e.g., opposite to the face or at least spaced apart from the face), and / or a (continuous) circumferential side wall adjacent to (e.g., disposed between) the first edge and / or the second edge, wherein at least one edge has a first circumferential edge and / or a second circumferential edge.

[0196] Embodiment 17 is arranged according to one of embodiments 1 to 16, wherein at least one edge is adjacent to or at a distance from at least one dielectric.

[0197] Embodiment 18 is according to any one of embodiments 1 to 17, wherein the sputtering target comprises a dopant content (eg, a ratio of the amount of dopant to the semiconductor material) greater than the solubility limit of the dopant in the semiconductor material.

[0198] Example 19 is configured according to one of Examples 1 to 18, wherein the sputtering target contains a dopant content greater than a dopant ratio (e.g., material content ratio and / or mass ratio) of 0.15% (e.g., based on a mixture of the dopant and the semiconductor material and / or based on the mass of the sputtering target), e.g., 0.15 wt% or 0.15 at%.

[0199] Embodiment 20 is configured according to one of embodiments 1 to 19, wherein the substrate carrier has a shield, by which the edges are shielded and / or by which the sputtering target is atomized (e.g., towards a solar cell precursor). wherein the shield is provided, for example, by a substrate holder of the substrate carrier, on which the solar cell precursor is located, or the shield comprises, for example, an opening, into which the solar cell precursor is inserted; wherein the shield is provided, for example, by a wall forming a recess (e.g., a substrate receiving recess) in the substrate carrier, into which the solar cell precursor is inserted; and / or wherein the shield has an opening, through which the sputtering target is atomized (e.g., towards the solar cell precursor).

[0200] Example 21 is configured according to one of Examples 1 to 20, wherein the substrate carrier (e.g., its shield) has an opening that exposes the solar cell precursor relative to the sputtering target, wherein the opening is formed, for example, by a circumferential edge of the substrate carrier (e.g., a side wall around the opening) and / or (e.g., surrounding) a convex surface of the substrate carrier (e.g., a circumferential surface of the substrate carrier); and / or wherein the shield (e.g., its edge) is configured in such a way that at least one edge of the solar cell precursor adjacent to the at least one edge is shielded, and its edge width is greater than 0.1 mm (e.g., greater than 1 mm).

[0201] Example 22 is arranged according to one of Examples 1 to 21, wherein the edge faces away from the sputtering target.

[0202] Embodiment 23 is configured according to any one of embodiments 1 to 22, further comprising: forming a layer (e.g., an intermediate layer) by sputtering a sputtering target onto a solar cell precursor, the layer preferably having a smaller or the same quantitative ratio of dopant to semiconductor material than the sputtering target.

[0203] Example 24 is configured according to Example 23, wherein the layer is at least partially (i.e., partially or completely) amorphous and / or has a sheet resistance (e.g., based on a 100 nm layer thickness) of at least about 1000 ohms (e.g., immediately after the layer is formed), e.g., at least about 2000 ohms.

[0204] Example 25 is configured according to Example 23 or 24, wherein the layer is at least partially (i.e., partially or completely) polycrystalline and / or has a sheet resistance (e.g., based on a layer thickness of 100 nanometers) of less than about 1000 ohms (e.g., after it is stimulated to crystallize, e.g., by a crystallization process and / or by heating the layer), e.g., less than about 200 ohms.

[0205] Embodiment 26 is according to any one of embodiments 23 to 25, wherein the content of the dopant in the layer (e.g., the ratio of the amount of dopant to the semiconductor material) is greater than: the solubility limit of the dopant in the semiconductor material; and / or 0.15% (e.g., at% or wt%).

[0206] Embodiment 27 is according to any one of embodiments 23 to 26, wherein the concentration of the dopant in the layer is greater than about 7·10 19 at / cm 3 , preferably greater than about 1·10 20 at / cm 3 .

[0207] Embodiment 28 is according to any one of embodiments 23 to 27, wherein the layer comprises semiconductor material and / or is doped with a dopant, for example the same doping type as the substrate of the solar cell precursor (when the surface is the back side of the solar cell precursor) or opposite to the doping type of the substrate of the solar cell precursor (when the surface is the front side of the solar cell precursor).

[0208] Embodiment 29 is configured according to any one of embodiments 23 to 28, further comprising: heating the layer, preferably after ejecting the solar cell precursor from the vacuum, for example, so that the crystalline portion of the layer increases (for example, so that solid phase crystallization occurs); and / or for example, so that the dopant in the dielectric absorption layer is doped (for example, by the dopant in the layer), for example, by the dopant of the layer; and / or for example, so that the layer forms a passivating contact with the underlying dielectric (for example, SiOx).

[0209] Embodiment 30 is arranged according to one of embodiments 23 to 29, wherein the layer includes or is formed from (eg, amorphous) silicon.

[0210] Embodiment 31 is according to any one of embodiments 1 to 30, wherein the solar cell precursor: is heated (preferably in a vacuum) before being transported to the coating area; and / or releases more thermal power than it absorbs (preferably in a vacuum) when being transported to the coating area (for example, such that the temperature of the solar cell precursor is reduced).

[0211] Embodiment 32 is arranged according to any one of embodiments 1 to 31, wherein the coating area includes a vacuum.

[0212] Embodiment 33 is configured according to one of embodiments 1 to 32, wherein the solar cell precursor is arranged in the coating region in such a way that a face of the solar cell precursor and / or the dielectric faces the sputtering target.

[0213] Embodiment 34 is configured according to one of embodiments 1 to 33, wherein the face is the front side of a solar cell precursor or the back side of a solar cell precursor, wherein the front side and the back side are preferably opposite to each other.

[0214] Example 35 is arranged according to one of Examples 1 to 34, wherein the solar cell precursor includes a base layer (e.g., a wafer) and / or and an emitter (e.g., an emitter layer), wherein the emitter is, for example, arranged on the surface or facing or facing away from the sputtering target (e.g., relative to the base layer); wherein the emitter and the base layer, for example, form a semiconductor junction.

[0215] Embodiment 36 is arranged according to one of embodiments 1 to 35, wherein at least one dielectric is in contact with the base layer or the emitter.

[0216] Embodiment 37 is according to any one of embodiments 1 to 36, further comprising heating the solar cell as it is transported out of the coating area so that the temperature of the solar cell precursor increases.

[0217] Embodiment 38 is according to any one of embodiments 1 to 37, wherein sputtering the sputtering target is performed by forming a plasma between the sputtering target and the solar cell precursor.

[0218] Embodiment 39 is according to any one of embodiments 1 to 38, wherein the solar cell precursor in the coating region is exposed to a chemical composition having a lower ratio of dopant to semiconductor material than or the same ratio as the sputtering target; and / or the chemical composition having fewer hydrogen atoms than dopant atoms, preferably being essentially free of hydrogen.

[0219] Embodiment 40 is arranged according to any one of embodiments 1 to 39, wherein at least one dielectric comprises a semiconductor material, such as an oxide thereof (eg, SiOx).

[0220] Embodiment 41 is according to any one of embodiments 1 to 40, wherein the at least one dielectric has a thickness less than about 5 nanometers, such as less than about 2 nanometers, and / or a thickness of 1.5 nanometers.

[0221] Example 42 is configured according to one of Examples 1 to 41, wherein one side (e.g., the side facing the sputtering target) of the solar cell precursor (e.g., the back side or the front side) is coated (e.g., passivated) with a dielectric layer (preferably at least one dielectric) having a thickness of less than 5 nanometers, preferably less than 2.5 nanometers.

[0222] Example 43 is arranged according to one of Examples 1 to 42, wherein the arrangement of the solar cell precursor in the coating area is carried out by a conveying system, which comprises a substrate carrier, the solar cell precursor and preferably a plurality (for example, more than 10, more than 50 or more than 100) additional solar cell precursors are inserted into the substrate carrier.

[0223] Example 44 is arranged according to any one of Examples 1 to 43, wherein the substrate carrier preferably includes a substrate holder (e.g., providing a shield), which has a through hole arranged between the solar cell precursor and the sputtering target when the solar cell precursor is arranged in the coating area.

[0224] Embodiment 45 is arranged according to any one of embodiments 1 to 44, wherein the doping concentration of the sputtering target is greater than 7·10 19 at / cm 3 , preferably greater than 2.35·10 20 at / cm 3 , more preferably greater than 1·10 21 at / cm 3 .

[0225] Embodiment 46 is configured according to one of embodiments 1 to 45, wherein the sputtering target is monolithic and / or the sputtering target is supported by a support tube extending through the sputtering target.

[0226] Example 47 is arranged according to one of Examples 1 to 46, wherein the sputtering target is injection molded or sintered, and / or the sputtering target is produced by an injection molding process or a sintering process.

[0227] Embodiment 48 is arranged according to any one of embodiments 1 to 47, wherein the semiconductor material purity of the sputtering target is greater than 99.9 at % (3N), preferably greater than 99.99 at % (4N), for example, when subtracting dopants. For example, the fraction (e.g., mass fraction and / or material content fraction) of the sum of the semiconductor material and the dopant can be greater than 99.9% of the sputtering target, for example, greater than 99.99% of the sputtering target (the remainder (e.g., excluding Si and P) can be, for example, less than 0.1% or 0.01%).

[0228] Embodiment 49 is arranged according to any one of embodiments 1 to 48, wherein the semiconductor material purity of the chemical composition of the sputtering target is greater than 99.999 at % (5N), preferably greater than 99.9999 at % (6N) when the dopant is subtracted.

[0229] Embodiment 50 is arranged according to any one of embodiments 1 to 49, wherein the semiconductor material includes or is silicon.

[0230] Embodiment 51 is according to any one of embodiments 1 to 50, wherein the dopant comprises or is phosphorus; and / or the dopant comprises or is arsenic.

[0231] Example 52 is arranged according to one of Examples 1 to 51, wherein a through hole (also called an orifice) of an orifice device (for example, arranged stationary relative to the target material) is arranged between the coating area and the sputtering target material, and the orifice is coated by sputtering of the sputtering target material, thereby, for example, shielding an edge portion of the sputtered material, which edge portion can interact more strongly with the ambient atmosphere (for example, preventing the shielded material from reaching the coating area).

[0232] Embodiment 53 is arranged according to any one of embodiments 1 to 52, wherein the coating area is arranged in one or more vacuum chambers (eg, the vacuum chambers form or are part of a common vacuum system).

[0233] Embodiment 54 is according to any one of embodiments 1 to 53, further comprising forming at least one dielectric, preferably within a vacuum system and / or preferably by physical vapor deposition.

[0234] Example 55 is arranged according to any one of Examples 1 to 54, wherein when (e.g., only if) the solar cell precursor is arranged in the coating area, at least one edge of the solar cell precursor is substantially not coated (by the sputtering target and / or by the semiconductor material of the sputtering target).

[0235] Example 56 is arranged according to any one of Examples 1 to 55, further comprising: forming an additional dielectric (e.g., SiN) on the solar cell precursor (preferably by sputtering a sputtering target onto the layer, e.g., when the surface is the back side), preferably in a vacuum system, after the solar cell precursor is brought out of the coating area, wherein the formation of the additional dielectric is preferably performed by chemical reaction and / or physical vapor deposition, preferably by reactive physical vapor deposition.

[0236] Example 57 is configured according to one of Examples 1 to 56, further comprising: additional coating of the front side of the solar cell precursor, preferably in a vacuum system, wherein the front side is, for example, a face or a face opposite to a face (e.g., a back face), wherein the coating of the face is preferably performed by physical vapor deposition and / or outside the coating area (e.g., in an additional coating area).

[0237] Embodiment 58 is configured according to embodiment 57, wherein the additional coating of the front surface further comprises: forming a layer on the front surface, the layer comprising a semiconductor material and / or being doped, preferably with a doping type of opposite polarity to the dopant on the back surface. For example, the front surface can be coated with SiOx and another aSi with opposite polarity doping, such that the back surface is n-doped and the front surface is p-doped (or vice versa). SiOx can optionally be omitted.

[0238] Embodiment 59 is configured according to embodiment 58, wherein additional coating of the front side is performed by an additional sputtering target and / or in a vacuum system. For example, the front side can be or be coated with aSi, for example as an alternative to or in addition to the back side coating.

[0239] Embodiment 60 is arranged according to one of embodiments 1 to 59, wherein when the solar cell precursor is arranged in the coating region, a side surface of the solar cell precursor extending along the edge is substantially not coated.

[0240] Example 61 is arranged according to any one of Examples 1 to 60, wherein when sputtering of the sputtering target occurs, a gas component is supplied to the coating area and / or a gas component is removed from the coating area, wherein the gas component: includes an inert gas or is formed by an inert gas, preferably a rare gas; and / or includes a smaller amount of dopant material than the sputtering target, preferably is essentially free of dopants; and / or includes a smaller amount of hydrogen material than the coating area, preferably is essentially free of hydrogen.

[0241] Example 62 is arranged according to any one of Examples 1 to 61, wherein the solar cell precursor includes: an emitter layer and a collector layer (e.g., a base layer) that form a semiconductor junction (e.g., a pn junction); wherein the solar cell precursor preferably includes at least one dielectric (e.g., forming a dielectric layer) between the semiconductor layer (e.g., dopant and / or amorphous) formed by sputtering a target material and the collector layer.

[0242] Embodiment 63 is arranged according to one of embodiments 1 to 62, wherein a doped polycrystalline semiconductor layer is formed on a side (eg, back side or front side) of a solar cell precursor by sputtering a target and subsequent annealing.

[0243] Embodiment 64 is configured according to any one of embodiments 1 to 63, wherein the thickness of the layer formed by sputtering the sputtering target is greater than 60 nanometers (e.g., in the range of about 60 nanometers to about 100 nanometers) or less than 60 nanometers (e.g., in the range of about 4 nanometers to about 20 nanometers), for example, wherein when the thickness of the layer formed by sputtering the sputtering target is greater than 60 nm (e.g., in the range of about 60 nm to about 100 nm) or less than 60 nm (e.g., in the range of about 4 nm to about 20 nm), the solar cell precursor is formed by a coating area (e.g., by a sputtered sputtering target) (e.g., after coating the sputtering target).

[0244] Embodiment 65 is configured according to any one of embodiments 1 to 64, wherein sputtering of the sputtering target is performed so that the amount (e.g., density) of the grain boundaries of the layer formed thereby (e.g., an intermediate layer) is less than the amount of grain boundaries based on a CVD process (e.g., LPCVD, PECVD) because, for example, the sputtering of the sputtering target is two to ten times smaller than the grain diameter of the polysilicon layer of LPCVD, PECVD; and / or the grain boundary density of the layer formed thereby is greater than that of one or more layers adjacent to the formed layer (e.g., having a dielectric and / or having a different dielectric).

[0245] Embodiment 66 is arranged according to any one of embodiments 1 to 65, wherein the sputtering target includes a certain amount of the semiconductor material dopant in an activated form. For example, the activated dopant amount can be greater than the solubility limit of the dopant in the semiconductor material and / or greater than the material content fraction of the dopant of 0.15 at%.

[0246] Embodiment 67 is configured according to one of Embodiments 1 to 66, wherein the content SM of the dopant and the solubility limit SG of the dopant in the semiconductor material satisfy the following relationship: SM>k·SG, wherein k>1, preferably k>1.1 or k>1.2 or k>1.3, further preferably k>1.4 or k>1.5 or k>1.6, further preferably k>1.7 or k>1.8 or k>1.9, further preferably k>3 or k>5 or k>8. The solubility limit SG may be 10 20 at / cm 3 or lower.

[0247] Example 68 is arranged according to one of Examples 1 to 67, wherein a diaphragm device is arranged between the coating area and the sputtering target material, the diaphragm device having a diaphragm opening (for example, the sputtering target material is sputtered into the coating area through the diaphragm opening), wherein preferably the diaphragm device is arranged to shield the coating area and / or the solar cell precursor from sputtering of the sputtering target material, wherein preferably the diaphragm device is arranged to be coated by sputtering of the sputtering target material.

[0248] Embodiment 69 is arranged according to embodiment 68, wherein the orifice device is arranged to coat the sputtering target with a first material flow (e.g., originating from the sputtering target) by atomizing the sputtering target, wherein a second material flow is provided into the coating region by atomizing the sputtering target, wherein the first material flow is X% of the second material flow, wherein X is greater than 5% (or 10%), such as about 15% (or 25%), such as about 15% (or 25%), and / or less than about 50% (or 30%), such as about 20% (or 10%). For example, the first material flow and the second material flow can be mass flows (mass per time).

[0249] Example 70 is arranged according to any one of Examples 1 to 69, wherein greater than about 5% (or 10%), for example greater than about 15% (or 25%), of the material flow produced by sputtering of the sputtering target is captured (for example before it reaches the coating area and / or solar cell precursor), for example by an orifice device and / or a substrate carrier (and then arranged to be so).

[0250] Example 71 is arranged according to any one of Examples 1 to 70, wherein less than about 50% (or 30%), for example less than about 20% (or 10%), of the material flow generated by sputtering of the sputtering target is captured (for example before it reaches the coating area and / or solar cell precursor), for example by an orifice device and / or a substrate carrier (and then arranged to be so).

[0251] In another example, a system is provided for use in a method of manufacturing a solar cell having at least one so-called passivating contact, the method comprising: sputtering a sputtering target into a coating region, wherein the sputtering target comprises a semiconductor material and an n-type dopant of the semiconductor material in a concentration greater than 7·10 19 at / cm 3 , preferably greater than 2.35·10 20 at / cm 3 (for example, it can be about 0.5 wt% P in Si); when the sputtering target is atomized into the coating area, the solar cell precursor is arranged in the coating area with the side (or multiple sides) to be coated facing the sputtering target; the system may optionally have the following characteristics: coating more than 3,000 substrates with a side length greater than 180 mm per hour, preferably more than 6,000 substrates per hour; and when the solar cell precursor is located in the coating area, the vertical edges of the solar cell precursor and / or the side surfaces of the solar cell precursor around the back are basically not coated.

[0252] The system prevents electrical short circuits or increased reverse current in finished solar cells.

[0253] Furthermore, in the additional illustrative examples:

[0254] -n dopant is preferably phosphorus or arsenic;

[0255] - the thickness of the aSi layer is preferably between 5 nm and 200 nm;

[0256] - preferably the process is carried out without the use of additional heating elements during the sputtering process, i.e. the substrate is fed at room temperature and is not heated during the coating process;

[0257] - In an in-line process, the cycle time for depositing the desired layer is preferably less than 45 seconds;

[0258] - Preferably there is a chamber for double-sided coating of aSi by simultaneous sputtering from the front side (eg n-doped) and the back side (eg p-doped), which also improves the coating properties.

[0259] Example 72 is configured according to one of Examples 1 to 71, wherein the substrate carrier is configured in such a way that an edge of the solar cell precursor (e.g., extending along a closed path) is at least partially (i.e., partially or completely) shielded from sputtering of the sputtering target by the substrate carrier, and the dielectric of the solar cell precursor is exposed along the edge.

[0260] Example 73 is arranged according to any one of Examples 1 to 72, wherein a sputtering target comprising a semiconductor material and a semiconductor material dopant is prefabricated and / or installed near the coating area, and the content of the dopant is greater than the solubility limit of the dopant in the semiconductor material and / or greater than the material content fraction of the dopant of 0.15at%.

[0261] Example 74 is arranged according to any one of Examples 1 to 73, wherein the sputtering target material includes a (e.g., homogeneous) mixture of a semiconductor material and a semiconductor material dopant, the mixture including a dopant content greater than the solubility limit of the dopant in the semiconductor material and / or less than a material content fraction of the dopant of 0.15 at %.

[0262] Embodiment 75 is configured according to any one of embodiments 1 to 74, wherein a portion of the sputtering target includes a dopant, the content of the dopant being greater than the solubility limit of the dopant in the semiconductor material and / or greater than the material content fraction of the dopant of 0.15 at %.

[0263] If the dopant content is greater than the solubility limit of the dopant in the portion and / or greater than the material content fraction of 0.15 at % of the dopant in the portion, the dopant has an extension into the coating area greater than about 1 (or 5) mm, for example greater than 1 cm, for example greater than 5 cm.

[0264] Embodiment 76 is arranged according to any one of embodiments 1 to 75, wherein the chemical ratio of the dopant to the semiconductor material of the sputtering target is greater than the solubility limit of the dopant in the semiconductor material and / or greater than the material content fraction of the dopant 0.15 at %.

[0265] Embodiment 77 is configured according to one of embodiments 1 to 76, wherein the chemical composition of the sputtering target is unchanged when the sputtering target is sputtered onto the coating area.

[0266] Embodiment 78 is according to any one of embodiments 1 to 77, wherein the sputtering of the sputtering target includes the sputtering target ejecting more dopant than absorbed dopant.

[0267] Embodiment 79 is according to any one of embodiments 1 to 78, wherein the sputtering target comprises a semiconductor material and a dopant for the semiconductor material, and before sputtering begins, after sputtering ends, and / or when the coating area is evacuated to a negative pressure (e.g., vacuum, e.g., high vacuum), the content of the dopant is greater than the solubility limit of the dopant in the semiconductor material and / or greater than the material content fraction of the dopant of 0.15 at%.

Claims

1. A vacuum system comprising - one or more vacuum chambers, in which the coating area is arranged; a sputtering device having a storage device for storing one or more sputtering targets (404) and being adapted to sputter the sputtering targets (404) into a coating region; - wherein the sputtering target (404) comprises a semiconductor material, and the sputtering target (404) further comprises a dopant of the semiconductor material, wherein the content of the dopant is greater than 0.15 at% of the material content of the dopant; a transport system having a substrate carrier and being configured to transport a solar cell precursor (402), the solar cell precursor (402) inserted into the substrate carrier being arranged in the coating area (401) when sputtering of the sputtering target (404) into the coating area (401) occurs; - wherein the substrate carrier is configured in such a way that the edges (510k, 512k) of the solar cell precursor (402) extending along a closed path are shielded from sputtering with respect to the sputtering target (404) by the substrate carrier.

2. The vacuum system according to claim 1, wherein the substrate carrier comprises a shield, by which the edge is shielded and / or by which the sputtering target is atomized.

3. The vacuum system according to claim 1 or 2, wherein: The substrate carrier has an opening that exposes the solar cell precursor to the sputtering target, the opening being defined by a convex surface of the substrate carrier.

4. The vacuum system according to claim 1 or 2, wherein: The target state of the vacuum system during operation is set so that when the solar cell precursor (402) is inserted into the coating area (401), the temperature of the solar cell precursor (402) is lower than about 200°C and / or lower than the temperature of the sputtering target (404).

5. The vacuum system according to claim 1 or 2, further comprising a gas transfer device comprising a quick connector, the gas transfer device being adapted to supply and / or extract a gas component to the coating area via the quick connector; - a single-walled conduit, through which the coated area is coupled to the gas transfer device.

6. The vacuum system according to claim 1, wherein when sputtering of the sputtering target (404) into the coating area (401) occurs, the solar cell precursor (402) is arranged in the coating area (401) so that the side of the solar cell precursor coated with at least one dielectric faces the sputtering target (404).

7. The vacuum system of claim 4, wherein the temperature of the solar cell precursor (402) is less than about 100°C when the solar cell precursor (402) is inserted into the coating area (401).

8. The vacuum system according to claim 1 or 2, wherein the sputtering device is configured to: - forming a layer (108) on the solar cell precursor (402) by sputtering the sputtering target (404), wherein the amount ratio of the dopant to the semiconductor material of the layer (108) is smaller than that of the sputtering target (404) or is the same as that of the sputtering target (404).

9. The vacuum system according to claim 8, wherein: The layer (108) is at least partially amorphous and / or has a sheet resistance of at least 1000 ohms.

10. The vacuum system according to claim 1 or 2, wherein: When the solar cell precursor (402) is arranged in the coating area (401), the substrate carrier is configured such that the edges (510k, 512k) of the solar cell precursor (402) are substantially uncoated.

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