Double data rate memory system, memory and electronic equipment
By using the chip core power supply VCC as the termination option for the address signal line in the DDR memory system and connecting a pull-up termination resistor, the signal open circuit problem caused by the inability to lay the IOVDD power supply for the address signal line of the DDR memory particle is solved, and the signal quality is improved. It is suitable for DDR1, DDR2, DDR3 or DDR4 systems.
Patent Information
- Application Number
- CN202422836243.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-09-26
- Estimated Expiration
- 2034-11-20
AI Technical Summary
The address signal lines of the DDR memory particles cannot be laid with the IOVDD power supply on the circuit board, resulting in an open signal circuit, forming echo oscillation, affecting the signal quality, causing the DDR particle receiving end to fail to meet the standards and affecting normal operation.
The chip core power supply VCC is used as the termination option for the DDR address signal line, and the address signal line is connected through a pull-up termination resistor, which solves the problem that the IOVDD power supply cannot be laid around the resistor row, ensuring that the signal quality meets the standard.
It effectively solves the problem of signal quality deterioration caused by open circuit of address signals in DDR memory systems, ensuring the normal operation of the memory system. It is suitable for DDR1, DDR2, DDR3 or DDR4 systems.
Smart Images
Figure CN223390275U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of circuit board system design, and in particular to a double data rate memory system, a memory, and an electronic device. Background Art
[0002] In related technologies, the address signal lines of DDR (Double Data Rate) memory chips are generally set on the circuit board. To save PCB costs, fewer stacking layers are used to design DDR routing and other power planes, resulting in the inability to lay IOVDD power around the resistor array. The address signal lines are open-circuited at the memory chip end, which easily forms echo oscillations, seriously affecting signal quality, causing the DDR chip receiving end to not meet the standards and affecting normal operation.
[0003] The above statements are only used to provide background information related to the present application and do not necessarily constitute prior art. Summary of the Invention
[0004] The present application is directed to a double data rate memory system, memory, and electronic device. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is provided below. This summary is not intended to be a comprehensive review, identify key or important components, or delineate the scope of protection for these embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the detailed description that follows.
[0005] According to one aspect of an embodiment of the present application, a double data rate memory system is provided, comprising a memory driving circuit, a pull-up termination resistor, an address signal line, and a plurality of memory chips;
[0006] The memory driving circuit and the memory particles are both connected to the address signal line;
[0007] A first end of the pull-up termination resistor is connected to the address signal line, and a second end of the pull-up termination resistor is connected to a chip core power supply.
[0008] In some embodiments of the present application, the system further includes a first driving resistor and a second driving resistor, the memory driving circuit is connected to the input and output power supply through the first driving resistor, and the memory driving circuit is grounded through the second driving resistor.
[0009] In some embodiments of the present application, the system further includes a circuit board, and the memory driving circuit, the first driving resistor, the second driving resistor, the pull-up termination resistor, the address signal line, and the plurality of memory particles are all arranged on the circuit board.
[0010] In some embodiments of the present application, the plurality of memory particles include 8 memory particles.
[0011] In some embodiments of the present application, the memory particle includes a storage array and a row and column decoder and a data register respectively connected to the storage array, the storage array includes a plurality of storage cells arranged in an array form; the row and column decoder is used to locate the target storage cell in the storage array according to the input address, and the data register is used to cache the data in the storage array.
[0012] In some embodiments of the present application, the memory cell includes a transistor.
[0013] According to another aspect of an embodiment of the present application, a memory is provided, comprising the double data rate memory system described in any embodiment of the present application.
[0014] According to another aspect of the embodiments of the present application, an electronic device is provided, comprising the memory described in any embodiment of the present application.
[0015] One aspect of the technical solution provided by the embodiments of the present application may have the following beneficial effects:
[0016] The double data rate memory system provided in an embodiment of the present application includes a memory driver circuit, a pull-up termination resistor, an address signal line, and multiple memory chips. The memory driver circuit and the memory chips are both connected to the address signal line. The first end of the pull-up termination resistor is connected to the address signal line, and the second end of the pull-up termination resistor is connected to the chip core power supply VCC. The chip core power supply VCC is used as the termination option for the DDR address signal line, thereby solving the problem in the related art that the IOVDD power supply cannot be laid around the resistor array, causing the address signal of the memory chip to be open-circuited, thereby seriously deteriorating the signal quality.
[0017] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1FIG. 4 shows a schematic diagram of a circuit structure of a memory system in related art.
[0020] Figure 2 The figure shows a waveform diagram obtained at the memory particle end of a memory system in the related art.
[0021] Figure 3 A schematic diagram of the circuit structure of a double data rate system according to an embodiment of the present application is shown.
[0022] Figure 4 An equivalent circuit diagram showing the change of an address signal line from 0 to 1 in a memory system according to an embodiment of the present application is shown.
[0023] Figure 5 An equivalent circuit diagram showing the change of an address signal line from 1 to 0 in a memory system according to an embodiment of the present application is shown.
[0024] Figure 6 The figure shows a waveform diagram obtained at the memory chip end when the address signal line in the memory system of one embodiment of the present application is terminated to the core power supply. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solutions and advantages of this application more clearly understood, this application is further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0026] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art, and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.
[0027] refer to Figure 1As shown, the memory system in the related art includes a circuit board 6, an address signal line 3 and 8 memory particles. The address signal line 3 and the 8 memory particles are all arranged on the circuit board 6. The 8 memory particles are all connected to the address signal line 3. The 8 memory particles are marked as 11-18 respectively. In order to save PCB costs, in some cases, fewer stacking layers are used to design DDR routing and other power planes, resulting in the inability to lay IOVDD power around the resistor array, causing the address signal of the memory particle to be open, easily forming echo oscillation, seriously affecting the signal quality, causing the DDR particle receiving end to not meet the standard, affecting normal operation. Reference Figure 2 As shown, in the related art, when the address signal line of the memory system is open, the "eye" in the waveform diagram obtained at the memory particle end is closed, and the memory cannot work normally.
[0028] In response to the problems existing in the related art, an embodiment of the present application provides a double data rate system, including a memory driving circuit, a pull-up termination resistor, an address signal line, and multiple memory chips. The memory driving circuit and the memory chips are both connected to the address signal line, the first end of the pull-up termination resistor is connected to the address signal line, and the second end of the pull-up termination resistor is connected to the chip core power supply VCC. The chip core power supply VCC is used as the termination option for the DDR address signal line, thereby solving the problem in the related art that the IOVDD power supply cannot be laid around the resistor array, causing the address signal of the memory chip to be open, thereby causing serious deterioration of the signal quality.
[0029] A double data rate system proposed according to an embodiment of the present application is described below with reference to the accompanying drawings.
[0030] refer to Figure 3 As shown, an embodiment of the present application provides a double data rate system, including a memory driving circuit 1, a pull-up termination resistor 2, an address signal line 3, and a plurality of memory particles; the memory driving circuit 1 and the memory particles are both connected to the address signal line 3; the first end of the pull-up termination resistor 2 is connected to the address signal line 3, and the second end of the pull-up termination resistor 2 is connected to the chip core power supply VCC.
[0031] This embodiment of the DDR system utilizes the chip's core power supply (VCC) as the termination option for the DDR address signal lines, thus resolving the problem in related technologies where the inability to route the IOVDD power supply around the resistor array results in an open circuit for the memory chip's address signals, severely degrading signal quality. This DDR system is suitable for all memory systems that utilize memory chips where on-die termination of the address signals is not possible, including systems using DDR1, DDR2, DDR3, and DDR4.
[0032] Figure 3In the example shown, eight memory cells are included. The eight memory cells are all connected to the address signal line 3 , and the eight memory cells are marked as 11 - 18 .
[0033] Each memory chip includes a memory array, row and column decoders, and data registers connected to the memory array. The memory array includes multiple memory cells arranged in an array. The row and column decoders are used to locate the target memory cell in the memory array based on the input address, and the data registers are used to cache data in the memory array. A memory cell consists of a transistor.
[0034] In some embodiments, the double data rate system further includes a first driving resistor 4 and a second driving resistor 5 , the memory driving circuit 1 is connected to the input / output power supply IOVDD through the first driving resistor 4 , and the memory driving circuit 1 is grounded through the second driving resistor 5 .
[0035] Exemplarily, the double data rate system further includes a circuit board 6, on which the memory driving circuit, the first driving resistor, the second driving resistor, the pull-up termination resistor, the address signal line, and the plurality of memory particles are all arranged.
[0036] In the related art, when a memory driver circuit is connected to multiple memory chips, the IOVDD power supply cannot be laid around the resistor array, resulting in an open circuit for the address signals of the memory chips. In the DDR system of this embodiment, since the chip core power supply (i.e., VCC) is arranged very widely on the circuit board, it is easy to connect to the terminal electrical connection resistor array (i.e., a row of resistors for address signals A0 to A13) for the DDR address signals, thereby solving the problem in the related art caused by the inability to lay the IOVDD power supply around the resistor array, resulting in an open circuit for the address signals of the memory chips, thereby seriously deteriorating the signal quality.
[0037] The method for obtaining the resistance value of the pull-up termination resistor may include the following specific implementation steps:
[0038] 1) On the circuit board, connect the address signal of the memory chip to the core power supply (i.e. VCC) through a resistor.
[0039] 2) Calculate the high level of the address signal of the DDR memory chip. At this time, the PMOS transistor of the memory driver circuit is turned on and the NMOS transistor is turned off. It is known that the power supply of the memory driver circuit is the input and output power supply IOVDD, and the pull-up resistor R at the end of the memory chip is connected to VCC. According to the Ohm resistance voltage divider law, the voltage of the signal at the high level is
[0040]
[0041] where Z O It is the equivalent pull-up / pull-down resistor of the PMOS / NMOS tube in the memory driver circuit.
[0042] 3) Calculate the low level of the address signal of the DDR memory chip. At this time, the PMOS transistor of the memory driver circuit is turned off and the NMOS transistor is turned on. It is known that the pull-up resistor R at the end of the memory chip is connected to VCC, and the equivalent pull-down resistance Z of the NMOS transistor of the memory driver circuit is flowing O To the ground.
[0043] According to Ohm's resistance voltage divider law, the voltage of the signal at a high level is
[0044]
[0045] 4) Use the high and low levels of the address signal of the DDR memory chip obtained in 2) and 3) to calculate the amplitude of the address signal, that is,
[0046] ΔV=V high -V low
[0047] That is to say
[0048]
[0049] Simplified to
[0050]
[0051] 5) Considering the loss from the chip end to the memory particle end, assuming that the signal amplitude drops to 1 / A of the original, the actual address signal amplitude reaching the memory particle is ΔV / A.
[0052] 6) According to the specification of the memory chip address signal amplitude ΔVspec, the required termination resistor value is deduced in reverse. The actual address signal amplitude reaching the memory chip needs to meet the condition of not less than the address signal amplitude specification ΔVspec.
[0053] Right now
[0054]
[0055] get
[0056]
[0057] Select a resistor that meets the above resistance conditions as pull-up termination resistor 2 and connect it to the chip core power supply VCC on the circuit board. This ensures that the address signal quality at the memory chip end is not degraded due to an open circuit, and the amplitude meets the designed ideal amplitude.
[0058] refer to Figure 4 , Figure 4The equivalent circuit diagram of the address signal line in the memory system of the embodiment of the present application changes from 0 to 1 is shown, where the capacitance C = memory chip equivalent capacitance × 8. Figure 5 , Figure 5 An equivalent circuit diagram showing the change of the address signal line from 1 to 0 in the memory system according to an embodiment of the present application is shown.
[0059] refer to Figure 6 As shown, when the address signal line of the memory system of this embodiment is connected to the chip core power supply VCC, the "eyes" in the waveform diagram obtained at the memory particle end are "open" and meet the specifications, and the memory system can work normally, which largely solves the following technical problems in related technologies: the address signal line of the memory system is open at the memory particle end and generates echo oscillation, affecting the signal quality, causing the DDR particle receiving end to not meet the standard, affecting normal operation.
[0060] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.
[0061] Another embodiment of the present application provides a memory including the double data rate memory system of any embodiment of the present application. The memory can achieve the beneficial technical effects achieved by the double data rate memory system.
[0062] Another embodiment of the present application provides an electronic device including the memory of any embodiment of the present application. The electronic device can achieve the beneficial technical effects achieved by the double data rate memory system of the embodiment of the present application.
[0063] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.
[0064] It should be noted that the above embodiments merely represent implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and such modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.
Claims
1. A double data rate memory system, characterized in that: Including memory driving circuit, pull-up termination resistor, address signal line, and multiple memory particles; The memory driving circuit and the memory particles are both connected to the address signal line; A first end of the pull-up termination resistor is connected to the address signal line, and a second end of the pull-up termination resistor is connected to a chip core power supply.
2. The system according to claim 1, wherein: The system further includes a first driving resistor and a second driving resistor. The memory driving circuit is connected to an input and output power supply through the first driving resistor, and the memory driving circuit is grounded through the second driving resistor.
3. The system according to claim 2, characterized in that The system further includes a circuit board, and the memory driving circuit, the first driving resistor, the second driving resistor, the pull-up termination resistor, the address signal line, and the plurality of memory particles are all arranged on the circuit board.
4. The system according to any one of claims 1 to 3, characterized in that The plurality of memory chips include 8 memory chips.
5. The system according to any one of claims 1 to 3, characterized in that The memory particle includes a storage array and a row and column decoder and a data register respectively connected to the storage array. The storage array includes a plurality of storage cells arranged in an array form; the row and column decoder is used to locate the target storage cell in the storage array according to the input address, and the data register is used to cache the data in the storage array.
6. The system according to claim 5, characterized in that The memory cell includes a transistor.
7. A memory, characterized in that: A double data rate memory system comprising the method of any one of claims 1 to 6.
8. An electronic device, characterized in that: Comprising the memory according to claim 7.