Signal output circuit
Through the combination of bias circuit, controller and comparator circuit, the problem of uncontrolled current and voltage in constant current or constant voltage output circuit is solved, controllable output and fault diagnosis are achieved, and the stability and reliability of the circuit are improved.
Patent Information
- Application Number
- CN202422859042.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-09-26
- Estimated Expiration
- 2034-11-22
AI Technical Summary
In the prior art, the constant current or constant voltage output circuit lacks a controllable input terminal, the current and voltage are uncontrolled, and are sensitive to temperature changes, and lack enable and diagnostic functions.
The bias circuit, the controller, the first transistor, the second transistor and the comparator circuit are adopted to achieve constant current or constant voltage output by comparing the voltage relationship between the controllable input terminal and the feedback input terminal, and is equipped with a fault diagnosis function.
It realizes controllable constant current or constant voltage output, reduces the influence of temperature change, has the ability to enable and diagnose faults, and improves the reliability and stability of the circuit.
Smart Images
Figure CN223391326U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a signal output circuit, belonging to the field of control circuits. Background Art
[0002] Constant current or constant voltage output is crucial in any application requiring precise control to ensure device performance, safety, and efficiency. This includes battery charging, LED lighting, solar systems, powering electronic devices, power conversion, laboratory testing, medical devices, industrial automation, electric vehicles, telecommunications equipment, and power system protection.
[0003] Currently, current limiting is often achieved by using two transistors and feedback voltage. However, this two-transistor circuit may present the following issues: 1. The output current of the main circuit is uncontrolled due to the lack of a controllable input terminal; 2. The output voltage of the main circuit is uncontrolled due to the lack of a controllable input terminal; 3. The circuit lacks enable and diagnostic functions; and 4. The circuit is significantly affected by temperature fluctuations, resulting in poor temperature characteristics.
[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Utility Model Content
[0005] In view of this, the present application provides a signal output circuit, which aims to achieve the function of adjustable constant current output or constant voltage output.
[0006] According to one aspect of an embodiment of the present utility model, a signal output circuit is provided, comprising: a bias circuit; a controller; a first transistor, comprising a first base, a first collector and a first emitter; a second transistor, comprising a second base, a second collector and a second emitter, the second collector being connected to the bias circuit and the first base respectively, and the second emitter being grounded; a comparator circuit, comprising a positive input terminal, a negative input terminal and an output terminal, the positive input terminal being connected to the first emitter, the negative input terminal receiving a signal from a PWM terminal of the controller, and the signal from the output terminal being transmitted to the second base.
[0007] The first collector is connected to the first interface, the first emitter is connected to the second interface, the first interface serves as the output interface, and the second interface is left floating; or, the first collector is connected to the first interface, the first emitter is connected to the second interface, the first interface is connected to a high level, and the second interface serves as the output interface.
[0008] Optionally, the bias circuit includes: a high level terminal; a bias terminal; a first enable terminal; and a first switch circuit, which is respectively connected to the high level terminal, the bias terminal, the first enable terminal and the ground terminal.
[0009] Optionally, the bias circuit further includes a diode, and the first switch circuit is connected to the high level end through the diode.
[0010] Optionally, it further includes a first capacitor and a first resistor, one end of the first capacitor is connected to the second collector and one end of the first resistor respectively, the other end of the first capacitor is connected to the second emitter, and the other end of the first resistor is connected to the bias end.
[0011] Optionally, the comparator circuit also includes: a second resistor connected between the output terminal and the second base; a third resistor connected between the second base and the ground terminal; a fourth resistor connected between the first emitter and the ground terminal; and a second capacitor connected between the first emitter and the ground terminal.
[0012] Optionally, a fault diagnosis circuit is also included, which includes: a field effect transistor, including a gate, a drain and a source, the drain is connected to the first collector, and the source is connected to the AD terminal of the controller; a power supply terminal; a second enable terminal; and a second switching circuit, respectively connected to the power supply terminal, the second enable terminal, the gate and the ground terminal.
[0013] Optionally, the fault diagnosis circuit further includes: a fifth resistor connected between the drain and the first collector; a sixth resistor connected between the second switch circuit and the gate; and a seventh resistor grounded and connected to an end of the sixth resistor away from the gate.
[0014] Optionally, the AD terminal of the controller is connected to an eighth resistor which is grounded.
[0015] Compared with the prior art, the embodiments of the present application have the following beneficial effects:
[0016] In an embodiment of the present application, the circuit includes: a bias circuit; a controller; a first transistor, including a first base, a first collector and a first emitter; a second transistor, including a second base, a second collector and a second emitter, the second collector being connected to the bias circuit and the first base respectively, and the second emitter being grounded; a comparator circuit, including a positive input terminal, a negative input terminal and an output terminal, the positive input terminal being connected to the first emitter, the negative input terminal receiving a signal from the controller PWM terminal, and the signal from the output terminal being transmitted to the second base; the first collector being connected to the first interface, the first emitter being connected to the second interface, the first interface being used as an output interface, and the second interface being left unconnected; or, the first collector being connected to the first interface, the first emitter being connected to the second interface, the first interface being connected to a high level, and the second interface being used as an output interface. In an embodiment of the present application, the comparator compares the voltage relationship between the controllable input terminal and the feedback input terminal, so that the circuit achieves the function of limiting current or voltage, thereby realizing constant current or constant voltage output. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without any creative work.
[0018] Figure 1 A schematic diagram of a signal output circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0019] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0021] like Figure 1As shown, the signal output circuit may include: a bias circuit; a controller; a first transistor Q2, including a first base, a first collector and a first emitter; a second transistor Q3, including a second base, a second collector and a second emitter, the second collector being connected to the bias circuit and the first base respectively, and the second emitter being grounded; a comparator circuit, including a positive input terminal, a negative input terminal and an output terminal, the positive input terminal being connected to the first emitter, the negative input terminal receiving a signal from the controller PWM terminal MCU_PWM, and the signal from the output terminal being transmitted to the second base; the first collector being connected to the first interface CON_2, the first emitter being connected to the second interface CON_3, the first interface being used as an output interface, and the second interface being left floating; or, the first collector being connected to the first interface, the first emitter being connected to the second interface, the first interface being connected to a high level, and the second interface being used as an output interface.
[0022] In this embodiment, the comparator compares the voltage between the controllable input terminal and the feedback input terminal, so that the circuit can achieve the function of limiting current or voltage, thereby realizing constant current or constant voltage output.
[0023] Furthermore, the bias circuit includes: a high level terminal CON_1; a bias terminal; a first enable terminal MCU_1; and a first switch circuit, which is respectively connected to the high level terminal, the bias terminal, the first enable terminal and the ground terminal.
[0024] In this embodiment, the first switch circuit is composed of resistors (R3, R5, R6, R7) and a first switch tube Q1. Exemplarily, the first switch tube is composed of a plurality of transistors.
[0025] Furthermore, the bias circuit further includes a diode D1 , and the first switch circuit is connected to the high level end via the diode.
[0026] Furthermore, it includes a first capacitor C1 and a first resistor R1, one end of the first capacitor is connected to the second collector and one end of the first resistor respectively, the other end of the first capacitor is connected to the second emitter, and the other end of the first resistor is connected to the bias end.
[0027] Furthermore, the comparator circuit also includes: a second resistor R10, connected between the output end and the second base; a third resistor R11, connected between the second base and the ground end; a fourth resistor R13, connected between the first emitter and the ground end; and a second capacitor C2, connected between the first emitter and the ground end.
[0028] Optionally, a fault diagnosis circuit is also included, which includes: a field effect transistor T1, including a gate, a drain and a source, the drain is connected to the first collector, and the source is connected to the controller AD terminal MCU_AD; a power supply terminal VCC_5V; a second enable terminal MCU_2; and a second switching circuit, respectively connected to the power supply terminal, the second enable terminal, the gate and the ground terminal.
[0029] In this embodiment, the second switch circuit is composed of resistors (R12, R14, R15, R16) and a second switch tube Q4. Exemplarily, the second switch tube is composed of a plurality of transistors.
[0030] This embodiment diagnoses faults by comparing the AD conversion value with the preset short-circuit voltage limit value and open-circuit voltage limit value.
[0031] Optionally, the fault diagnosis circuit further includes: a fifth resistor R2 connected between the drain and the first collector; a sixth resistor R8 connected between the second switch circuit and the gate; and a seventh resistor R9 grounded and connected to an end of the sixth resistor away from the gate.
[0032] Optionally, the AD terminal of the controller is connected to an eighth resistor R4 which is grounded.
[0033] As can be seen from the above, the signal output circuit has 8 PIN pin interfaces, namely CON_1, CON_2, CON_3, MCU_1, MCU_2, MCU_PWM, MCU_AD, and VCC_5V. The specific circuit principles include:
[0034] 1) Constant current output mode:
[0035] CON_1 is connected to a high-level signal to provide a bias voltage for driving Q2.
[0036] CON_2 is connected to the high-side load, and Q2 realizes the low-side adjustable constant current output.
[0037] CON_3 is left floating.
[0038] MCU_1 is the enable switch for the base bias voltage of Q2, which is active high. When the signal is low, Q2 is not conducting, so the circuit consumes no current at the CON_2 terminal.
[0039] MCU_2 is the diagnostic enable signal for CON_2 and is active high. When the signal is high to enable diagnostics, the circuit has extremely low leakage current, which is calculated as: UCON_2 / (R2+R4).
[0040] MCU_PWM is the control signal for the current (I) in Q2. After third-order filtering and rectification, MCU_PWM is converted into a FUN- DC voltage (UFUN-). The relationship between this voltage and the current (I) in Q2 is: UFUN- / R13=I.
[0041] MCU_AD is the diagnostic enable signal of CON_2, which is used to respond to short-circuit and open-circuit faults of Q2 during operation.
[0042] VCC_5V is the power input terminal of the circuit.
[0043] 2) Constant voltage output mode:
[0044] CON_1 is connected to a high-level signal to provide a bias voltage for driving Q2.
[0045] CON_2 is connected to a high level (can be shorted with CON_1) and serves as the energy source for constant voltage output. Q2 realizes low-side adjustable constant voltage output.
[0046] CON_3 is the output terminal of the regulated constant voltage.
[0047] The functions of MCU_1 and MCU_2 are the same as those in constant current output mode.
[0048] MCU_PWM is the control signal for the output voltage on CON_3. After third-order filtering and rectification, MCU_PWM is converted into a FUN- DC voltage (UFUN-). The relationship between FUN- and the output voltage on CON_3 (U CON_3) is: UFUN- = U CON_3.
[0049] The function of MCU_AD is the same as that in constant current output mode.
[0050] VCC_5V is the power input terminal of the circuit.
[0051] The above is only a preferred embodiment of the present embodiment patent, but the protection scope of the present embodiment patent is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the scope disclosed by the present embodiment patent according to the technical solution and utility model concept of the present embodiment patent, which fall within the protection scope of the present embodiment patent.
Claims
1. A signal output circuit, characterized in that: include: Bias circuit; Controller; A first triode, comprising a first base, a first collector and a first emitter; A second triode comprises a second base, a second collector and a second emitter, wherein the second collector is connected to the bias circuit and the first base respectively, and the second emitter is grounded; The comparator circuit includes a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is connected to the first emitter, the negative input terminal receives a signal from the controller PWM terminal, and the signal from the output terminal is transmitted to the second base; The first collector is connected to the first interface, the first emitter is connected to the second interface, the first interface serves as the output interface, and the second interface is left floating; or, The first collector is connected to the first interface, the first emitter is connected to the second interface, the first interface is connected to a high level, and the second interface serves as an output interface.
2. The signal output circuit according to claim 1, wherein: The bias circuit includes: High level end; Bias terminal; First enabling terminal; The first switch circuit is connected to the high level terminal, the bias terminal, the first enable terminal and the ground terminal respectively.
3. The signal output circuit according to claim 2, wherein: The bias circuit further includes a diode, and the first switch circuit is connected to the high level end through the diode.
4. The signal output circuit according to claim 2, wherein: It also includes a first capacitor and a first resistor, one end of the first capacitor is connected to the second collector and one end of the first resistor respectively, the other end of the first capacitor is connected to the second emitter, and the other end of the first resistor is connected to the bias end.
5. The signal output circuit according to claim 1, wherein: The comparator circuit also includes: a second resistor connected between the output terminal and the second base; a third resistor connected between the second base and the ground terminal; a fourth resistor connected between the first emitter and the ground terminal; The second capacitor is connected between the first emitter and the ground terminal.
6. The signal output circuit according to claim 1, wherein: It also includes a fault diagnosis circuit, which includes: The field effect tube comprises a gate, a drain and a source, wherein the drain is connected to the first collector and the source is connected to the AD terminal of the controller; Power supply end; The second enabling terminal; The second switch circuit is connected to the power supply terminal, the second enable terminal, the gate terminal and the ground terminal respectively.
7. The signal output circuit according to claim 6, characterized in that: The fault diagnosis circuit also includes: a fifth resistor connected between the drain and the first collector; a sixth resistor connected between the second switch circuit and the gate; The seventh resistor is grounded and connected to an end of the sixth resistor away from the gate.
8. The signal output circuit according to claim 6, wherein: The AD terminal of the controller is connected to an eighth resistor which is grounded.