Array substrate and display panel

Abstract

The utility model provides an array substrate and a display panel. The array substrate is provided with a display area and a non-display area located on the periphery of the display area. The array substrate comprises a substrate, a first transistor and a second transistor. The first transistor is arranged on the substrate and located in the non-display area, the first transistor comprises a first source electrode, a first drain electrode and a first active layer, the first source electrode, the first drain electrode and the first active layer are arranged in a stacked mode, and the first active layer is located between the first source electrode and the first drain electrode. The second transistor is arranged on the substrate and located in the display area, the second transistor comprises a second source electrode, a second drain electrode and a second active layer, the second source electrode, the second drain electrode and the second active layer are arranged in a stacked mode, and the second active layer is located between the second source electrode and the second drain electrode. The first transistor and the second transistor are both of a closed-loop structure, and the second source electrode and the first source electrode are arranged on the same layer. The first active layer and the second active layer are arranged on the same layer. The second drain electrode and the first drain electrode are arranged on the same layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the related art, an array substrate combining IGZO (Indium Gallium Zinc Oxide) technology and LTPS (Low Temperature Poly Silicon) technology has been proposed. This array substrate utilizes the high mobility of the LTPS structure and the low leakage current of oxide semiconductors (e.g., IGZO (Indium Gallium Zinc Oxide)) to reduce the size of thin film transistors to a certain extent.

[0003] However, the array substrate has a display area and a non-display area, and thin-film transistors need to be set in both the display area and the non-display area. The combination of IGZO and LTPS technologies adopted in the relevant technology is mainly for the purpose of reducing the size of the thin-film transistors in the non-display area, which has a certain effect on achieving high PPI, but the effect is not significant and needs to be improved. Utility Model Content

[0004] In view of this, the present application provides an array substrate and a display panel to improve the problem that the combination of LTPS and IGZO reduces the size of thin film transistors but does not significantly improve the PPI.

[0005] The technical solutions adopted by this application to solve the above technical problems are:

[0006] In a first aspect, an embodiment of the present application provides an array substrate having a display area and a non-display area located outside the display area, the array substrate comprising:

[0007] substrate;

[0008] a first transistor disposed on the substrate and located in the non-display area, the first transistor comprising a first source electrode, a first drain electrode, and a first active layer, wherein the first source electrode, the first drain electrode, and the first active layer are stacked and the first active layer is located between the first source electrode and the first drain electrode;

[0009] a second transistor disposed on the substrate and located in the display area, the second transistor comprising a second source electrode, a second drain electrode, and a second active layer, the second source electrode, the second drain electrode, and the second active layer being stacked, and the second active layer being located between the second source electrode and the second drain electrode;

[0010] Among them, the first transistor and the second transistor are both closed-loop structures, and the second source is set in the same layer and made of the same material as the first source, the second drain is set in the same layer and made of the same material as the first drain, and the first active layer is set in the same layer and made of the same material as the second active layer.

[0011] In some embodiments of the present application, the orthographic projections of the first transistor and the second transistor on the substrate are both circular.

[0012] In some embodiments of the present application, the orthographic projections of the first source electrode, the first drain electrode, and the first active layer on the substrate are all circular, and the radius of the orthographic projection of the first source electrode, the radius of the orthographic projection of the first drain electrode, and the radius of the orthographic projection of the first active layer are all equal;

[0013] The orthographic projections of the second source, the second drain and the second active layer on the substrate are all circular, and the orthographic radius of the second source, the orthographic radius of the second drain and the orthographic radius of the second active layer are all equal.

[0014] In some embodiments of the present application, the array substrate further includes a third transistor, which is disposed on the substrate and located in the non-display area. The third transistor is electrically connected to the first transistor, and the orthographic projection of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first transistor on the substrate. The third transistor includes a third active layer, and an angle between a channel portion of the first active layer and the plane of the substrate is different from an angle between a channel portion of the third active layer and the plane of the substrate.

[0015] In some embodiments of the present application, the first source electrode, the first active layer, and the first drain electrode are sequentially stacked on the substrate in a direction away from the substrate, and the first source electrode is electrically connected to the conductor portion of the third active layer.

[0016] In some embodiments of the present application, the first transistor also includes a first gate and a first gate insulating layer, the first gate insulating layer is arranged on the substrate and covers the first source, the first drain and the first active layer, and the first gate is arranged on the side of the first gate insulating layer away from the substrate and is electrically connected to the third transistor.

[0017] In some embodiments of the present application, the second transistor includes a second gate insulating layer and a second gate, the second gate insulating layer covers the second source, the second drain and the second active layer, and the second gate is arranged on a side of the second gate insulating layer away from the substrate.

[0018] In some embodiments of the present application, the first gate insulating layer and the second gate insulating layer are connected in the same layer and are made of the same material, and the first gate and the second gate are arranged in the same layer and are made of the same material.

[0019] In some embodiments of the present application, the orthographic projection of the first gate on the substrate covers a portion of the orthographic projection of the first active layer on the substrate, and a portion of the first gate is aligned with the channel portion in the first active layer.

[0020] In some embodiments of the present application, the orthographic projection of the first gate on the substrate is a circular ring, and the circular ring is coaxially arranged with the circle.

[0021] In some embodiments of the present application, the third transistor is a low-temperature polysilicon thin film transistor, the first transistor is an oxide thin film transistor, and the first transistor is located on a side of the third transistor away from the substrate.

[0022] In a second aspect, an embodiment of the present application provides a display panel comprising the array substrate as described in the first aspect.

[0023] In summary, due to the adoption of the above technical solution, this application has at least the following beneficial effects:

[0024] The embodiments of the present application provide an array substrate and a display panel. By configuring the first transistor and the second transistor as a closed-loop structure, the width of the first transistor and the width of the second transistor are converted from a linear length to a circular circumference, which is beneficial to reducing the size of the first transistor and the second transistor, thereby improving the PPI of the display panel. Specifically, the size of the array substrate actually occupied by the first transistor and the second transistor in the width direction is set to the diameter of the circle, which greatly reduces the size occupied by the first transistor in the non-display area and the size occupied by the second transistor in the display area, which is beneficial to the miniaturization of the device. In addition, by configuring the second source electrode and the first source electrode in the same layer and with the same material, configuring the second drain electrode and the first drain electrode in the same layer and with the same material, and configuring the first active layer and the second active layer in the same layer and with the same material, when the two transistors are formed, the source electrode, drain electrode and active layer of both can be formed simultaneously, which is beneficial to improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0026] Figure 2 A schematic top view of a first transistor and a second transistor in an array substrate provided in an embodiment of the present application.

[0027] Figure 3A schematic top view of another first transistor in an array substrate provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present application (Part 1);

[0029] Figure 5 A schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present application (Part II);

[0030] Figure 6 A schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present application (Part 3);

[0031] Figure 7 A circuit diagram of an array substrate provided in an embodiment of the present application.

[0032] Description of reference numerals:

[0033] 100. Array substrate; 110. Base; 120. Third transistor; 121. Third active layer; 122. Third gate insulating layer; 123. Third gate; 130. First transistor; 131. First source; 132. First drain; 133. First active layer; 134. First gate; 135. First gate insulating layer; 140. Second transistor; 141. Second source; 142. Second drain; 143. Second active layer; 144. Second gate insulating layer; 145. Second gate; 150. Interlayer dielectric layer; 160. Buffer layer; 170. Passivation layer; 180. Pixel electrode; NA. Non-display area; AA. Display area. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0035] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0036] At the same time, this application uses specific terms to describe the embodiments of this application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "one embodiment," "an embodiment," or "an alternative embodiment" mentioned twice or multiple times in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application may be appropriately combined.

[0037] See Figure 1 and Figure 2 An embodiment of the present application provides an array substrate 100 having a display area AA and a non-display area NA located outside the display area AA.

[0038] The array substrate includes a substrate 110, a first transistor 130, and a second transistor 140. The first transistor 130 is disposed on the substrate 110 and located in the non-display area NA. The first transistor 130 includes a first source electrode 131, a first drain electrode 132, and a first active layer 133. The first source electrode 131, the first drain electrode 132, and the first active layer 133 are stacked, and the first active layer 133 is located between the first source electrode 131 and the first drain electrode 132.

[0039] The second transistor 140 is disposed on the substrate 110 and located in the display area AA. The second transistor 140 includes a second source electrode 141, a second drain electrode 142 and a second active layer 143. The second source electrode 141, the second drain electrode 142 and the second active layer 143 are stacked, and the second active layer 143 is located between the second source electrode 141 and the second drain electrode 142.

[0040] The first transistor 130 and the second transistor 140 both have closed-loop structures, and the second source electrode 141 is provided in the same layer and made of the same material as the first source electrode 131. The first active layer 143 is provided in the same layer and made of the same material as the second active layer 133. The second drain electrode 142 is provided in the same layer and made of the same material as the first drain electrode 132.

[0041] The technical solution provided in this application converts the width of the first transistor 130 and the width of the second transistor 140 from a linear length to a circular circumference by configuring both the first transistor 130 and the second transistor 140 in a closed-loop structure. This helps reduce the size of the first transistor 130 and the second transistor 140, thereby improving the PPI of the display panel. Specifically, the width of the array substrate 100 actually occupied by the first transistor 130 and the second transistor 140 is changed to the diameter of the circle, significantly reducing the size occupied by the first transistor 130 in the non-display area NA and the size occupied by the second transistor 140 in the display area, thereby facilitating device miniaturization. Furthermore, by providing the second source electrode 141 and the first source electrode 131 in the same layer and using the same material, the second drain electrode and the first drain electrode in the same layer and using the same material, and the first active layer 133 and the second active layer 143 in the same layer and using the same material, the source, drain, and active layers of both transistors can be formed simultaneously during molding, thereby improving production efficiency.

[0042] In some embodiments, the orthographic projections of the first transistor 130 and the second transistor 140 on the substrate 110 are both circular. It should be noted here that for the closed-loop structure described in the aforementioned embodiment, it includes a ring shape with a hollow middle, and also includes a circular shape with a solid middle, and the closed-loop structure can be a square ring, a square, a triangular ring, a triangle, or a circular ring, a circle, etc. And, here, the orthographic projections of the first transistor 130 and the second transistor 140 on the substrate 110 are both circular, which means that the orthographic projection of the outer contour of the first transistor 130 on the substrate 110 is circular, and the orthographic projection of the outer contour of the second transistor 140 on the substrate 110 is circular. Setting the orthographic projections of the first transistor 130 and the second transistor 140 on the substrate 110 to be circular is conducive to controlling the area occupied by the two transistors in the display area and the non-display area NA where they are located, and then the array substrate 100 with the same volume can place more transistors.

[0043] Furthermore, the orthographic projections of the first source electrode 131, the first drain electrode 132, and the first active layer 133 on the substrate 110 are all circular. Furthermore, the radii of the orthographic projections of the first source electrode 131, the first drain electrode 132, and the first active layer 133 are all equal. By ensuring that the orthographic projections of the first source electrode 131, the first drain electrode 132, and the first active layer 133 are all circular and have equal radii, the first source electrode 131, the first drain electrode 132, and the first active layer 133 can completely overlap, thereby confining the channel portion of the first active layer 133 between the first drain electrode 132 and the first source electrode 131. The length of the channel portion is equal to the thickness of the first active layer 133, forming a vertical channel. This reduces the channel length of the transistor. Meanwhile, the channel width of the transistor is equal to the circumference of the outer edge of the active layer, increasing the channel width of the transistor and improving the on-state current and mobility of the first transistor 130.

[0044] Furthermore, the orthographic projections of the second source electrode 141, the second drain electrode 142, and the second active layer 143 on the substrate 110 are all circular, and the radii of the orthographic projections of the second source electrode 141, the second drain electrode 142, and the second active layer 143 are all equal. This facilitates the formation of the source electrode, the drain electrode, and the active layer, and the miniaturization of the second transistor 140.

[0045] In some embodiments, the array substrate 100 further includes a third transistor 120. The third transistor 120 is disposed on the substrate 110 and located in the non-display area NA. The third transistor 120 includes a third active layer 121. A first transistor 130 is disposed on the substrate 110 and located in the non-display area NA. The first transistor 130 is electrically connected to the third transistor 120, and an orthographic projection of the third transistor 120 on the substrate 110 at least partially overlaps with an orthographic projection of the first transistor 130 on the substrate 110.

[0046] The included angle between the channel portion of the first active layer 133 and the plane where the substrate 110 is located is different from the included angle between the channel portion of the third active layer 121 and the plane where the substrate 110 is located.

[0047] By disposing the first active layer 133 in the first transistor 130 between the stacked first source 131 and first drain 132, the length of the channel portion of the first active layer 133 is limited by the thickness of the first active layer 133, forming a vertical channel. This improves the mobility and on-state current of the first transistor 130. Furthermore, the angle between the channel portion of the first active layer 133 and the plane of the substrate 110 is different from the angle between the channel portion of the third active layer 121 and the plane of the substrate 110, thereby adapting to the third transistor 120, which originally has a higher mobility and on-state current. The third transistor 120 and the first transistor 130 are electrically connected to form a CMOS circuit, effectively alleviating the current mismatch problem in CMOS circuits formed by combining LTPS and IGZO. In detail, the first source electrode 131, the first drain electrode 132, and the first active layer 133 are stacked and arranged, and the first active layer 133 is located between the first source electrode 131 and the first drain electrode 132, so that the channel portion of the active layer is defined between the first source electrode 131 and the first drain electrode 132. Since the first source electrode 131 and the first drain electrode 132 are stacked, the channel portion of the first active layer 133 is defined by the thickness of the first active layer 133, and the length of the channel portion of the first active layer 133 is the thickness of the first active layer 133, so that the channel portion of the first active layer 133 is formed into a vertical channel. Then, by limiting the distance between the channel portion of the first active layer 133 and the plane where the substrate 110 is located, the channel portion of the first active layer 133 is defined. The angle is different from the angle between the channel portion of the third active layer 121 and the plane of the substrate 110, indicating that the third transistor 120 is an LTPS transistor with a large mobility and on-state current, that is, the array substrate 100 is a combination of an LTPS transistor and an IGZO transistor in the non-display area NA, so that the third transistor 120 and the first transistor 130 are electrically connected to form a CMOS circuit, and the first transistor 130 has a vertical channel, thereby improving the mobility and on-state current of the first transistor 130, ensuring that the current in the third transistor 120 matches the current in the first transistor 130, and effectively improving the current mismatch problem in the CMOS circuit formed by the combination of LTPS and IGZO. In addition, by making the orthographic projection of the third transistor 120 on the substrate 110 at least partially overlap with the orthographic projection of the first transistor 130 on the substrate 110, it is beneficial to reduce the space occupied on the plane, thereby providing more space for the layout of other functional circuit components in the non-display area NA, and the partial overlap of the orthographic projection of the third transistor 120 and the orthographic projection of the first transistor 130 can also reduce the parasitic resistance between the two, shorten the current transmission path, and play a certain auxiliary role in the current matching of the two transistors.

[0048] Please note that, see Figure 1 and Figure 5The third transistor 120 is a low-temperature polysilicon thin-film transistor, and the first transistor 130 is an oxide thin-film transistor. The first transistor 130 is located on the side of the third transistor 120 facing away from the substrate 110. Among LTPS (Low Temperature Poly Silicon) thin-film transistors and IGZO (Indium Gallium Zinc Oxide) thin-film transistors, LTPS thin-film transistors generally have larger carrier mobility and on-state current, while IGZO generally has smaller carrier mobility and on-state current. If the IGZO thin-film transistor and the LTPS thin-film transistor are directly electrically connected to form a CMOS circuit, the CMOS circuit will have a current mismatch problem, affecting the normal operation of the CMOS circuit and resulting in reduced stability of the TFT device. In the present application, when the third transistor 120 is an LTPS thin-film transistor with a large on-state current and the first transistor 130 is an IGZO thin-film transistor with a small on-state current, the first active layer 133 in the first transistor 130 is arranged between the stacked first source 131 and the first drain 132, so that the channel length of the first active layer 133 is limited by the thickness of the first active layer 133, forming a vertical channel, thereby improving the mobility and on-state current of the first transistor 130 to adapt to the third transistor 120 that originally has a large mobility and on-state current. Compared with the CMOS circuit of the traditional structure, the current of the first transistor 130 with a vertical channel in the CMOS circuit of the present application is more matched with the current of the third transistor 120 with a horizontal channel, so that the CMOS circuit operates stably and the stability of the TFT device is improved.

[0049] In some embodiments, a buffer layer 160 is disposed on the substrate 110, extending from the non-display area NA to the display area AA. The third transistor 120 is disposed on a side of the buffer layer 160 facing away from the substrate 110 and includes a second active layer 143, a third gate insulating layer 122, and a third gate electrode 123. The second active layer 143 is disposed on a side of the buffer layer 160 facing away from the substrate 110. The third gate insulating layer 122 is disposed on a side of the buffer layer 160 facing away from the substrate 110 and covers the second active layer 143. The third gate insulating layer 122 extends from the non-display area NA to the display area AA. The third gate electrode 123 is disposed on a side of the third gate insulating layer 122 facing away from the substrate 110. The third gate electrode 123 is annular, with a portion aligned with the second active layer 143.

[0050] Furthermore, an interlayer dielectric layer 150 is disposed on a side of the third gate insulating layer 122 facing away from the substrate 110 . The interlayer dielectric layer 150 covers the third gate 123 and extends from the non-display area NA to the display area AA.

[0051] In some embodiments, the first source electrode 131, the first active layer 133, and the first drain electrode 132 are sequentially stacked on the substrate 110 in a direction away from the substrate 110, and the first source electrode 131 is electrically connected to the conductive portion of the third active layer 121. Specifically, the first source electrode 131 is disposed on a side of the interlayer dielectric layer 150 facing away from the substrate 110, the first active layer 133 is disposed on a side of the first source electrode 131 facing away from the substrate 110, and the first drain electrode 132 is disposed on a side of the first active layer 133 facing away from the substrate 110. The first source electrode 131 passes through the interlayer dielectric layer 150 and extends into the third gate insulating layer 122, electrically connecting the first source electrode 131 to the conductive portion of the first active layer 133. It should be noted that, for the third gate 123, its orthographic projection on the substrate is a circular ring. The hollow structure in the middle part of the circular ring is used to avoid the connection between the first source 131 and the conductor part of the first active layer 133, thereby preventing the third gate 123 from obstructing the connection between the first source 131 and the conductor part of the first active layer 133.

[0052] The first transistor 130 also includes a first gate electrode 134 and a first gate insulating layer 135. The first gate insulating layer 135 is disposed on the substrate 110 and covers the first source electrode 131, the first drain electrode 132, and the first active layer 133, providing insulation protection for the source electrode, the drain electrode, and the active layer. The first gate electrode 134 is disposed on the side of the first gate insulating layer 135 facing away from the substrate 110 and is electrically connected to the third transistor 120. Specifically, the first gate electrode 134 is electrically connected to the third gate electrode 123 of the third transistor 120 through the first gate insulating layer 135 and the interlayer dielectric layer 150, thereby electrically connecting the third transistor 120 and the first transistor 130 to form a CMOS circuit.

[0053] In some embodiments, the first drain electrode 132, the first active layer 133, and the first source electrode 131 are sequentially stacked on the substrate 110 in a direction away from the substrate 110, and the first drain electrode 132 is electrically connected to the conductive portion of the third active layer 121. Specifically, the first drain electrode 132 is disposed on a side of the interlayer dielectric layer 150 facing away from the substrate 110, the first active layer 133 is disposed on a side of the first drain electrode 132 facing away from the substrate 110, and the first source electrode 131 is disposed on a side of the first active layer 133 facing away from the substrate 110. The first drain electrode 132 passes through the interlayer dielectric layer 150 and extends into the third gate insulating layer 122, electrically connecting the first drain electrode 132 to the conductive portion of the first active layer 133. It should be noted that, for the third gate 123, its orthographic projection on the substrate is a circular ring. The hollow structure in the middle part of the circular ring is used to avoid the connection between the first drain 132 and the conductor part of the first active layer 133, thereby preventing the third gate 123 from obstructing the connection between the first drain 132 and the conductor part of the first active layer 133.

[0054] The first transistor 130 also includes a first gate electrode 134 and a first gate insulating layer 135. The first gate insulating layer 135 is disposed on the substrate 110 and covers the first source electrode 131, the first drain electrode 132, and the first active layer 133, providing insulation protection for the source electrode, the drain electrode, and the active layer. The first gate electrode 134 is disposed on the side of the first gate insulating layer 135 facing away from the substrate 110 and is electrically connected to the third transistor 120. Specifically, the first gate electrode 134 is electrically connected to the third gate electrode 123 of the third transistor 120 through the first gate insulating layer 135 and the interlayer dielectric layer 150, thereby electrically connecting the third transistor 120 and the first transistor 130 to form a CMOS circuit.

[0055] Furthermore, the orthographic projection of the first gate 134 on the substrate 110 covers a portion of the orthographic projection of the first active layer 133 on the substrate 110, allowing the first gate 134 to be positioned as close as possible to the center of the first active layer 133, thereby reducing the size of the first transistor 130 in the width direction of the display panel. Furthermore, a portion of the first gate 134 is aligned with the channel portion of the first active layer 133, and a gate insulating layer is disposed between the first active layer 133 and the first gate 134, enabling the first gate 134 to function as a control transistor.

[0056] Furthermore, the orthographic projection of the first gate 134 on the substrate 110 is annular, and the annular shape is coaxially arranged with the circle. This means that the annular shape of the orthographic projection of the first gate 134 on the substrate 110 obstructs the outer edge of the circular orthographic projection of the first active layer 133 on the substrate. Furthermore, because the first drain 132 and the first source 131 completely overlap with the first active layer 133, the orthographic projection of the first gate 134 also obstructs the outer edges of the circular orthographic projections of the first drain 132 and the first source 131 on the substrate. This configuration converts the width of the first transistor 130 from a linear length to the circumference of a circle. This means that the actual width of the array substrate 100 occupied by the first transistor 130 is the diameter of the circle. This significantly reduces the size of the array substrate 100 occupied by the first transistor 130, facilitating device miniaturization.

[0057] In addition, the annular structure of the first gate 134 partially blocks the orthographic projection of the first active layer 133 on the substrate 110, limiting the channel width of the first transistor 130 to the perimeter of the outer edge of the first active layer 133. This helps increase the channel width of the transistor, thereby improving the device effect of the transistor. Furthermore, the first gate 134 extends toward the substrate 110 to ensure that the projection of the first gate 134 toward the side of the first active layer 133 covers the side of the first active layer 133, thereby ensuring that the first active layer 133 can form a channel with a length equal to the thickness of the first active layer 133.

[0058] See Figure 3 In another embodiment, the first active layer 133 is in the shape of a circular ring, but it can also be in other ring shapes. Correspondingly, the first source electrode 131 and the first drain electrode 132 are also in the shape of circular rings. The first active layer 133 is in the shape of a circular ring, having an inner ring and an outer ring. To ensure that the first gate electrode 134 can fully cover the inner ring and the outer ring of the first active layer, the inner ring diameter a of the first gate electrode 134 is smaller than the inner ring diameter b of the first active layer 133, and the outer ring diameter d of the first gate electrode 134 is larger than the outer ring diameter c of the first active layer 133. In this embodiment, the channel width is equal to the sum of the inner ring circumference and the outer ring circumference of the first active layer 133. Without increasing the size of the transistor, the channel width is further increased, thereby improving the device effect of the transistor.

[0059] In addition, configuring the first active layer 133 , the first drain electrode 132 and the first source electrode 131 to be in a ring shape is also beneficial for reducing parasitic capacitance.

[0060] In some embodiments, the second transistor 140 includes a second gate insulating layer 144 and a second gate 145. A second source electrode 141, a second drain electrode 142, and a second active layer 143 are stacked, with the second active layer 143 located between the second source electrode 141 and the second drain electrode 142. The second gate insulating layer 144 covers the second source electrode 141, the second drain electrode 142, and the second active layer 143. The second gate 145 is located on the side of the second gate insulating layer 144 facing away from the substrate 110. The structure of the second transistor 140 is the same as that of the first transistor 130, and they are arranged side by side along the width direction of the array substrate 100, so that the first transistor 130 and the second transistor 140 can be formed simultaneously.

[0061] Specifically, the second source electrode 141 is arranged in the same layer and made of the same material as the first source electrode 131, the second drain electrode 142 is arranged in the same layer and made of the same material as the first drain electrode 132, the first active layer 133 is arranged in the same layer and made of the same material as the second active layer 143, the first gate insulating layer 135 is connected to the second gate insulating layer 144 in the same layer and made of the same material, and the first gate electrode 134 is arranged in the same layer and made of the same material as the second gate electrode 145.

[0062] It should be noted that the structure of the second transistor 140 is the same as that of the first transistor 130. Correspondingly, the structure, shape and beneficial effects of the second source 141, the second drain 142, the second active layer 143 and the second gate 145 in the second transistor 140 can all refer to the relevant embodiments of the aforementioned first transistor 130 and will not be repeated here.

[0063] See Figure 4The embodiment of the present application further provides a method for manufacturing an array substrate 100, wherein the array substrate 100 includes a display area AA and a non-display area NA located outside the display area AA. The manufacturing method includes:

[0064] S1. Coating a buffer layer 160 on a substrate.

[0065] The substrate may be a glass substrate, and the film material of the buffer layer 160 may be a multi-layer stacked structure, such as a three-layer stacked structure of silicon oxide, silicon nitride, and silicon oxide stacked in sequence.

[0066] S2. Coating a semiconductor layer on the side of the buffer layer 160 facing away from the substrate.

[0067] The semiconductor material can be polysilicon, which can be obtained by laser annealing or other crystallization methods of amorphous silicon, and patterning the semiconductor layer into a polysilicon channel layer. The semiconductor layer coating is the third active layer 121 described in the above embodiment, located in the non-display area NA.

[0068] S3 . Form a third gate insulating layer 122 on a side of the buffer layer 160 facing away from the substrate, form a third gate 123 on a side of the third gate insulating layer 122 facing away from the substrate, and pattern the third gate 123 .

[0069] The first gate electrode 134 is coated with a film, the film material of which can be Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO, and is patterned, and the gate electrode is used as a mask to perform doping or plasma treatment on the areas on both sides of the channel.

[0070] S4. An interlayer dielectric layer 150 is coated on the side of the buffer layer 160 facing away from the substrate. The interlayer dielectric layer 150 covers the third gate 123 and is located in the display area AA and the non-display area NA. Then, the interlayer dielectric layer 150 and a portion of the third gate insulating layer 122 are etched to expose the conductor portion of the third active layer 121.

[0071] Interlayer dielectric coating, the film layer can be SiOx or SiNx or SiNx / SiOx or SiNOx, etc., and its patterning process.

[0072] S5. Metal coating is performed on the side of the interlayer dielectric layer 150 facing away from the substrate and patterned. A portion of the metal coating extends along the blind hole etched in the interlayer dielectric layer 150 to the conductor portion of the third active layer 121 to form an electrical connection. The metal coating forms a first source electrode 131 or a first drain electrode 132 in the non-display area NA, and forms a second source electrode 141 or a second drain electrode 142 in the display area AA.

[0073] The film material of the metal coating can be Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO, and patterned.

[0074] S6. Form a first active layer 133 and a second active layer 143 on the side of the metal coating film facing away from the substrate. The first active layer 133 is disposed on the first source electrode 131 or the first drain electrode 132 , and the second active layer 143 is disposed on the second source electrode 141 or the second drain electrode 142 .

[0075] The first active layer 133 and the second active layer 143 are both oxide semiconductor layers, and the materials may be IGZO, IGTO, IGZO, IGO, IZO, AIZO, ATZO, etc., and the semiconductor layers may be patterned.

[0076] S7. Perform metal coating and patterning on the side of the first active layer 133 facing away from the substrate. The metal coating forms the first drain 132 or the first source 131 in the non-display area NA and forms the second drain 142 or the second source 141 in the display area AA.

[0077] The film material of the metal coating may be Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO.

[0078] S8. An insulating layer is formed and patterned on the side of the interlayer dielectric layer 150 facing away from the substrate to cover the first source electrode 131, the first drain electrode 132 and the first active layer 133. The insulating layer extends from the non-display area NA to the display area, thereby forming a first gate insulating layer 135 and a second gate insulating layer 144 connected to each other.

[0079] The insulating layer coating may be made of SiOx, SiNx, SiNx / SiOx, or SiNOx, and patterned. The patterning of the first gate insulating layer 135 involves etching the first gate insulating layer 135 to form a through hole and continuing the etching process to also etch away a portion of the interlayer dielectric layer 150, thereby exposing the third gate 123.

[0080] S9. Form a metal layer on the side of the insulating layer facing away from the substrate and pattern the metal layer to form a first gate 134 and a second gate 145. The first gate 134 is located in the non-display area NA, and the second gate 145 is located in the display area AA.

[0081] The film material of the metal layer may be Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO.

[0082] S10. A passivation layer 170 is formed on the side of the insulating layer facing away from the substrate. The passivation layer 170 extends from the non-display area NA to the display area to cover the first gate insulating layer 135, the second gate insulating layer 144, the first gate 134, and the second gate 145. The passivation layer 170 is patterned to form a through hole together with the second gate insulating layer 144 to expose the second source electrode 141 or the second drain electrode 142.

[0083] The film material of the passivation layer 170 can be SiOx, SiNx, SiNx / SiOx, or SiNOx.

[0084] S11 . Form a pixel electrode 180 on a side of the passivation layer 170 facing away from the substrate. The pixel electrode 180 is electrically connected to the second source electrode 141 or the second drain electrode 142 through a through hole.

[0085] The material of the pixel electrode 180 can be transparent oxides such as ITO, IZO, AZO, and ZTO.

[0086] The embodiments of the present application further provide a display panel (not shown), which includes the array substrate 100 described in any of the above embodiments. Since the display panel includes the array substrate 100, the display panel also has the structure and beneficial effects of the array substrate 100. The derivation process of the beneficial effects of the display panel will not be repeated here. For details, please refer to the aforementioned description of the embodiment of the array substrate 100.

[0087] It should be noted that, in order to simplify the description of the embodiments of this application and thus facilitate understanding of one or more embodiments, the foregoing description of the embodiments sometimes combines multiple features into a single embodiment, figure, or description thereof. However, this presentation does not mean that the subject matter of this application requires more features than those recited in the claims. In fact, an embodiment may have fewer features than all of the features of a single disclosed embodiment.

Claims

1. An array substrate, characterized in that: The array substrate has a display area and a non-display area located outside the display area, and includes: substrate; a first transistor disposed on the substrate and located in the non-display area, the first transistor comprising a first source electrode, a first drain electrode, and a first active layer, wherein the first source electrode, the first drain electrode, and the first active layer are stacked and the first active layer is located between the first source electrode and the first drain electrode; a second transistor disposed on the substrate and located in the display area, the second transistor comprising a second source electrode, a second drain electrode, and a second active layer, the second source electrode, the second drain electrode, and the second active layer being stacked, and the second active layer being located between the second source electrode and the second drain electrode; Among them, the first transistor and the second transistor are both closed-loop structures, and the second source is set in the same layer and made of the same material as the first source, the second drain is set in the same layer and made of the same material as the first drain, and the first active layer is set in the same layer and made of the same material as the second active layer.

2. The array substrate according to claim 1, wherein: The orthographic projections of the first transistor and the second transistor on the substrate are both circular.

3. The array substrate according to claim 2, wherein: The orthographic projections of the first source electrode, the first drain electrode, and the first active layer on the substrate are all circular, and the radius of the orthographic projection of the first source electrode, the radius of the orthographic projection of the first drain electrode, and the radius of the orthographic projection of the first active layer are all equal; The orthographic projections of the second source, the second drain and the second active layer on the substrate are all circular, and the orthographic radius of the second source, the orthographic radius of the second drain and the orthographic radius of the second active layer are all equal.

4. The array substrate according to claim 3, wherein: The array substrate also includes a third transistor, which is arranged on the substrate and located in the non-display area. The third transistor is electrically connected to the first transistor, and the orthographic projection of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first transistor on the substrate. The third transistor includes a third active layer, and the angle between the channel portion of the first active layer and the plane where the substrate is located is different from the angle between the channel portion of the third active layer and the plane where the substrate is located.

5. The array substrate according to claim 4, wherein: The first source electrode, the first active layer and the first drain electrode are sequentially stacked on the substrate in a direction away from the substrate, and the first source electrode is electrically connected to the conductor portion of the third active layer.

6. The array substrate according to claim 4, wherein: The first transistor also includes a first gate and a first gate insulating layer. The first gate insulating layer is arranged on the substrate and covers the first source, the first drain and the first active layer. The first gate is arranged on the side of the first gate insulating layer away from the substrate and is electrically connected to the third transistor.

7. The array substrate according to claim 6, wherein: The second transistor includes a second gate insulating layer and a second gate. The second gate insulating layer covers the second source, the second drain and the second active layer. The second gate is arranged on a side of the second gate insulating layer away from the substrate.

8. The array substrate according to claim 7, wherein: The first gate insulating layer and the second gate insulating layer are connected in the same layer and made of the same material. The first gate and the second gate are arranged in the same layer and made of the same material.

9. The array substrate according to claim 6, wherein: The orthographic projection of the first gate on the substrate covers a portion of the orthographic projection of the first active layer on the substrate, and a portion of the first gate is aligned with a channel portion in the first active layer.

10. The array substrate according to claim 9, wherein: The orthographic projection of the first gate on the substrate is a circular ring, and the circular ring is coaxially arranged with the circle.

11. The array substrate according to any one of claims 4 to 10, wherein: The third transistor is a low-temperature polysilicon thin film transistor, the first transistor is an oxide thin film transistor, and the first transistor is located on a side of the third transistor away from the substrate.

12. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 11.

Images