Load ground end compensating circuit, arbitrary waveform generator and testing machine

Abstract

The utility model relates to a load ground end compensation circuit, an arbitrary waveform generator and a testing machine, the load ground end compensation circuit comprises a near-end buffer circuit, a filtering gain circuit and a driving circuit, the near-end buffer circuit receives a signal of a load ground end and outputs a buffer signal; the filtering gain circuit carries out filtering and gain processing on the received buffer signal and then transmits the signal to the driving circuit, and the driving circuit receives the signal output by the filtering gain circuit and outputs a driving signal to a tested device so that interference such as noise introduced by wiring between the near-end buffer circuit and the filtering gain circuit can be effectively inhibited. And the NSD, SFDR and THD performances of the arbitrary waveform generator are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a load-ground compensation circuit, an arbitrary waveform generator, and a tester. Background Art

[0002] One type of device under test (DUT) in a digital tester is a hybrid chip, such as an audio ADC or DAC chip. The arbitrary waveform generator (AWG) on the tester serves as a signal source, transmitting analog waveforms such as sine waves to the DUT. Precision digital testers require the AWG to have adequate performance; otherwise, test results will be limited by the signal source. In a common ground system, ground voltage differences between the AWG and the DUT are inevitable due to the impedance of the signal ground (AGND) and ground currents. To eliminate the impact of this ground voltage difference on precision ground-referenced signal measurements, a load ground terminal (DUTGND) is required near the DUT to eliminate shared current paths between the load ground terminal and the signal ground (AGND). Furthermore, this load ground terminal is introduced into the downstream signal conditioning circuitry to compensate for the ground voltage difference and maintain the tester's measurement accuracy and dynamic performance. However, improving the interference immunity of the signal transmission between the load ground terminal (DUTGND) and the downstream signal conditioning circuitry remains a pressing issue. Utility Model Content

[0003] Based on this, it is necessary to provide a load ground compensation circuit, an arbitrary waveform generator and a test machine that can improve the anti-interference ability of signal transmission to address the above problems.

[0004] A first aspect of the present application provides a load ground compensation circuit, comprising:

[0005] a proximal buffer circuit connected to a load ground terminal of the device under test, receiving a signal from the load ground terminal, and outputting a buffered signal;

[0006] a filter gain circuit connected to the proximal buffer circuit and the driving circuit, filtering and gain processing the received buffer signal and then transmitting the signal to the driving circuit;

[0007] The driving circuit is connected to the device under test, receives the signal output by the filter gain circuit, and outputs a driving signal to the device under test.

[0008] In one embodiment, the proximal buffer circuit includes an operational amplifier U10, a resistor R30, a resistor R31, a capacitor C7, and a capacitor C8. The first end of the resistor R30 is connected to the load ground, the second end of the resistor R30 is connected to the first end of the resistor R31 and the first end of the capacitor C7, the second end of the resistor R31 is connected to the non-inverting input of the operational amplifier U10 and the first end of the capacitor C8, the second end of the capacitor C7 is connected to the inverting input and output of the operational amplifier U10, the second end of the capacitor C8 is connected to the signal ground, and the output of the operational amplifier U10 is connected to the filter gain circuit.

[0009] In one embodiment, the filter gain circuit is further connected to a bias signal source, and performs sum processing on the filtered buffer signal and the bias signal output by the bias signal source, and then outputs the sum to the drive circuit after inverting the gain.

[0010] In one embodiment, the filtering gain circuit includes a low-pass filter, a resistor R1, a resistor R3 and an operation unit, the low-pass filter is connected to the proximal buffer circuit and the first end of the resistor R3, the second end of the resistor R3 is connected to the operation unit, the first end of the resistor R1 is connected to the bias signal source, the second end of the resistor R1 is connected to the operation unit, and the operation unit is connected to the driving circuit.

[0011] In one embodiment, the low-pass filter includes a resistor R2 and a capacitor C1, a first end of the resistor R2 is connected to the proximal buffer circuit, a second end of the resistor R2 is connected to the first end of the resistor R3 and the first end of the capacitor C1, and a second end of the capacitor C1 is connected to a signal ground.

[0012] In one embodiment, the operation unit includes an operational amplifier U1, an operational amplifier U2, a resistor R4, a resistor R5, a resistor R6, a capacitor C2 and a capacitor C3, the inverting input terminal of the operational amplifier U1 is connected to the second end of the resistor R3 and the second end of the resistor R1, the non-inverting input terminal of the operational amplifier U1 is connected to the signal ground, the first end of the capacitor C2 is connected to the inverting input terminal of the operational amplifier U1, the second end of the capacitor C2 is connected to the output terminal of the operational amplifier U1, the first end of the resistor R4 is connected to the inverting input terminal of the operational amplifier U1, and the resistor R4 is connected to the output terminal of the operational amplifier U1. The second end of is connected to the output end of the operational amplifier U2, the output end of the operational amplifier U1 is connected to the non-inverting input end of the operational amplifier U2, the first end of the capacitor C3 is connected to the inverting input end of the operational amplifier U2, the second end of the capacitor C3 is connected to the output end of the operational amplifier U2, the first end of the resistor R5 is connected to the inverting input end of the operational amplifier U2 and the first end of the resistor R6, the second end of the resistor R5 is connected to the signal ground, the second end of the resistor R6 is connected to the output end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected to the driving circuit.

[0013] In one embodiment, the driving circuit includes an operational amplifier U3, an operational amplifier U4, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11 and a capacitor C4, a first end of the resistor R7 is connected to the filter gain circuit, a second end of the resistor R7 is connected to the first end of the resistor R8, the first end of the capacitor C4 and the inverting input terminal of the operational amplifier U3, a second end of the capacitor C4 is connected to the output terminal of the operational amplifier U3, a first end of the resistor R9 is connected to the AC signal source, a second end of the resistor R9 is connected to the first end of the resistor R10 and the non-inverting input terminal of the operational amplifier U3, a second end of the resistor R10 is connected to a signal ground, the output terminal of the operational amplifier U3 is connected to the non-inverting input terminal of the operational amplifier U4, the output terminal of the operational amplifier U4 is connected to the first end of the resistor R11, and the second end of the resistor R11 is connected to the inverting input terminal of the operational amplifier U4, the second end of the resistor R8 and the device under test.

[0014] A second aspect of the present application provides an arbitrary waveform generator, comprising an FPGA, a digital-to-analog converter, and the above-mentioned load ground compensation circuit, wherein the FPGA is connected to the load ground compensation circuit via the digital-to-analog converter.

[0015] In one embodiment, the digital-to-analog converter is an AC signal source of an arbitrary waveform generator.

[0016] A third aspect of the present application provides a testing machine, comprising the above-mentioned arbitrary waveform generator.

[0017] The above-mentioned load ground compensation circuit, arbitrary waveform generator and test machine, the load ground compensation circuit includes a proximal buffer circuit, a filter gain circuit and a drive circuit. The proximal buffer circuit receives the signal of the load ground end and outputs a buffered signal. The filter gain circuit filters and performs gain processing on the received buffered signal and then transmits it to the drive circuit. The drive circuit receives the signal output by the filter gain circuit and outputs a drive signal to the device under test. It can effectively suppress interference such as noise introduced by the wiring between the proximal buffer circuit and the filter gain circuit, and improve the anti-interference ability of the ground pressure difference compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a structural block diagram of a load ground terminal compensation circuit in one embodiment;

[0019] Figure 2 FIG. 4 is a structural schematic diagram of a load ground terminal compensation circuit in one embodiment. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0022] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0023] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, operations, components, parts, or combinations thereof.

[0024] In one embodiment, Figure 1As shown, a load ground compensation circuit is provided, including a proximal buffer circuit 110, a filter gain circuit 120 and a drive circuit 130. The proximal buffer circuit 110 is connected to the load ground of the device under test (DUT), receives a signal from the load ground, and outputs a buffered signal; the filter gain circuit 120 is connected to the proximal buffer circuit 110 and the drive circuit 130, filters and performs gain processing on the received buffered signal, and then transmits it to the drive circuit 130; the drive circuit 130 is connected to the device under test (DUT), receives the signal output by the filter gain circuit 120, and outputs a drive signal to the device under test (DUT).

[0025] The device under test (DUT) can be a semiconductor chip or other device. Figure 2 As shown, the device under test (DUT) can be mounted on a load board (DUT Board). The DUT's load ground terminal (DUTGND) is connected to the DUT Board and output to a proximal buffer circuit 110. Proximal buffer circuit 110 performs buffer filtering (e.g., low-pass filtering) on ​​the incoming signal to suppress interference from the load ground terminal (DUTGND) and outputs a buffered signal (DUTGND_BUFF) to a filter gain circuit 120. Filter gain circuit 120 performs low-pass filtering on the received buffered signal (DUTGND_BUFF) before performing operational amplification or attenuation to suppress interference such as noise introduced by the wiring between proximal buffer circuit 110 and filter gain circuit 120.

[0026] The filter gain circuit 120 is further connected to the offset signal source AWG offset source, and performs sum processing on the filtered buffer signal and the offset signal output by the offset signal source AWG offset source, and then outputs the summed signal to the driving circuit 130 after inverting the gain.

[0027] The specific structure of the proximal buffer circuit 110 is not unique. In one embodiment, Figure 2As shown, proximal buffer circuit 110 includes an operational amplifier U10, resistors R30 and R31, capacitors C7, and C8. The first end of resistor R30 is connected to the load ground terminal DUTGND, the second end of resistor R30 is connected to the first end of resistor R31 and the first end of capacitor C7, the second end of resistor R31 is connected to the non-inverting input terminal of operational amplifier U10 and the first end of capacitor C8, the second end of capacitor C7 is connected to the inverting input terminal and the output terminal of operational amplifier U10, the second end of capacitor C8 is connected to signal ground AGND, and the output terminal of operational amplifier U10 is connected to filter gain circuit 120. In proximal buffer circuit 110, resistors R30, R31, capacitors C7, and C8 create two poles within the circuit, providing a low-pass filter that suppresses interference above 1 kHz on the load ground terminal DUTGND. Operational amplifier U10 provides a drive capability of tens of milliamperes for the buffer output. The proximal buffer circuit 110 can be placed at the edge of the AWG board. Specifically, the operational amplifier U10 can be placed within 20 cm of the edge of the AWG board. Each AWG board requires only one proximal buffer circuit 110. The operational amplifier U10, resistors R30 and R31, and capacitors C7 and C8 form a second-order active filter to prevent interference from the load ground terminal DUTGND from spreading and worsening within the board.

[0028] The structure of the filter gain circuit 120 is not unique. In one embodiment, the filter gain circuit 120 includes a low-pass filter 122, resistors R1 and R3, and a computing unit 124. The low-pass filter 122 is connected to the proximal buffer circuit 110 and the first end of the resistor R3. The second end of the resistor R3 is connected to the computing unit 124. The first end of the resistor R1 is connected to the bias signal source AWG offset source, and the second end of the resistor R1 is connected to the computing unit 124. The computing unit 124 is connected to the drive circuit 130. After low-pass filtering of the buffer signal DUTGND_BUFF by the low-pass filter 122, the signal is transmitted to the computing unit 124 via the resistor R3. The computing unit 124 also receives the bias signal offset output by the bias signal source AWG offset source via the resistor R1. After internal summation and inverting amplification or inverting attenuation, the computing unit 124 outputs a combined signal Comb to the drive circuit 130. The digital-to-analog converter (DAC) serves as an AWG offset source. The offset signal from the offset signal source provides a DC component for the AWG drive signal, thereby meeting the common-mode input requirements of the device under test (DUT) in test applications. Low-pass filter 122 may include resistor R2 and capacitor C1. The first end of resistor R2 is connected to proximal buffer circuit 110, specifically to the output of operational amplifier U10. The second end of resistor R2 is connected to the first end of resistor R3 and the first end of capacitor C1. The second end of capacitor C1 is connected to signal ground AGND. This significantly suppresses interference such as noise introduced by long-distance traces, improving NSD, THD, and SFDR performance. It is particularly suitable for large-scale, multi-channel arbitrary signal generator boards.

[0029] The operation unit 124 can be designed as a compound inverting unit to improve the driving capability and maintain low noise. Figure 2The operation unit 124 specifically includes an operational amplifier U1, an operational amplifier U2, a resistor R4, a resistor R5, a resistor R6, a capacitor C2, and a capacitor C3. The inverting input terminal of the operational amplifier U1 is connected to the second end of the resistor R3 and the second end of the resistor R1, the non-inverting input terminal of the operational amplifier U1 is connected to the signal ground AGND, a first end of the capacitor C2 is connected to the inverting input terminal of the operational amplifier U1, a second end of the capacitor C2 is connected to the output terminal of the operational amplifier U1, a first end of the resistor R4 is connected to the inverting input terminal of the operational amplifier U1, a second end of the resistor R4 is connected to the output terminal of the operational amplifier U2, the output terminal of the operational amplifier U1 is connected to the non-inverting input terminal of the operational amplifier U2, a first end of the capacitor C3 is connected to the inverting input terminal of the operational amplifier U2, a second end of the capacitor C3 is connected to the output terminal of the operational amplifier U2, a first end of the resistor R5 is connected to the inverting input terminal of the operational amplifier U2 and the first end of the resistor R6, a second end of the resistor R5 is connected to the signal ground AGND, a second end of the resistor R6 is connected to the output terminal of the operational amplifier U2, and the output terminal of the operational amplifier U2 is connected to the driving circuit 130.

[0030] In filter gain circuit 120, the bias signal "offset" and the buffer signal "DUTGND_BUFF" serve as input signals, and the output signal "Comb" is a combined signal. Operational amplifiers U1 and U2 form a composite inverting amplifier attenuator. The output noise is dominated by the low-noise operational amplifier U1, which sums the input bias signal and the buffer signal. The output drive capability is provided by the high-current output operational amplifier U2. Capacitor C2 provides a zero and a pole at the output of operational amplifier U1. The zero frequency is higher than the pole frequency, allowing operational amplifier U1 to achieve phase margin and stability. Resistors R5 and R6 provide non-inverting amplification capability for operational amplifier U2. Capacitor C3 provides a zero and a pole at the output of operational amplifier U2. The zero frequency is higher than the pole frequency, allowing operational amplifier U2 to achieve phase margin and stability. Operational amplifier U1, resistors R1, and resistors R4 provide inverting amplification for the bias signal "offset," with a gain of k = -R4 / R1. Resistor R2 and capacitor C1 form a first-order low-pass filter (remote filtering of the load ground terminal DUTGND), which suppresses interference such as noise coupled on the buffer signal DUTGND_BUFF trace. Resistor R2 and capacitor C1 are placed within 20cm of the operational amplifier U1. Operational amplifier U1, resistor R2, resistor R3, and resistor R4 provide inverting amplification for the buffer DUTGND_BUFF, with a gain of -R4 / (R2+R3). For the compensation circuit, the gain needs to be 0dB, and R4 is designed to be R2+R3. Therefore, the input-output relationship of the filter gain circuit 120 is V comb =-kV offset -V DUTGND .

[0031] It should be noted that the gain of the bias signal -R4 / R1 and the gain of the buffer signal -R4 / (R2+R3) can be controlled separately. In this article, only the gain of the buffer signal can be set to 0 to ensure that the V output of the filter gain circuit is DUTGND Maintain zero gain.

[0032] Furthermore, the drive circuit 130 can be designed as a composite amplifier drive circuit to improve drive capability and maintain low noise. The drive circuit 130 specifically includes an operational amplifier U3, an operational amplifier U4, resistors R7, R8, R9, R10, R11, and a capacitor C4. The first end of resistor R7 is connected to the filter gain circuit 120, specifically to the output of the operational amplifier U2. The second end of resistor R7 is connected to the first end of resistor R8, the first end of capacitor C4, and the inverting input of the operational amplifier U3. The second end of capacitor C4 is connected to the output of the operational amplifier U3. The first end of resistor R9 is connected to the AC signal source AWGAC source. The second end of resistor R9 is connected to the first end of resistor R10 and the non-inverting input of the operational amplifier U3. The second end of resistor R10 is connected to the signal ground AGND. The output of the operational amplifier U3 is connected to the non-inverting input of the operational amplifier U4. The output of the operational amplifier U4 is connected to the first end of resistor R11. The second end of resistor R11 is connected to the inverting input of the operational amplifier U4, the second end of resistor R8, and the device under test (DUT). The driving circuit 130 may further include a switch S1 , and the second end of the resistor R11 is connected to the device under test DUT through the switch S1 .

[0033] In the driving circuit 130, the AC signal AC of the AC signal source AWG AC source and the combined signal Comb output by the filter gain circuit 120 are used as inputs, and the output driving signal AWG is sent to the device under test DUT. The operational amplifier U3 and the operational amplifier U4 form a composite subtractor. The operational amplifier U3 performs difference processing on the input combined signal Comb and the AC signal AC. The output noise is dominated by the low-noise operational amplifier U3, and the output driving capability is provided by the operational amplifier U4 with high current output capability. The capacitor C4 provides a zero point and a pole for the output of the operational amplifier U3 respectively. The zero point frequency is higher than the pole frequency, so that the operational amplifier U3 obtains phase margin and achieves stability. The resistor R11 limits the current of the operational amplifier U4 to prevent damage to the device. To ensure the accuracy of the AWG output, the inverting input terminal of the operational amplifier U4 is connected to the far end of the resistor R11. The operational amplifier U3, the resistor R7, the resistor R8, the resistor R9 and the resistor R10 form a subtraction function. The input and output relationship of the circuit is:

[0034]

[0035] For the driving circuit 130 , the gain of the AC signal and the combined signal Comb needs to be 0 dB. Therefore, the resistors R7 , R8 , R9 , and R10 are designed to be completely equal. Therefore, the input-output relationship of the circuit is:

[0036] AWG=+V AC -V comb =+V AC +kV offset +V DUTGND

[0037] It can be seen from the expression that the output drive signal AWG increases the voltage difference V between the load ground terminal DUTGND and the signal ground AGND DUTGND , achieving compensation for the single-ended drive signal AWG. The bias signal offset from the bias signal source provides a DC component for the drive signal AWG to meet the input common-mode requirements of the device under test in the test application.

[0038] The load ground compensation circuit provided by this application comprises a proximal buffer circuit 110 that receives the load ground signal and outputs a buffered signal. A filter gain circuit 120 filters and amplifies the received buffered signal before transmitting it to a driver circuit 130. This circuit effectively suppresses interference such as noise introduced by the wiring between proximal buffer circuit 110 and filter gain circuit 120. This application optimizes the load ground compensation circuit DUTGND, reducing the negative impacts of NSD, THD, and SFDR on large, multi-channel AWG boards. It also improves driver circuit 130, ensuring that the AWG output has both low noise and high drive capability, and compensates the buffered signal DUTGND_BUFF to the device under test (DUT) in a zero-gain manner.

[0039] In one embodiment, Figure 2 As shown, an arbitrary waveform generator is also provided, including an FPGA, a digital-to-analog converter, and the above-mentioned load-ground compensation circuit, wherein the FPGA is connected to the load-ground compensation circuit via the digital-to-analog converter. The digital-to-analog converter is the AC signal source AWG AC source of the arbitrary waveform generator.

[0040] In one embodiment, a test machine is further provided, including the above-mentioned arbitrary waveform generator. The test machine may be a digital test machine.

[0041] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A load ground compensation circuit, characterized in that: include: a proximal buffer circuit connected to a load ground terminal of the device under test, receiving a signal from the load ground terminal, and outputting a buffered signal; a filter gain circuit connected to the proximal buffer circuit and the driving circuit, filtering and gain processing the received buffer signal and then transmitting the signal to the driving circuit; The driving circuit is connected to the device under test, receives the signal output by the filter gain circuit, and outputs a driving signal to the device under test.

2. The circuit according to claim 1, characterized in that The proximal buffer circuit includes an operational amplifier U10, a resistor R30, a resistor R31, a capacitor C7, and a capacitor C8. The first end of the resistor R30 is connected to the load ground, the second end of the resistor R30 is connected to the first end of the resistor R31 and the first end of the capacitor C7, the second end of the resistor R31 is connected to the non-inverting input of the operational amplifier U10 and the first end of the capacitor C8, the second end of the capacitor C7 is connected to the inverting input and output of the operational amplifier U10, the second end of the capacitor C8 is connected to the signal ground, and the output of the operational amplifier U10 is connected to the filter gain circuit.

3. The circuit according to claim 1, wherein: The filter gain circuit is also connected to a bias signal source, performs sum processing on the filtered buffer signal and the bias signal output by the bias signal source, and then outputs the sum to the drive circuit after inverting the gain.

4. The circuit according to claim 1, wherein: The filtering gain circuit includes a low-pass filter, a resistor R1, a resistor R3 and a computing unit. The low-pass filter is connected to the proximal buffer circuit and the first end of the resistor R3, the second end of the resistor R3 is connected to the computing unit, the first end of the resistor R1 is connected to the bias signal source, the second end of the resistor R1 is connected to the computing unit, and the computing unit is connected to the driving circuit.

5. The circuit according to claim 4, characterized in that The low-pass filter includes a resistor R2 and a capacitor C1. The first end of the resistor R2 is connected to the proximal buffer circuit, the second end of the resistor R2 is connected to the first end of the resistor R3 and the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the signal ground.

6. The circuit according to claim 4, characterized in that The operation unit includes an operational amplifier U1, an operational amplifier U2, a resistor R4, a resistor R5, a resistor R6, a capacitor C2 and a capacitor C3. The inverting input terminal of the operational amplifier U1 is connected to the second end of the resistor R3 and the second end of the resistor R1. The non-inverting input terminal of the operational amplifier U1 is connected to the signal ground. The first end of the capacitor C2 is connected to the inverting input terminal of the operational amplifier U1. The second end of the capacitor C2 is connected to the output terminal of the operational amplifier U1. The first end of the resistor R4 is connected to the inverting input terminal of the operational amplifier U1. The second end of the resistor R4 is connected to the The first end of the capacitor C3 is connected to the inverting input of the operational amplifier U2, the second end of the capacitor C3 is connected to the output of the operational amplifier U2, the first end of the resistor R5 is connected to the inverting input of the operational amplifier U2 and the first end of the resistor R6, the second end of the resistor R5 is connected to the signal ground, the second end of the resistor R6 is connected to the output of the operational amplifier U2, and the output of the operational amplifier U2 is connected to the drive circuit.

7. The circuit according to claim 1, wherein: The driving circuit includes an operational amplifier U3, an operational amplifier U4, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11 and a capacitor C4, a first end of the resistor R7 is connected to the filter gain circuit, a second end of the resistor R7 is connected to the first end of the resistor R8, the first end of the capacitor C4 and the inverting input terminal of the operational amplifier U3, a second end of the capacitor C4 is connected to the output terminal of the operational amplifier U3, a first end of the resistor R9 is connected to the AC signal source, a second end of the resistor R9 is connected to the first end of the resistor R10 and the non-inverting input terminal of the operational amplifier U3, a second end of the resistor R10 is connected to the signal ground, the output terminal of the operational amplifier U3 is connected to the non-inverting input terminal of the operational amplifier U4, the output terminal of the operational amplifier U4 is connected to the first end of the resistor R11, and the second end of the resistor R11 is connected to the inverting input terminal of the operational amplifier U4, the second end of the resistor R8 and the device under test.

8. An arbitrary waveform generator, characterized in that: The device comprises an FPGA, a digital-to-analog converter and the load ground compensation circuit according to any one of claims 1 to 7, wherein the FPGA is connected to the load ground compensation circuit via the digital-to-analog converter.

9. The arbitrary waveform generator according to claim 8, characterized in that: The digital-to-analog converter is the AC signal source of the arbitrary waveform generator.

10. A testing machine, characterized in that: The arbitrary waveform generator comprising claim 8 or 9.

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