Stacked quantum chip supporting structure

Abstract

The utility model discloses a stacked quantum chip supporting structure. The stacked quantum chip supporting structure comprises a first chip and a second chip, a cut-off layer is arranged on the end face between the first chip and the second chip, the cut-off layer is provided with multiple sets of limiting columns, and the first chip and the one or more second chips are aligned and bonded through the limiting columns to form a multi-layer stacked structure. According to the utility model, a plurality of groups of limiting columns are arranged at the corresponding positions of one or more cut-off layers between chips, so that the stress can be better balanced without influencing the wiring of the chips, the stress is more uniform and the chips are not deformed when the chips are subjected to flip-chip bonding or stacking design, and the sizes of the gaps between the chips can be determined by controlling the heights of the limiting columns, so that the yield of the chips is improved. Gaps and design are ensured to be consistent, and the problems of inclination, collapse and the like after multiple layers of chips are stacked are effectively solved; in addition, a lantern ring structure is formed by mutually embedding and connecting the coating cavities, so that the supporting stability is further improved, interconnected metal can be effectively prevented from overflowing to influence an external circuit structure, and the gap distance between the chips can be accurately controlled.

Description

Technical Field

[0001] The utility model relates to the technical field of superconducting quantum computing chips, and in particular to a stacked quantum chip support structure. Background Art

[0002] In the development of superconducting quantum computing, as the number of quantum bits increases, quantum chips are gradually transitioning from a two-dimensional planar structure to a three-dimensional structure, further improving the chip's integration. However, since the interconnection metal must be made of superconducting materials, and when the metal has a high melting point, it will cause annealing of the Josephson junction during thermal bonding, which in turn affects bit performance. Therefore, in the field of superconducting quantum chips, soft metals (such as indium) are more commonly used as interconnection metals to achieve flip-chip interconnection.

[0003] With the development of three-dimensional structure technology, flip-chip bonding equipment is needed to bond two chips together. Flip-chip bonding technology uses a pressing material to press together two chips at a certain pressure and temperature to form a single chip. Currently, metal plating is often performed using a thermal evaporation process, which makes the formed metal balls uneven. During interconnection, the uneven force will cause the chip gap to be inconsistent with the design requirements, and it is prone to significant compression deformation and tilt at a certain angle. As the number of quantum bits increases, when chips need to be stacked in multiple layers, when bonding is performed through multiple flip-chip bonding, each bonding will be affected, resulting in a gradual increase in gap deviation and self-capacitance deviation. This will in turn cause changes in the quantum bit frequency, the coupling capacitance between the XY line and the bit, and the capacitance between the read resonant cavity and the bit, affecting the reading conditions and the Purcell attenuation limit imposed on the quantum bit. Utility Model Content

[0004] The purpose of the present invention is to solve the above problems and provide a stacked quantum chip support structure.

[0005] In order to achieve the above objectives, the present invention adopts the following technical solution: a stacked quantum chip support structure, comprising:

[0006] a first chip and a second chip;

[0007] A cutoff layer is provided between the first chip and the second chip, and the cutoff layer is provided with multiple groups of limiting pillars. The first chip and one or more second chips are aligned and bonded through the limiting pillars to form a stacked structure.

[0008] In some embodiments, the cutoff layer is provided with one or more layers.

[0009] In some embodiments, the limiting pillar is disposed on the cutoff layer of the first chip or the second chip.

[0010] In some embodiments, the limiting pillars are disposed on the cutoff layers of the first chip and the second chip.

[0011] In some embodiments, the limiting column is a solid and / or hollow column.

[0012] In some embodiments, a group of the limiting posts is surrounded by multiple groups of limiting posts of the same and / or different shapes.

[0013] In some embodiments, the limiting pillars include a first supporting portion, and a plurality of first supporting portions are arranged around the first chip and / or the second chip.

[0014] In some embodiments, the limiting column further includes a second supporting portion, and the second supporting portion is disposed at the center of the first chip and / or the second chip.

[0015] In some embodiments, one group of the limiting posts is provided with a covering cavity, and the outer contour of the corresponding other group of the limiting posts fits the inner contour of the covering cavity.

[0016] In some embodiments, the limiting column provided with the covering cavity covers the outside of the limiting column not provided with the covering cavity, and the limiting columns are bonded to form a ring.

[0017] In some embodiments, the limiting pillars on the two stop layers are made of different materials.

[0018] The utility model has the following beneficial effects:

[0019] 1. The utility model sets multiple groups of limit posts at corresponding positions of one or more cut-off layers between chips, which can better balance stress without affecting chip wiring, ensuring that the chips are more evenly stressed and will not deform during flip-chip soldering or stacking design. The size of the chip gap can be determined by controlling the height of the limit posts to ensure that the gap is consistent with the design, effectively solving problems such as tilting and collapse after multi-layer chip stacking, and realizing the stacking design and processing of two or more layers of chips.

[0020] 2. The present invention adopts a structure of a ring formed by interlocking two sets of limiting pillars through a covering cavity, which further improves the support stability, effectively prevents the overflow of interconnected metal from affecting the external circuit structure, and accurately controls the gap distance between chips.

[0021] In order to more clearly illustrate the structural features and functions of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1Schematic diagram of the structure of the stacked quantum chip support structure provided in the embodiment of the present application Figure 1 ;

[0023] Figure 2 A schematic diagram of the structure of a double-layer chip design provided in one embodiment of the present application Figure 2 ;

[0024] Figure 3 A schematic diagram of the structure of a double-layer chip design provided in one embodiment of the present application Figure 1 ;

[0025] Figure 4 A schematic diagram of the structure of a double-layer chip design provided in one embodiment of the present application Figure 2 ;

[0026] Figure 5 A schematic diagram of the structure of a multi-layer chip design solution provided in one embodiment of the present application;

[0027] Figure 6 A schematic structural diagram of the support column collar design provided in one embodiment of the present application.

[0028] Reference numerals:

[0029] 1. First chip; 11. First supporting area; 2. Second chip; 21. Second supporting area; 3. Support member; 31. First supporting portion; 32. Second supporting portion. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0031] See Figures 1-6 As shown, the present invention provides an embodiment of a support structure for stacked quantum chips. The specific structure includes: a first chip 1 and a second chip 2. A cutoff layer 3 is provided between the first chip 1 and the second chip 2. The cutoff layer 3 is provided with multiple groups of vapor-deposited limiting pillars 31. The limiting pillars 31 allow the first chip 1 and one or more second chips 2 to be aligned and bonded to form a stacked structure, thereby supporting and limiting the chip structure, ultimately enabling the design and processing of stacked two or more layers of chips.

[0032] It is understandable that the cutoff layer 3 may be optionally provided with one or more layers, and the specific number of layers is selected according to processing parameters such as the spacing when the chips are stacked.

[0033] Furthermore, the limiting posts 31 are arranged around the cutoff layer 3 of the first chip 1 and / or the second chip 2. For example, the limiting posts 31 can be arranged at the center and four edges of the first chip 1 or the second chip 2, thereby avoiding the wiring area of ​​the chip, ensuring that the circuit structure of the chip is not affected, and can adapt to different stacking structures and stacking spacings according to different stacking schemes when performing flip-chip bonding or multi-layer stacking.

[0034] At the same time, the limiting pillars 31 of different positions and numbers can separate the large wiring area of ​​the end faces of the first chip 1 and the second chip 2 into multiple small wiring areas. Different wiring areas can improve the reliability and stability of the chip as needed. By rationally planning the double-row pin settings at each edge of the wiring layer, and connecting these pins with the control line port array and the reading cavity port array in the core area of ​​the wiring layer, automatic and efficient wiring can be achieved, thereby improving the overall performance and reliability of the quantum chip.

[0035] Furthermore, the limiting column 31 is a solid and / or hollow column, which can be flexibly selected for different stacking design schemes;

[0036] In addition, a group of limiting pillars 31 may be surrounded by multiple groups of limiting pillars of the same and / or different shapes, which can be flexibly selected and adapted according to the routing schemes of different chips.

[0037] Specifically, the limiting pillars may be prisms, cylinders, pyramids or other cylindrical bodies, and the limiting pillars at different positions may have the same or different shapes, thereby adapting to regular / heterogeneous chip layouts.

[0038] Furthermore, the limiting pillar 31 includes a first supporting portion 311, and multiple groups of the first supporting portions 311 are arranged around the first chip 1 and / or the second chip 2, and can be flexibly arranged on the overlapping surface between the corresponding two groups of chips according to the overlapping scheme.

[0039] Optionally, the limiting pillar 31 further includes a second supporting portion 312 , and the second supporting portion 312 is disposed at a center position of the first chip 1 and / or the second chip 2 .

[0040] For example, the first support portions 311 can be symmetrically arranged at equal distances along the four edges of the first chip 1 or the second chip 2, and the plurality of second support portions 312 can be symmetrically arranged relative to the center point of the first support portion 311. By providing the limiting posts 31 at the center, four sides, and edges of the support area, the stress between the chips can be better balanced, ensuring that the chips are subjected to more uniform stress and will not deform or tilt during flip-chip soldering or stacking. In addition, the size of the chip gap can be determined by controlling the height of the limiting posts 31 to ensure that the gap is consistent with the gap of the coupling capacitor design.

[0041] Furthermore, when the cutoff layer 3 is provided with multiple layers, the limiting pillars 31 on two adjacent groups of cutoff layers 3 can be bonded to each other, and the gap distance between the chips during bonding can be determined according to the height of the limiting pillars 31 .

[0042] For example, when two layers of cut-off layers 3 are correspondingly arranged between the first chip 1 and the second chip 2, a coating cavity is provided at the end of one group of limiting columns 31, and the outer contour of the other group of limiting columns 31 correspondingly bonded fits the inner contour of the coating cavity, and the limiting columns 31 with the coating cavity and the limiting columns 31 without the coating cavity are made of different materials; in this way, when the chips are bonded, the limiting columns 31 with the coating cavity can be coated on the outside of the other group of limiting columns 31, and a ring is formed by bonding, which can effectively prevent the overflow of interconnected metal from affecting the external circuit structure and accurately control the gap distance between the chips.

[0043] Currently, metal plating is often carried out using a thermal evaporation process, which results in uneven metal balls. During interconnection, uneven force will cause the chip gap to be inconsistent with the design requirements, and it is easy to cause obvious compression deformation and tilt at a certain angle. To overcome the above technical problems, refer to Figure 2 As shown, in a specific embodiment, a limiting column 31 is formed by evaporation on the surface of the superconducting quantum chip to be bonded prepared by wafer. The limiting column 31 is arranged in the center and the surrounding edge of the superconducting quantum chip cutoff layer 3; the limiting column 31 is made of superconducting metal or superconducting material with low loss junction dielectric, such as hard conductive metal (Sn, Al and Au, etc.) or hard compound (SiO2, TiN and SiN, etc.), which has high mechanical strength and stability, can effectively support and fix the structure of the superconducting quantum chip, good thermal conductivity helps to manage and disperse the heat generated in the quantum chip, and high oxidation resistance and chemical stability can work stably in the operating environment of superconducting quantum computing for a long time, which can improve the stability and performance of the chip.

[0044] Exemplarily, the limiting column 31 is formed by photolithography patterning followed by evaporation of material. The shape of the limiting column 31 can be a square column, a round column, or other regular or irregular shaped columns. The specific shape depends on the chip wiring space and actual processing requirements.

[0045] See Figure 3As shown, in another specific embodiment, for a double-layer chip design, when the height range of a single-layer limiting column 31 can meet the gap height requirement, the limiting column 31 may not be set on the first chip 1, and the limiting column 31 may be set on the second chip 2. The first chip 1 and the second chip 2 are aligned and bonded together by flip-chip method to form a stacked structure, and the gap height is determined by the height of a layer of limiting columns 31. The limiting columns 31 can play a supporting and limiting role to ensure that the chip gap distance and the gap of the coupling capacitor design are consistent.

[0046] See Figure 4 As shown, in another specific embodiment, for a double-layer chip design, when the height range of a single-layer limiting column 31 cannot meet the gap height requirement, a limiting column 31 can be set on the first chip 1, and a limiting column 31 can be set on the second chip 2. The first chip 1 and the second chip 2 are aligned and bonded together by flip-chip method to form a stacked structure, and the gap height is jointly determined by the height of the two layers of limiting columns 31. The limiting columns 31 can play a supporting and limiting role to ensure that the chip gap distance and the gap of the coupling capacitor design remain consistent.

[0047] See Figure 5 As shown, in another specific embodiment, for a multi-layer chip stacking design, the first chip 1 is not provided with a limiting column 31, and the second chip 2 is provided with a limiting column 31. The first chip 1 and the second chip 2 are aligned and bonded together in a flip-chip manner to form a stacking structure, and then multiple groups of second chips 2 are bonded to the stacked structure in sequence. In this process, the first chip 1 and the second chip 2 that are first bonded at the bottom will be continuously squeezed. After alignment and bonding are achieved through the limiting column 31, the upper and lower support columns can be well aligned, and the gap distance can be determined according to the height of the limiting column 31. For chips with three layers or more, the stacking structure that is bonded multiple times is continuously compressed. The limiting member can effectively prevent the tilting and collapse after multiple stacking to cause damage to the chip.

[0048] See Figure 6 As shown, in another specific embodiment, the limiting post 31 of the first chip 1 is provided with a covering cavity, the inner contour of which fits the limiting post 31 of the second chip 2; and the limiting post 31 of the first chip 1 can be a superconducting metal or a superconducting material of a low-loss junction dielectric (Sn, Al, Au, SiO2, TiN and SiN, etc.), while the limiting post 31 of the second chip 2 can be an existing connecting metal (In, etc.). In this way, during bonding, the limiting post 31 at the top can be completely covered on the outside of the limiting post 31 at the bottom to form a collar design, which can effectively prevent the overflow of the interconnected metal from affecting the external circuit structure and accurately control the gap distance between the chips.

[0049] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A stacked quantum chip support structure, characterized in that: include: A first chip (1) and a second chip (2); A cutoff layer (3) is provided between the first chip (1) and the second chip (2), the cutoff layer (3) being provided with a plurality of groups of limiting pillars (31), and the first chip (1) and one or more second chips (2) are aligned and bonded via the limiting pillars (31) to form a stacked structure.

2. A stacked quantum chip support structure according to claim 1, characterized in that: The cut-off layer (3) is provided with one or more layers.

3. A stacked quantum chip support structure according to claim 2, characterized in that: The limiting column (31) is arranged on the cutoff layer (3) of the first chip (1) or the second chip (2).

4. A stacked quantum chip support structure according to claim 2, characterized in that: The limiting pillars (31) are arranged on the cutoff layers (3) of the first chip (1) and the second chip (2).

5. A stacked quantum chip support structure according to claim 4, characterized in that: The limiting column (31) is a solid and / or hollow column.

6. A stacked quantum chip support structure according to claim 4, characterized in that: A group of the limiting posts (31) is surrounded by multiple groups of limiting posts (31) with the same and / or different shapes.

7. The stacked quantum chip support structure according to claim 4, characterized in that: The limiting column (31) comprises a first supporting portion (311), and a plurality of first supporting portions (311) are arranged around the first chip (1) and / or the second chip.

8. The stacked quantum chip support structure according to claim 4, characterized in that: The limiting column (31) further includes a second supporting portion (312), and the second supporting portion (312) is arranged at the center of the first chip (1) and / or the second chip.

9. The stacked quantum chip support structure according to claim 4, characterized in that: One group of the limiting posts (31) is provided with a covering cavity, and the outer contour of the corresponding other group of the limiting posts (31) fits the inner contour of the covering cavity.

10. The stacked quantum chip support structure according to claim 9, characterized in that: The limiting column (31) provided with the covering cavity covers the outside of the limiting column (31) not provided with the covering cavity, and the limiting columns (31) are bonded to form a collar.

11. The stacked quantum chip support structure according to claim 1, characterized in that: The materials of the limiting columns (31) on the two stop layers (3) are different.

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