Anti-reverse protection circuit capable of keeping low standby quiescent current

Abstract

The utility model relates to an anti-reverse protection circuit capable of keeping low standby quiescent current. The anti-reverse protection circuit comprises an MOS tube Q1, a voltage-regulator tube D1, a first resistor R1, a triode Q2, a second resistor R2, a diode D2, a third resistor R3, a fourth resistor R4 and a power management module. The negative electrode of the voltage-regulator tube D1 is connected with the source electrode of the MOS tube Q1, the positive electrode of the voltage-regulator tube D1 is connected with the grid electrode of the MOS tube Q1, and the first end of the first resistor R1 is connected with the source electrode of the MOS tube Q1. According to the anti-reverse protection circuit for keeping the low standby quiescent current, when the electronic equipment works normally, the MOS tube is conducted bidirectionally, so that lower on-resistance is obtained, and the power supply of the equipment is in an optimal working state; when the electronic equipment is in a standby state, the grid electrode of the P-channel MOS tube is disconnected with the GND, so that basically no current passes through each component in the anti-reverse circuit, and a relatively low standby quiescent current is obtained.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to an anti-reverse protection circuit for maintaining low standby static current. Background Art

[0002] For automotive electronic equipment, in order to prevent damage when the battery is mistakenly connected in reverse, an anti-reverse protection design must be included in the power circuit. Before the positive and negative poles of the battery are connected to the power management circuit of the device, the anti-reverse protection circuit protects the polarized capacitors and ICs in the back-end circuit from reverse breakdown.

[0003] The simplest form of anti-reverse circuit for automotive electronic equipment is to use a diode for anti-reverse. This form is very low cost, but it is only suitable for applications with low currents of 1~2A. For high current applications, anti-reverse circuits usually have the following forms:

[0004] 1. Use N-channel MOS tube on the low side of the power supply to prevent reverse, but this form is rarely used in practice because it separates the power ground and the load ground;

[0005] 2. Use P-channel MOS tube on the high side of the power supply to prevent reverse, such as Figure 1 This form is widely used in practice, but its main disadvantage is that the standby quiescent current is large, usually more than 2mA;

[0006] 3. Use a dedicated driver IC plus a P-channel or N-channel MOS tube for anti-reverse operation. This form of standby static current can be made very low, usually within 10~50 uA, but the disadvantage is that the cost of the dedicated IC is relatively high. Utility Model Content

[0007] To this end, the technical problem addressed by this utility model is to overcome the existing technical problem that modern automobiles contain a large number of electronic devices. If many of these electronic devices have high standby quiescent currents, this will undoubtedly put pressure on the vehicle battery, causing continuous high battery power consumption while the vehicle is stopped. Over time, this will shorten the battery life and affect the normal starting of the vehicle. The aforementioned third type of anti-reverse protection circuit cannot completely replace the second type of anti-reverse protection circuit due to the high price of the dedicated IC and the greater risk of stock shortages. Therefore, how to reduce the standby quiescent current of the P-channel MOS tube anti-reverse protection circuit is a technical problem that needs to be solved urgently.

[0008] In order to solve the above technical problems, the utility model provides an anti-reverse protection circuit for maintaining low standby static current, comprising: a MOS tube Q1, a voltage regulator tube D1, a first resistor R1, a transistor Q2, a second resistor R2, a diode D2, a third resistor R3, a fourth resistor R4 and a power management module; wherein the source of the MOS tube Q1 is connected to the power management module at the back end, the negative electrode of the voltage regulator tube D1 is connected to the source of the MOS tube Q1, and the positive electrode of the voltage regulator tube D1 is connected to the gate of the MOS tube Q1, and the first end of the first resistor R1 is connected to the The source of the MOS transistor Q1 is connected, and the second end of the first resistor R1 is connected to the gate of the MOS transistor Q1. The collector of the transistor Q2 is connected to the gate of the MOS transistor Q1 through the second resistor R2. The emitter of the transistor Q2 is connected to GND. The anode of the diode D1 is connected to VCC, and the cathode of the diode D2 is connected to the base of the transistor Q2 through the third resistor R3. The first end of the fourth resistor R4 is connected to the base of the transistor Q2, and the second end of the fourth resistor R4 is connected to the emitter of the transistor Q2. The utility model discloses an anti-reverse protection circuit for maintaining low standby quiescent current. When the electronic device is in normal operation, the gate of the P-channel MOS tube is connected to GND through the circuit setting, so that the MOS tube is bidirectionally conductive, thereby obtaining a low on-resistance and keeping the power supply of the device in an optimal working state. When the electronic device is in standby mode, the gate of the P-channel MOS tube is disconnected from GND, so that basically no current flows through the various components in the anti-reverse protection circuit, thereby obtaining a low standby quiescent current.

[0009] In one embodiment of the present invention, the drain of the MOS transistor Q1 is connected to the positive power supply electrode.

[0010] In one embodiment of the present invention, the GND is connected to the negative power supply electrode.

[0011] In one embodiment of the present invention, the anode of the diode D2 is connected to the VCC of the power management module.

[0012] In one embodiment of the present invention, the VCC value of the power management module is 5V or 3.3V.

[0013] In one embodiment of the present invention, the MOS transistor Q1 is a P-channel MOS transistor.

[0014] In one embodiment of the present invention, the transistor Q2 is an NPN transistor.

[0015] In one embodiment of the present invention, the power management module is connected to a switch signal.

[0016] In one embodiment of the present invention, the diode D2 and the third resistor R3 are connected in series.

[0017] The above technical solution of the utility model has the following beneficial effects compared with the prior art:

[0018] The anti-reverse protection circuit for maintaining low standby quiescent current described in the utility model adopts the structure of a high-side P-channel MOS transistor and adds a circuit capable of controlling the gate of the P-channel MOS transistor. The low standby quiescent current control method is as follows: when the electronic device is in normal operation, the gate control circuit connects the connection between the gate of the P-channel MOS transistor and GND, making the MOS transistor bidirectionally conductive, thereby obtaining a low on-resistance and ensuring that the power supply of the device is in an optimal working state; when the electronic device is in standby mode, the gate control circuit disconnects the connection between the gate of the P-channel MOS transistor and GND, thereby obtaining a low standby quiescent current. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the content of the utility model easier to understand, the utility model is further described in detail below based on the specific embodiments of the utility model and in conjunction with the accompanying drawings, wherein

[0020] Figure 1 This is a circuit diagram of an anti-reverse protection circuit for maintaining low standby quiescent current in a preferred embodiment of the present invention.

[0021] Description of the accompanying drawings in the specification: MOS tube Q1, voltage regulator tube D1, first resistor R1, transistor Q2, second resistor R2, diode D2, third resistor R3, fourth resistor R4, power management module 100. DETAILED DESCRIPTION

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention.

[0023] Reference Figure 1As shown, the anti-reverse protection circuit for maintaining low standby static current of the present invention includes: a MOS tube Q1, a voltage regulator tube D1, a first resistor R1, a transistor Q2, a second resistor R2, a diode D2, a third resistor R3, a fourth resistor R4 and a power management module 100; wherein, the source of the MOS tube Q1 is connected to the power management module 100 at the back end, the negative electrode of the voltage regulator tube D1 is connected to the source of the MOS tube Q1, and the positive electrode of the voltage regulator tube D1 is connected to the gate of the MOS tube Q1, and the first end of the first resistor R1 is connected to the source of the MOS tube Q1 , and the second end of the first resistor R1 is connected to the gate of the MOS transistor Q1, the collector of the transistor Q2 is connected to the gate of the MOS transistor Q1 through the second resistor R2, the emitter of the transistor Q2 is connected to GND, the anode of the diode D1 is connected to VCC, and the cathode of the diode D2 is connected to the base of the transistor Q2 through the third resistor R3, the diode D2 and the third resistor R3 are connected in series, the first end of the fourth resistor R4 is connected to the base of the transistor Q2, and the second end of the fourth resistor R4 is connected to the emitter of the transistor Q2.

[0024] The drain of the MOS transistor Q1 is connected to the positive power supply electrode. The GND is connected to the negative power supply electrode. The MOS transistor Q1 is a P-channel MOS transistor. The transistor Q2 is an NPN transistor.

[0025] In addition, the anode of the diode D2 is connected to the VCC of the power management module 100. VCC is output by the power management module 100 of the electronic device during normal operation, and is generally 5V or 3.3V.

[0026] In addition, the power management module 100 is connected to a switch signal.

[0027] According to the above circuit, the control method of the anti-reverse protection circuit for maintaining low standby quiescent current of the present invention includes the following:

[0028] When the device is in standby mode, the power management module 100 of the device does not output VCC, and VCC is 0V. At this time, the transistor Q2 is in the cut-off state, thereby disconnecting the gate of the MOS transistor Q1 from GND. Basically, no current flows through the components described in the anti-reverse protection circuit 200. The standby static current is approximately equal to the leakage current of the transistor Q2, which is approximately 0.1~5 uA, achieving a low standby static current.

[0029] When the device is awakened by the switch signal, the power management module 100 enters a normal working state and outputs VCC. At this time, the transistor Q2 operates in an amplification or saturation state, thereby connecting the gate of the MOS transistor Q1 to GND. The MOS transistor Q1 is bidirectionally conductive, thereby obtaining a lower on-resistance, so that the power supply of the device is in an optimal working state.

[0030] When the power supply is reversed, the transistor Q2 is in the cut-off state, the diode D2 is also reversely cut off, the drain and source of the MOS tube Q1 are in the cut-off state, and the parasitic diode of the MOS tube Q1 is also in the reverse cut-off state. The anti-reverse protection circuit realizes anti-reverse protection, and basically no current passes through each component, and the standby static current is also approximately equal to zero.

[0031] The present invention provides a control method for an anti-reverse protection circuit that maintains a low standby quiescent current. The transistor Q2 in the anti-reverse protection circuit may also be other components with voltage-controlled switching characteristics, such as relays, MOS transistors, or switch ICs. The anode of the diode D2 may also be connected not to VCC but to other ports that can be powered off when the device is in standby mode and powered when the device is operating, such as an IO port on the device's main control chip. The device software controls the output of high-level (5V or 3.3V) and low-level (0V) states to achieve the low standby quiescent current control proposed by the present invention.

[0032] Compared with the typical P-channel MOS tube anti-reverse protection circuit, the method proposed in the utility model can reduce the standby static current to about 0.1~5 uA, which is comparable to the anti-reverse protection circuit using a dedicated IC, and has a lower implementation cost.

[0033] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A reverse protection circuit for maintaining low standby quiescent current, characterized in that: include: MOS transistor Q1, voltage regulator transistor D1, first resistor R1, transistor Q2, second resistor R2, diode D2, third resistor R3, fourth resistor R4 and power management module; The source of the MOS transistor Q1 is connected to a back-end power management module, the cathode of the voltage regulator D1 is connected to the source of the MOS transistor Q1, and the anode of the voltage regulator D1 is connected to the gate of the MOS transistor Q1. The first end of the first resistor R1 is connected to the source of the MOS transistor Q1, and the second end of the first resistor R1 is connected to the gate of the MOS transistor Q1. The collector of the transistor Q2 is connected to the gate of the MOS transistor Q1 through the second resistor R2, and the emitter of the transistor Q2 is connected to GND. The anode of the diode D1 is connected to VCC, and the cathode of the diode D2 is connected to the base of the transistor Q2 through the third resistor R3. The first end of the fourth resistor R4 is connected to the base of the transistor Q2, and the second end of the fourth resistor R4 is connected to the emitter of the transistor Q2.

2. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 1, characterized in that: The drain of the MOS tube Q1 is connected to the positive power supply electrode.

3. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 1, characterized in that: The GND is connected to the negative power supply electrode.

4. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 1, characterized in that: The anode of the diode D2 is connected to the VCC of the power management module.

5. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 4, characterized in that: The VCC value of the power management module is 5V or 3.3V.

6. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 1, characterized in that: The MOS transistor Q1 is a P-channel MOS transistor.

7. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 1, characterized in that: The transistor Q2 is an NPN transistor.

8. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 1, characterized in that: The power management module is connected to a switch signal.

9. The anti-reverse protection circuit for maintaining low standby quiescent current according to claim 1, characterized in that: The diode D2 and the third resistor R3 are connected in series.

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