Three-dimensional fan-out type packaging structure
By introducing a supporting substrate and metal column structure into the three-dimensional fan-out packaging structure, the gap can be filled with plastic packaging at one time, solving the problems of complicated processes and low reliability, reducing costs and improving the stability and heat dissipation of the chip.
Patent Information
- Application Number
- CN202422841335.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-10-10
- Estimated Expiration
- 2034-11-20
AI Technical Summary
The existing three-dimensional fan-out packaging structure has complicated processes, high costs and low chip reliability. Multiple plastic packaging and rewiring lead to thermal expansion coefficient mismatch and bump solder joint fatigue damage.
A support substrate and a first metal pillar structure are used. By adjusting the distance between the support substrate and the first chip, a one-time plastic package is implemented to fill the gap, simplifying the process, avoiding damage to the bump solder joints caused by thermal expansion coefficient mismatch and high-temperature baking, and using a single wiring substrate to replace the traditional redistribution layer.
The process is simplified, the manufacturing cost is reduced, the stability and heat dissipation effect of the chip are improved, the stability and reliability of the packaging structure are ensured, and it is suitable for mass production.
Smart Images
Figure CN223427490U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductor packaging and relates to a three-dimensional fan-out packaging structure. Background Art
[0002] With the advent of the 5G communications and artificial intelligence (AI) era, the amount of data that chips used in these related fields need to transmit and process at high speed is enormous. Such chips typically have a huge number of pad pins (hundreds or even thousands), and ultra-fine pin sizes and spacing (a few microns or even smaller). On the other hand, demand for mobile Internet and the Internet of Things is becoming increasingly strong, and the miniaturization and multifunctionality of electronic terminal products have become a major trend in industrial development. How to integrate and package multiple different types of high-density chips together to form a powerful system or subsystem with relatively small size and power consumption has become a major challenge in the field of advanced semiconductor chip packaging.
[0003] Currently, for multi-chip integrated packaging of such high-density chips, the industry typically uses methods such as through-silicon vias (TSVs) and silicon interposers to lead out and effectively interconnect the chip's ultra-fine pins to form a functional module or system. However, this technology is relatively expensive, which greatly limits its scope of application. Fan-out packaging technology, which uses wafer reconstruction and rewiring of RDLs, provides a good platform for achieving multi-chip integrated packaging. However, existing fan-out packaging technology has multiple plastic encapsulation processes, which cause thermal expansion coefficient mismatches between plastic encapsulation layers and easily lead to plastic layer delamination. At the same time, it is often difficult to stack and dissipate heat on the bottom chip. In addition, the multiple rewiring processes easily subject the chip to multiple high temperatures, causing wear on the bottom bump solder joints of the chip, thereby affecting the chip's reliability and many other issues. In addition, the complex process also leads to high costs, which is not conducive to mass production.
[0004] Therefore, how to provide a three-dimensional fan-out packaging structure to solve the high cost problem caused by the complicated processes in the existing three-dimensional fan-out packaging structure and the low chip reliability problem caused by multiple plastic packaging and rewiring has become an important technical problem that needs to be urgently solved by technical personnel in this field.
[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of this application and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Utility Model Content
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional fan-out packaging structure to solve the problems of complicated processes and low reliability of the three-dimensional fan-out packaging structure in the prior art.
[0007] To achieve the above and other related objectives, the present invention provides a three-dimensional fan-out packaging structure, comprising the following:
[0008] a first rewiring layer, the first rewiring layer comprising a first surface and a second surface oppositely disposed;
[0009] a first chip, the first chip being located on the second surface of the first redistribution layer and electrically connected to the first redistribution layer;
[0010] a first metal pillar, the first metal pillar being located on the second surface of the first redistribution layer, the first metal pillar being electrically connected to the first redistribution layer, and the first metal pillar and the first chip being located in the same plane;
[0011] a support structure, the support structure being located above the first metal pillar and electrically connected to the first metal pillar, the support structure comprising a second metal pillar and a support substrate, the support substrate having a first surface connected to the second metal pillar and an opposite second surface, and a gap being provided between the first surface of the support substrate and the first chip;
[0012] a second chip, the second chip being flip-chip bonded to the second surface of the support substrate and electrically connected to the support substrate;
[0013] a passive component mounted on the second surface of the support substrate and electrically connected to the support substrate;
[0014] a plastic encapsulation layer, the plastic encapsulation layer being located on the second surface of the first rewiring layer and covering the first chip, the second chip, the passive component, the first metal pillar, the supporting structure, and the gap;
[0015] A metal bump is located on the first surface of the first redistribution layer and is electrically connected to the first redistribution layer.
[0016] Optionally, the projection morphology of the support substrate is distributed in a matrix, and the projection size of the support substrate is smaller than the projection size of the first rewiring layer.
[0017] Optionally, the projection of the support substrate is smaller than the projection size of the first rewiring layer by 5 to 20 μm.
[0018] Optionally, a vertical distance between the support substrate and the first rewiring layer ranges from 150 to 480 μm.
[0019] Optionally, a vertical distance between the gap between the support substrate and the first chip ranges from 50 to 200 μm.
[0020] Optionally, the plastic sealing layer includes one or a combination of a polyimide layer, a silicone layer and an epoxy resin layer.
[0021] Optionally, the support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.
[0022] Optionally, the three-dimensional fan-out packaging structure further includes a bottom filling layer, and the bottom filling layer is located between the first chip and the first rewiring layer.
[0023] Optionally, the metal bump includes one of a copper metal bump, an aluminum metal bump, a nickel metal bump, a gold metal bump, a silver metal bump, and a titanium metal bump.
[0024] Optionally, the first redistribution layer includes a first dielectric layer and a first metal layer, wherein the first dielectric layer includes one of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer or a fluorine-containing glass layer, and the first metal layer includes one of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer or a titanium layer.
[0025] As described above, the present invention provides a three-dimensional fan-out packaging structure. By setting a first metal column and a second metal column structure whose height is adjustable, the distance between the support substrate and the first chip is controlled so that during the plastic sealing process, the plastic sealing material can flow into the gap and eventually fill the first chip, the second chip, the first metal column, the passive component, the support structure and the gap to form a plastic sealing layer structure. This not only simplifies the process, but also avoids the problem of stratification due to mismatched thermal expansion coefficients of different plastic sealing layers. In addition, since the distance between the support substrate and the first rewiring layer is adjustable, the heat dissipation effect of the chip can be improved while allowing the number of first chips to be increased. Furthermore, by adopting a single wiring substrate structure instead of the traditional second rewiring layer, the process steps are simplified, the problem of damage to the bump solder joints caused by high-temperature baking is avoided, the process manufacturing cost is reduced, and the stable performance of the chip is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 Shown is a schematic diagram of the process flow for preparing a three-dimensional fan-out packaging structure in a comparative example.
[0027] Figure 2 It is a schematic structural diagram after providing a first supporting substrate and forming a separation layer in a comparative example.
[0028] Figure 3It is a schematic structural diagram showing a comparative example in which a first redistribution layer is formed on the separation layer.
[0029] Figure 4 It is a schematic diagram of the structure after the metal connecting column is formed in the comparative example.
[0030] Figure 5 It is a schematic structural diagram after the first chip is formed in the comparative example.
[0031] Figure 6 It is a schematic diagram of the structure after the bottom filling layer is formed in the comparative example.
[0032] Figure 7 It is a schematic diagram of the structure after the first plastic sealing layer is formed in the comparative example.
[0033] Figure 8 It is a schematic diagram of the structure after the second rewiring layer is formed in the comparative example.
[0034] Figure 9 It is a schematic structural diagram after forming the second chip and passive components in the comparative example.
[0035] Figure 10 It is a schematic diagram of the structure after the second plastic sealing layer is formed in the comparative example.
[0036] Figure 11 It is a schematic diagram of the structure after removing the first supporting substrate and the separation layer in the comparative example.
[0037] Figure 12 It is a schematic diagram of the structure after the metal bumps are formed in the comparative example.
[0038] Figure 13 Shown is a schematic diagram of the process flow for preparing the three-dimensional fan-out packaging structure in the present invention.
[0039] Figure 14 It shows a schematic structural diagram after providing a first supporting substrate and forming a separation layer in the present invention.
[0040] Figure 15 It shows a schematic structural diagram after the first rewiring layer is formed in the present invention.
[0041] Figure 16 It is a schematic diagram of the structure after the first metal pillar is formed in the present invention.
[0042] Figure 17 It shows a schematic structural diagram after the first chip is formed in the present invention.
[0043] Figure 18 It shows a schematic diagram of the structure after the bottom filling layer is formed in the present invention.
[0044] Figure 19 It shows a schematic diagram of the structure after the support structure is formed in the present invention.
[0045] Figure 20 It shows a projection diagram of the supporting substrate and the first supporting substrate in the vertical direction of the present invention.
[0046] Figure 21 It is a schematic diagram of the structure after the second chip and passive components are formed in the present invention.
[0047] Figure 22 It shows a schematic diagram of the structure after the plastic sealing layer is formed in the present invention.
[0048] Figure 23 It shows a schematic diagram of the structure after the first supporting substrate and the separation layer are removed to form the metal bumps.
[0049] Description of Reference Numerals
[0050] 100 first supporting substrate
[0051] 110 separation layer
[0052] 200 First rewiring layer
[0053] 201 First Metal Layer
[0054] 202 first dielectric layer
[0055] 300 Metal connecting column
[0056] 301 First Metal Pillar
[0057] 310 First Chip
[0058] 320 bottom fill layer
[0059] 330 First plastic layer
[0060] 400 support structure
[0061] 401 Second Metal Pillar
[0062] 402 Support substrate
[0063] 410 Second Chip
[0064] 420 Passive Components
[0065] 430 Second Rewiring Layer
[0066] 431 Second Metal Layer
[0067] 432 Second dielectric layer
[0068] 450 Second plastic layer
[0069] 500 plastic encapsulation layer
[0070] 600 metal bump DETAILED DESCRIPTION
[0071] The above objectives, features and advantages of the present application will become apparent from specific description of the embodiments of the present application below. Other advantages of the present application can easily be understood by those skilled in the art from the disclosure of the present application. The present application can be embodied in various ways, and thus should not be construed as being limited to the embodiments set forth herein. It will also be understood that each of the features described herein can be substituted with any other suitable feature, or two or more features can be combined into a single feature, without departing from the scope of the present application.
[0072] In the following detailed description of the embodiments of the present application, the sectional views of the device structure are partially enlarged without the general scale for the convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.
[0073] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relationship words are intended to include other orientations of the device in use or operation in addition to the orientations depicted in the drawings, which can include embodiments in which the first and second features are formed in direct contact, and embodiments in which additional features are formed between the first and second features, so that the first and second features can not be in direct contact, and in addition, when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
[0074] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus the diagrams only show the components related to the present application, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can also be more complex.
[0075] Comparative Example
[0076] Figures 1 to 12 The structure schematic diagrams presented by each step in the preparation of the prior art three-dimensional fan-out package structure are illustrated. The preparation of the three-dimensional fan-out package structure is introduced below in conjunction with the drawings of the present specification.
[0077] First, refer to Figure 1 and Figure 2, performing step S1 - 1 , providing a first support substrate 100 , and forming a separation layer 110 on the first support substrate 100 .
[0078] Specifically, the first support substrate 100 comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the first support substrate 100 is a glass substrate, which is relatively low in cost, easily forms the separation layer 110 on its surface, and reduces the difficulty of the subsequent peeling process. The size of the first support substrate 100 is not limited herein, but is preferably wafer-scale.
[0079] Specifically, the separation layer 110 includes a polymer layer or an adhesive layer and a light-to-heat conversion layer (LTHC). The polymer layer or adhesive layer is formed on the first supporting substrate 100 by a spin coating process and then cured and formed by a UV curing or thermal curing process. The light-to-heat conversion layer (LTHC) has stable performance and a relatively smooth surface, which is conducive to the subsequent production of a rewiring layer, and in the subsequent peeling process, the peeling is less difficult.
[0080] Next, refer to Figure 1 and Figure 3 , performing step S1 - 2 to form a first redistribution layer 200 on the separation layer 110 , wherein the first redistribution layer 200 is divided into a first surface connected to the separation layer 110 and a second surface.
[0081] Specifically, the first rewiring layer 200 includes a first metal layer 201 and a first dielectric layer 202. The first rewiring layer 200 is formed based on the Damascus process; wherein, the first dielectric layer 202 can be made of one or a combination of silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO and BCB, and the first metal layer 201 can include one or a combination of copper layer, aluminum layer, nickel layer, gold layer, silver layer and titanium layer. There is no limitation on the material, number of wiring layers and wiring distribution of the first rewiring layer 200, and they can be selected according to needs. In this embodiment, the material of the first dielectric layer 202 is selected as PI (polyimide) to further reduce the process difficulty and process cost.
[0082] Next, refer to Figure 1 and Figure 4 , performing step S1 - 3 , forming a metal connecting column 300 on the second surface of the first redistribution layer 200 , wherein the metal connecting column 300 is electrically connected to the first redistribution layer 200 .
[0083] Specifically, the metal connecting column 300 is one of Au, Ag, Cu, and Al. In this embodiment, the metal connecting column 300 is a copper column, which is formed by electroplating on the second surface of the first redistribution layer 200 to improve its stability and reduce impedance. Of course, in some other embodiments, the metal connecting column 300 can also be prepared by other methods.
[0084] Next, refer to Figure 1 and Figure 5 , perform step S1 - 4 , provide a first chip 310 , flip-chip bonded to the second surface of the first redistribution layer 200 , and electrically connected to the first redistribution layer 200 .
[0085] Specifically, the first chip 310 includes one of a logic chip, a memory chip, a sensor chip, a power chip, and a communication chip. In this embodiment, the first chip 310 is a logic chip.
[0086] Next, refer to Figure 1 and Figure 6 , executing step S1 - 5 , forming an underfill layer 320 between the first chip 310 and the first rewiring layer 200 .
[0087] Specifically, the bottom filling layer 320 can, on the one hand, provide protection for the connection between the first chip 310 and the first rewiring layer 200 to prevent corrosion or connection damage, and on the other hand, can improve the bonding performance between the first chip 310 and the first rewiring layer 200 and improve the mechanical strength.
[0088] Next, refer to Figure 1 and Figure 7 , execute step S1-6 to form a first plastic encapsulation layer 330 on the second surface of the first rewiring layer 200, the first plastic encapsulation layer 330 encapsulates the first chip 310 and the metal connecting column 300, and then thins the first plastic encapsulation layer 330 to expose the surface of the metal connecting column 300.
[0089] Specifically, the first plastic encapsulation layer 330 can be formed by transfer molding or compression molding. Compression molding does not require transferring molding materials such as epoxy resin to a distant location. Instead, the chip is placed vertically downward on the molding material, thereby reducing defects such as voids and elongation. Therefore, compression molding is preferred for the plastic encapsulation layer in this embodiment. The first plastic encapsulation layer 330 covers the first chip 310 and the metal connecting pillars 300 to provide insulation protection.
[0090] Furthermore, the first plastic encapsulation layer 330 may include one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer. In this embodiment, the first plastic encapsulation layer 330 is a polyimide layer.
[0091] Next, refer to Figure 1 and Figure 8 , perform step S1-7 to form a second redistribution layer 430 on the surface of the first plastic layer 330, wherein the second redistribution layer 430 has a first surface and a second surface electrically connected to the metal connection column 300.
[0092] Specifically, the second rewiring layer 430 includes a second metal layer 431 and a second dielectric layer 432. The second rewiring layer 430 is formed based on the Damascus process; wherein, the second dielectric layer 432 can be made of one or a combination of silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO and BCB, and the second metal layer 431 can include one or a combination of copper layer, aluminum layer, nickel layer, gold layer, silver layer, titanium layer. The material, number of wiring layers and wiring distribution of the second rewiring layer 430 are not limited here and can be selected as needed. In this embodiment, the material of the second dielectric layer 432 is selected as PI (polyimide) to further reduce the process difficulty and process cost.
[0093] Next, refer to Figure 1 and Figure 9 , execute step S1-8, connect the passive component 420 and the second chip 410 on the second surface of the second redistribution layer 430, so that the second chip 410 and the passive component 420 are electrically connected to the second redistribution layer 430.
[0094] Specifically, in some embodiments, a second bottom filling layer (not shown) is formed between the second chip 410 and the second rewiring layer 430; on the one hand, the second bottom filling layer can provide protection for the connection between the second chip 410 and the second rewiring layer 430 to prevent corrosion or connection damage; on the other hand, it can improve the bonding performance between the second chip 410 and the second rewiring layer 430 and improve the mechanical strength.
[0095] Next, refer to Figure 1 and Figure 10 , executing step S1-9, forming a second plastic encapsulation layer 450 on the surface of the second redistribution layer 430, wherein the second plastic encapsulation layer 450 covers the second chip 410 and the passive component 420.
[0096] Specifically, the second plastic sealing layer 450 may include one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer. In this embodiment, the second plastic sealing layer 450 is a polyimide layer.
[0097] Next, referring to Figure 1 and Figure 11 , step S1-10 is performed to remove the first support substrate 100 and the separation layer 110 to expose the first surface of the first re-wiring layer 200.
[0098] Specifically, based on the separation layer 110, the first support substrate 100 can be released by, for example, light / radiation, and after the first support substrate 100 is removed, the first surface of the first re-wiring layer 200 is exposed, facilitating subsequent electrical connection. However, the method for removing the first support substrate 100 and the first re-wiring layer 200 is not limited thereto.
[0099] Next, referring to Figure 1 and Figure 12 , step S1-11 is performed to form a metal bump 600 on the first surface of the first re-wiring layer 200 and electrically connect it to the first re-wiring layer 200.
[0100] Specifically, the metal bump 600 can include, for example, a solder ball bump, a C4 metal bump, a columnar bump, etc. The material of the metal bump 600 is one or a combination of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium. The specific type of the metal bump 600 is not limited herein.
[0101] As can be seen from the above, in the prior art, after the first chip 310 is formed, the first encapsulation layer 330 is encapsulated, then the second re-wiring layer 430 is formed on the surface of the first encapsulation layer 330, then the second chip 410 and the passive component 420 are formed on the surface of the second re-wiring layer 430, and finally the second encapsulation layer 450 is encapsulated. Due to the difference in the thermal expansion coefficient between the two encapsulation layers, the interface is prone to delamination, affecting the stability of the performance of the packaging structure. In addition, during the formation of the second re-wiring layer 430, the thermal curing process of the second dielectric layer 432 is prone to cause fatigue damage to the bump 320 between the first chip 310 and the first re-wiring layer 200, affecting the performance stability of the encapsulation structure.
[0102] Embodiment One
[0103] Referring to Figures 13 to 23 , the embodiment of the present application provides a preparation method of a three-dimensional fan-out type packaging structure. Compared with the preparation method in the comparative example, the embodiment has simple manufacturing steps, low cost, solves the problem of high cost caused by complex processes in the existing three-dimensional fan-out type packaging structure, and the problem of low chip reliability caused by multiple encapsulation and re-wiring. In the embodiment, Figures 13 to 23The structure schematic diagram presented in each step when preparing the three-dimensional fan-out package structure is shown. The preparation of the three-dimensional fan-out package structure is introduced below in combination with the description of the accompanying drawings.
[0104] Firstly, referring to Figure 13 and Figure 14 , step S2-1 is performed to provide a first support substrate 100 and form a separation layer 110 on the first support substrate 100.
[0105] Specifically, the first support substrate 100 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In the embodiment, the first support substrate 100 is selected as a glass substrate, which has a lower cost, is easy to form a separation layer 110 on the surface, and can reduce the difficulty of subsequent peeling process. The size of the first support substrate 100 is not limited here, and is preferably wafer level.
[0106] The separation layer 110 includes a polymer layer or an adhesive layer and a light-heat conversion layer (LTHC). The polymer layer or the adhesive layer is formed on the first support substrate 100 by a spin coating process, and then is cured by using an ultraviolet curing or a thermal curing process. The light-heat conversion layer (LTHC) has stable performance and a smooth surface, which is beneficial to the subsequent production of the rewiring layer, and has a lower peeling difficulty in the subsequent peeling process.
[0107] Next, referring to Figure 13 and Figure 15 , step S2-2 is performed to form a first rewiring layer 200 on the separation layer 110, and the first rewiring layer 200 includes a first surface connected with the separation layer 110 and a second surface.
[0108] Specifically, the first rewiring layer 200 includes a first metal layer 201 and a first dielectric layer 202. The first rewiring layer 200 is formed based on Damascene process; wherein the first dielectric layer 202 can adopt one or a combination of, such as silicon oxide, silicon nitride, fluorine-containing glass, PI, PBO and BCB, and the first metal layer 201 can include one or a combination of, such as a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer, a titanium layer. The material, the number of wiring layers and the distribution of wiring of the first rewiring layer 200 are not limited here, and can be selected as needed. In the embodiment, the material of the first dielectric layer 202 is selected as PI (polyimide) to further reduce the process difficulty and the process cost.
[0109] Next, referring to Figure 13 and Figure 16, performing step S2 - 3 , forming a first metal pillar 301 on the second surface of the first redistribution layer 200 , wherein the first metal pillar 301 is electrically connected to the first redistribution layer 200 .
[0110] Specifically, the first metal pillar 301 can usually be formed by electroplating on the second surface of the first rewiring layer 200. The first metal pillar 301 is arranged perpendicular to the first rewiring layer 200 to shorten the conduction path. The first metal pillar 301 is one of Au, Ag, Cu, and Al. In this embodiment, the first metal pillar 301 is a copper pillar. The copper pillar is formed by electroplating on the second surface of the first rewiring layer 200 to improve its stability and reduce impedance.
[0111] Next, see Figure 13 and Figure 17 , executing step S2 - 4 , providing a first chip 310 , flip-chip bonding it to the second surface of the first redistribution layer 200 , and electrically connecting it to the first redistribution layer 200 .
[0112] Specifically, the first chip 310 includes one of a logic chip, a memory chip, a sensor chip, a power chip, and a communication chip. In this embodiment, the first chip 310 is a logic chip.
[0113] In some embodiments, see Figure 18 A bottom filling layer 320 may also be formed between the first chip 310 and the first rewiring layer 200 .
[0114] Specifically, in this embodiment, the underfill layer 320 is filled between the first chip 310 and the first re-distribution layer 200. For example, the underfill layer 320 can be formed using a dispensing process. The underfill layer 320 can protect the connection between the first chip 310 and the first re-distribution layer 200 from corrosion or damage, and can also improve the bonding between the first chip 310 and the first re-distribution layer 200, thereby increasing the mechanical strength.
[0115] Next, see Figure 13 and Figure 19 , execute step S2-5 to provide a support structure 400, wherein the support structure 400 includes a support substrate 402 and a second metal pillar 401, wherein the support substrate has a first surface connected to the second metal pillar and an opposite second surface, and the support structure 400 is connected to the first metal pillar 301 through the second metal pillar 401, and a gap (not marked) is provided between the first surface of the support substrate 402 and the first chip 310.
[0116] Specifically, the support substrate 402 is divided into a first surface connected with the second metal column 401 and a second surface, and the second metal column 401 is grown on the first surface of the support substrate 402. The second metal column 401 in the embodiment is a copper column. A seed layer is deposited on the support substrate 402 by sputtering or CVD, and then the seed layer is patterned by coating photoresist to form a pattern of the copper column. Then, a copper column with a required height is formed by electroplating, a uniform nickel barrier layer is formed on the surface of the metal copper column by electroplating, and then electroplated solder is formed to connect the first metal column 301.
[0117] Further, the second metal column 401 is divided into a first end and a second end arranged opposite to each other, the first end of the second metal column 401 is connected with the support substrate 402, and the other end is soldered to the top of the first metal column 301. By adjusting the height of the first metal column 301 and the height of the second metal column 401, the vertical distance between the first surface of the support substrate 402 and the first redistribution layer 200 is in the range of 150-480 μm, for example, 150 μm, 200 μm, 240 μm, 300 μm, 350 μm, 400 μm, 450 μm, 480 μm, or any value within the range. By adjusting the height of the first metal column 301 and the height of the second metal column 401 respectively, the distance between the support substrate 402 and the first redistribution layer 200 is more adjustable. Meanwhile, a higher gap allows the position of the first chip 310 to be stacked in multiple layers, and is also conducive to the dissipation of heat from the first chip 310, avoiding the problem of performance degradation of the chip caused by the failure of heat dissipation.
[0118] Further, the vertical distance between the first surface of the support substrate 402 and the first chip 310 is in the range of 50-200 μm, for example, 50 μm, 100 μm, 150 μm, 200 μm, or any value within the range. The vertical distance between the first surface of the support substrate 402 and the first chip 310 allows the plastic encapsulation material to fill the gap between the first chip 310, the first metal column 301, the support structure 400, the support substrate 402, and the first redistribution layer during the subsequent plastic encapsulation process, thereby reducing bubbles and defects during the plastic encapsulation process and facilitating the stability of the plastic encapsulation layer structure.
[0119] Further, referring to Figure 20The support substrate 402 adopts a single-wiring substrate, and the projection topography is in a matrix distribution. Meanwhile, the projection size of the support substrate 402 is smaller than the projection size of the first re-wiring layer 200, and the size difference ranges from 5 to 20 μm, for example, 5 μm, 8 μm, 10 μm, 15 μm, 17 μm, 20 μm, or any value within this range. The size difference is conducive to the subsequent plastic sealing process, in which the plastic sealing layer can flow into the space of the first chip 310, the first metal column 301, and the second metal column 401, reducing bubbles and defects in the plastic sealing process, and maintaining the stability of the plastic sealing layer structure. The support substrate 402 not only saves the process step of re-wiring on the glass substrate, but also avoids the fatigue damage of the bump welding point of the underfill layer 320 between the first chip 310 and the first re-wiring layer 200 caused by high-temperature baking in the secondary re-wiring process, which is conducive to the performance stability of the first chip 310.
[0120] Further, the support substrate 402 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the support substrate 402 adopts a glass substrate.
[0121] Next, referring to Figure 13 and Figure 21 , step S2-6 is performed to provide a second chip 410 and a passive component 420. The second chip 410 is flip-chip bonded to the second surface of the support substrate 402 and is electrically connected to the first metal column 301 through the second metal column 401. The passive component 420 is attached to the second surface of the support substrate 402 and is electrically connected to the first metal column 301 through the second metal column 401.
[0122] Specifically, the second chip 410 includes one of a logic chip, a storage chip, a sensor chip, a power chip, and a communication chip. In this embodiment, the second chip 410 is a storage chip.
[0123] Next, referring to Figure 13 and Figure 22 , step S2-7 is performed to form a plastic sealing layer 500 on the second surface of the first re-wiring layer 200. The plastic sealing layer 500 fills the gap formed by the first chip 310, the second chip 410, the passive component 420, the first metal column 301, and the support structure 400, and seals the first chip 310, the second chip 410, the passive component 420, the first metal column 301, and the support structure 400.
[0124] Specifically, the plastic sealing layer 500 can include one or a combination of a polyimide layer, a silica gel layer, and an epoxy resin layer. In this embodiment, the plastic sealing layer 500 is a polyimide layer. In this embodiment, because there is a gap between the support substrate 402 and the first chip 310, the plastic sealing material can flow into the first chip 310, the second chip 410, the passive component 420, the first metal column 301, the support structure 400, and the gap during plastic sealing, so that the first chip 310, the second chip 410, the passive component 420, the first metal column 301, and the support structure are plastic sealed by one plastic sealing process. This method avoids the complex process of two plastic sealing processes in the prior art, and also avoids the problem of delamination at the interface layer due to the difference in the coefficient of thermal expansion between the multiple plastic sealing layers, thereby ensuring the stability of the packaging structure and reducing the manufacturing cost, which is conducive to mass production.
[0125] Next, referring to Figure 13 and Figure 23 , step S2-8 is performed to remove the first support substrate 100 and the separation layer 110, form a metal bump 600 on the first face of the first re-wiring layer 200, and electrically connect the metal bump 600 to the first re-wiring layer 200.
[0126] Specifically, based on the separation layer 110, the first support substrate 100 can be released by, for example, light / radiation, so that the first face of the first re-wiring layer 200 is exposed after the first support substrate 100 is removed, facilitating subsequent electrical connection. However, the method for removing the first support substrate 100 is not limited thereto.
[0127] Further, the metal bump 600 can include, for example, a solder ball bump, a C4 metal bump, a columnar bump, etc. The material of the metal bump 600 is one or a combination of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium. The specific type of the metal bump 600 is not limited herein.
[0128] Embodiment Two
[0129] This embodiment proposes a three-dimensional fan-out type packaging structure, which is obtained by the manufacturing method described in Embodiment One or other suitable similar methods. The manufacturing method, material, and structure of the three-dimensional fan-out type packaging structure can be referred to Embodiment One, and referring to Figure 23 , which shows a cross-sectional structure diagram of the three-dimensional fan-out type packaging structure. The three-dimensional fan-out type packaging structure includes:
[0130] a first re-wiring layer 200, which includes oppositely arranged first and second faces.
[0131] The first chip 310 is located on the second surface of the first redistribution layer 200 and is electrically connected to the first redistribution layer 200 .
[0132] The first metal pillar 301 is located on the second surface of the first redistribution layer 200 , and the first metal pillar 301 is electrically connected to the first redistribution layer 200 . The first metal pillar 301 and the first chip 310 are located in the same plane.
[0133] A support structure 400 is provided, wherein the support structure 400 is located above the first metal pillar 301 and is electrically connected to the first metal pillar 301. The support structure 400 includes a second metal pillar 401 and a support substrate 402. The support substrate 402 has a first surface connected to the second metal pillar 401 and an opposite second surface. A gap is provided between the first surface of the support substrate 402 and the first chip 310.
[0134] The second chip 410 is flip-chip bonded on the second surface of the support substrate 402 and is electrically connected to the support substrate 402 .
[0135] The passive component 420 is mounted on the second surface of the support substrate 402 and is electrically connected to the support substrate 402 .
[0136] The plastic encapsulation layer 500 is located on the second surface of the first redistribution layer 200 and covers the first chip 310 , the second chip 410 , the passive component 420 , the first metal pillar 301 , the support structure 400 and the gap.
[0137] The metal bump 600 is located on the first surface of the first redistribution layer 200 and is electrically connected to the first redistribution layer 200 .
[0138] For example, see Figure 20 The projection morphology of the supporting substrate 402 is distributed in a matrix, and the size of the supporting substrate 402 is smaller than the projection size of the first rewiring layer 200, and the size difference ranges from 5 to 20 μm, such as 5 μm, 10 μm, 15 μm, 18 μm, 20 μm, and any value within this range.
[0139] Specifically, the support substrate 402 has a size smaller than the projected size of the first re-wiring layer 200, which is advantageous for the plastic encapsulation layer 500 to flow into the space between the first chip 310, the first metal pillar 301 and the support structure 400 in the subsequent plastic encapsulation process, so as to reduce the air bubbles and defects in the plastic encapsulation process and maintain the stability of the plastic encapsulation layer 500.
[0140] Further, the support substrate 402 comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.
[0141] As an example, the three-dimensional fan-out package structure further comprises a under-fill layer 320 between the first chip 310 and the first re-wiring layer 200. The under-fill layer 320 can provide protection for the connection between the first chip 310 and the first re-wiring layer 200, prevent corrosion or connection damage, and improve the adhesion between the first chip 310 and the first re-wiring layer 200 and the mechanical strength.
[0142] Further, the support substrate 402 not only saves the process step of re-wiring on the glass substrate, but also avoids fatigue damage of the bump solder joint of the under-fill layer 320 between the first chip 310 and the first re-wiring layer 200 caused by high-temperature baking in the secondary re-wiring, which is advantageous for the performance stability of the first chip 310.
[0143] As an example, the plastic encapsulation layer 500 can comprise one or a combination of a polyimide layer, a silica gel layer and an epoxy resin layer. In the embodiment, the plastic encapsulation layer 500 is a polyimide layer.
[0144] In the embodiment, since there is a gap with a certain distance between the support substrate 402 and the first chip 310, when plastic encapsulation is performed, the material of the plastic encapsulation layer 500 can flow into the gap between the first chip 310, the second chip 410, the passive component 420, the first metal pillar 301 and the support structure 400, so as to ensure that the first chip 310, the second chip 410, the passive component 420, the first metal pillar 301 and the support structure 400 are encapsulated by one-time plastic encapsulation process. This way avoids the complex process of two-time plastic encapsulation in the prior art, and also avoids the problem of delamination at the interface layer caused by the difference in the coefficient of thermal expansion between the multiple plastic encapsulation layers, ensures the stability of the package structure, and reduces the manufacturing cost, which is advantageous for mass production.
[0145] As an example, the vertical distance between the support substrate 402 and the first redistribution layer 200 ranges from 150 to 480 μm, for example, 150 μm, 240 μm, 300 μm, 350 μm, 400 μm, 450 μm, 480 μm, or any other value within this range. Specifically, by adjusting the height of the first metal pillar 301 and the height of the second metal pillar 401, the distance between the support substrate 402 and the first redistribution layer 200 is more adjustable. Furthermore, the higher gap allows for multiple stacking of the first chip 310, facilitating heat dissipation from the first chip 310 and preventing chip performance degradation due to delayed heat dissipation.
[0146] As an example, the first rewiring layer 200 includes a first dielectric layer 202 and a first metal layer 201, wherein the material of the first dielectric layer 202 includes one of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer or a fluorine-containing glass layer, and the first metal layer includes one of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer or a titanium layer.
[0147] As an example, the material of the metal bump 600 is one of a copper metal bump, an aluminum metal bump, a nickel metal bump, a gold metal bump, a silver metal bump, and a titanium metal bump.
[0148] The three-dimensional fan-out packaging structure of this embodiment includes the first rewiring layer 200, the first chip 310, the first metal pillar 301, the support structure 400, the second chip 410, the passive component 420, the plastic layer 500, and the metal bumps 600. By arranging the first metal pillar 301 and the second metal pillar 401 structure and adjusting their heights, the distance between the first chip 310 and the support substrate 402 is controlled. This allows the material of the plastic layer 500 to flow into the gap during the plastic encapsulation process, ultimately filling the first chip 310, the second chip 410, the first metal pillar 301, the support structure 400, and the passive component 420 to form the plastic layer 500. This not only simplifies the process steps but also avoids the problem of delamination caused by mismatched thermal expansion coefficients of the multi-layer plastic encapsulation structure. In addition, by adopting a single wiring substrate structure instead of the traditional second rewiring layer, the risk of fatigue damage to the bump solder joints of the bottom filling layer 320 between the first chip 310 and the first rewiring layer 200 caused by high-temperature baking is avoided, thereby ensuring the stability of the chip function.
[0149] In summary, the present invention provides a three-dimensional fan-out packaging structure. By setting a first metal column and a second metal column structure and making them height-adjustable, the distance between the support substrate and the first chip is controlled so that during the plastic sealing process, the plastic sealing material can flow into the gap and eventually fill the first chip, the second chip, the first metal column, the support structure and the passive components to form a single plastic sealing layer structure. This not only simplifies the process, but also avoids the problem of stratification due to mismatched thermal expansion coefficients of different plastic sealing layers. In addition, since the distance between the support substrate and the first rewiring layer is adjustable, the heat dissipation effect of the chip can be improved, and at the same time, the number of first chips can be increased. Furthermore, by adopting a single wiring substrate structure instead of the traditional second rewiring layer, the process steps are simplified, the problem of damage to the bump solder joints caused by high-temperature baking is avoided, the process manufacturing cost is reduced, and the stable performance of the chip is guaranteed. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0150] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed in the present invention are intended to be covered by the claims of the present invention.
Claims
1. A three-dimensional fan-out packaging structure, characterized in that: The three-dimensional fan-out packaging structure includes: a first rewiring layer, the first rewiring layer comprising a first surface and a second surface oppositely disposed; a first chip, the first chip being located on the second surface of the first redistribution layer and electrically connected to the first redistribution layer; a first metal pillar, the first metal pillar being located on the second surface of the first redistribution layer, the first metal pillar being electrically connected to the first redistribution layer, and the first metal pillar and the first chip being located in the same plane; a support structure, the support structure being located above the first metal pillar and electrically connected to the first metal pillar, the support structure comprising a second metal pillar and a support substrate, the support substrate having a first surface connected to the second metal pillar and an opposite second surface, and a gap being provided between the first surface of the support substrate and the first chip; a second chip, the second chip being flip-chip bonded to the second surface of the support substrate and electrically connected to the support substrate; a passive component mounted on the second surface of the support substrate and electrically connected to the support substrate; a plastic encapsulation layer, the plastic encapsulation layer being located on the second surface of the first rewiring layer and covering the first chip, the second chip, the passive component, the first metal pillar, the support structure, and the gap; A metal bump is located on the first surface of the first redistribution layer and is electrically connected to the first redistribution layer.
2. The three-dimensional fan-out packaging structure according to claim 1, wherein: The projection morphology of the support substrate is distributed in a matrix, and the projection size of the support substrate is smaller than the projection size of the first rewiring layer.
3. The three-dimensional fan-out packaging structure according to claim 2, wherein: The projection of the support substrate is smaller than the projection size of the first rewiring layer by 5-20 μm.
4. The three-dimensional fan-out packaging structure according to claim 1, wherein: The vertical distance between the support substrate and the first rewiring layer ranges from 150 μm to 480 μm.
5. The three-dimensional fan-out packaging structure according to claim 1, wherein: A vertical distance between the support substrate and the first chip ranges from 50 μm to 200 μm.
6. The three-dimensional fan-out packaging structure according to claim 1, wherein: The plastic sealing layer includes one or a combination of a polyimide layer, a silicone layer and an epoxy resin layer.
7. The three-dimensional fan-out packaging structure according to claim 1, wherein: The support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.
8. The three-dimensional fan-out packaging structure according to claim 1, wherein: The three-dimensional fan-out packaging structure further includes a bottom filling layer, and the bottom filling layer is located between the first chip and the first rewiring layer.
9. The three-dimensional fan-out packaging structure according to claim 1, wherein: The metal bumps include one of copper metal bumps, aluminum metal bumps, nickel metal bumps, gold metal bumps, silver metal bumps, and titanium metal bumps.
10. The three-dimensional fan-out packaging structure according to claim 1, wherein: The first rewiring layer includes a first dielectric layer and a first metal layer, wherein the first dielectric layer includes one of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer or a fluorine-containing glass layer, and the first metal layer includes one of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer or a titanium layer.