Package structure

Abstract

The utility model provides a packaging structure which comprises a heterogeneous substrate which comprises a core made of glass and a first circuit layer arranged above the core, and the first circuit layer is provided with a flat part arranged on the upper surface of the first circuit layer; and the bridging wafer is arranged above the flat part, and the lower surface of the bridging wafer is parallel to the flat part. The glass has high heat resistance and anti-warping capability, so that excellent heat stability and anti-warping capability can be provided for the heterogeneous substrate by using the glass as the core, the flatness of the upper surface of the heterogeneous substrate can be kept, and the first circuit layer arranged above the core can also be kept flat; the lower surface of the bridging wafer can be kept parallel to the flat part, so that good contact between the bridging wafer and the heterogeneous substrate is ensured, and the quality of the whole packaging structure is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor packaging technical field, concretely relates to a packaging structure. BACKGROUND

[0002] It is a time-honored technique to use a bridge wafer to realize electrical connection between two wafers, however, when the bridge wafer is applied, if the bottom of the substrate is not flat or warping occurs, it will cause the bridge wafer to be difficult to package, thereby causing electrical problems. SUMMARY

[0003] The utility model provides a packaging structure.

[0004] In the first aspect, the utility model provides a packaging structure, include: hetero substrate, including with glass as material core and set up on the first circuit layer of core top, first circuit layer has set up on the flat portion of first circuit layer upper surface, bridge wafer is set up on the flat portion top and bridge wafer lower surface with flat portion parallel.

[0005] In some optional implementation, the packaging structure further includes:

[0006] The first mold sealing layer is arranged to cover the upper surface of the first circuit layer.

[0007] In some optional implementation, the first mold sealing layer includes a recess formed by the recessed upper surface, and the recess exposes the flat portion.

[0008] In some optional implementation, in the cross-sectional view, the horizontal width of the flat portion is greater than the horizontal width of the recess.

[0009] In some optional implementation, in the cross-sectional view, the horizontal width of the recess is greater than the horizontal width of the bridge wafer.

[0010] In some optional implementation, the packaging structure further includes:

[0011] The second mold sealing layer is filled in the recess.

[0012] In some optional implementation, the top surface of the first mold sealing layer, the second mold sealing layer and the bridge wafer is flush.

[0013] In some optional implementation, the packaging structure further includes:

[0014] The adhesive layer is arranged between the bridge wafer and the flat portion.

[0015] In some optional implementation, the packaging structure further includes:

[0016] A first metal pillar is disposed on the first circuit layer and electrically connected with the first circuit layer.

[0017] In some optional embodiments, the top surface of the first metal pillar is flush with the top surface of the bridge wafer.

[0018] In order to solve the problem that if the bottom of the substrate is not flat or has warping, the bridge wafer is not easy to package, and thus electrical problems are caused when the bridge wafer is applied, the utility model provides a packaging structure, glass is used as the core to provide excellent thermal stability and warping resistance for the heterogeneous substrate, keep the upper surface of the heterogeneous substrate flat, and the first circuit layer arranged above the core is also kept flat, when the bridge wafer is arranged above the flat part, the lower surface of the bridge wafer can be parallel to the flat part, which helps to ensure good contact between the bridge wafer and the heterogeneous substrate, and thus the quality of the overall packaging structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Other features, objects and advantages of the utility model will become more apparent through reading the detailed description of the non-restrictive embodiments made with reference to the following drawings:

[0020] Figure 1 is a structural schematic view of an existing packaging structure;

[0021] Figure 2 is a structural schematic view of an embodiment 2a of the packaging structure according to the utility model;

[0022] Figure 3 is Figure 2 is a local enlarged view of the rectangular dashed line area in

[0023] Figure 4 is a structural schematic view of an embodiment 3a of the packaging structure according to the utility model;

[0024] Figure 5-Figure 17 is a schematic view of the manufacturing steps of an embodiment 2a of the semiconductor packaging structure according to the utility model;

[0025] Figures 18-29 is a schematic view of the manufacturing steps of an embodiment 3a of the semiconductor packaging structure according to the utility model.

[0026] Explanation of the reference signs / symbols:

[0027] 101 - substrate; 102 - bridge wafer; 103 - first wafer; 104 - second wafer; 201 - heterogeneous substrate; 202 - bridge wafer; 203 - first mold sealing layer; 204 - second mold sealing layer; 205 - adhesive layer; 206 - first metal column; 207 - third mold sealing layer; 208 - solder resist layer; 209 - film; 210 - BT (Bismaleimide-Triazine); 2011 - core; 2012 - first circuit layer; 2013 - resin layer; 2014 - second circuit layer; 20121 - flat part; 2021 - lower surface of bridge wafer; 2022 - second metal column; 2031 - upper surface of first mold sealing layer; 2032 - recess. DETAILED DESCRIPTION

[0028] The specific embodiments of the present application will be described below in conjunction with the drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced by the present application through the contents described in the specification. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, in order to facilitate description, only the parts related to the application are shown in the drawings.

[0029] It should be readily understood that the meanings of "on", "above", and "on top of" in the present application should be interpreted in the broadest manner, such that "on" not only means "directly on" but also means "on with intervening components or layers therebetween".

[0030] In addition, in order to facilitate description, spatial relative terms such as "below", "under", "lower", "above", "upper" and the like can be used herein to describe the relationship of one element or component to another element or component shown in the drawings. In addition to the orientation described in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0031] As used herein, the term "layer" refers to a portion of a material comprising an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above and / or below. A layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0032] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer. Further alternatively, the substrate can have semiconductor devices or circuits formed therein.

[0033] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0034] It should also be noted that the longitudinal section corresponding to the embodiment of the present invention may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0035] In addition, the embodiments and features of the embodiments of the present invention can be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] refer to Figure 1, Figure 1 It is a structural diagram of an existing packaging structure.

[0037] like Figure 1 As shown, the existing packaging structure includes a substrate 101, a bridge chip 102, a first chip 103 and a second chip 104, wherein the bridge chip 102 is arranged in the substrate 101, and the first chip 103 and the second chip 104 are electrically connected through the bridge chip 102. However, when using the bridge chip 102, if the bottom of the substrate 101 is uneven or warped, it will make it difficult to package the bridge chip 102, thereby causing electrical problems.

[0038] refer to Figure 2 , Figure 2 It is a structural diagram of an embodiment 2a of the packaging structure according to the present utility model.

[0039] like Figure 2 As shown, the package structure 2a of the present invention includes a heterogeneous substrate 201 and a bridge chip 202, wherein:

[0040] The heterogeneous substrate 201 includes a core 2011 made of glass and a first circuit layer 2012 arranged above the core 2011. The first circuit layer 2012 has a flat portion 20121 arranged on the upper surface of the first circuit layer 2012; the bridge chip 202 is arranged above the flat portion 20121 and the lower surface 2021 of the bridge chip is parallel to the flat portion 20121.

[0041] Here, because glass has high thermal stability and warping resistance, using glass as the core 2011 can provide excellent thermal stability and warping resistance for the heterogeneous substrate 201, maintain the flatness of the upper surface of the heterogeneous substrate 201, and thus maintain the flatness of the first circuit layer 2012 disposed above the core 2011. Furthermore, the first circuit layer 2012 can have a flat portion 20121 disposed on the upper surface of the first circuit layer 2012. The flat portion 20121 can be a portion of the upper surface of the first circuit layer 2012.

[0042] In this way, when the bridge chip 202 is set above the flat portion 20121, the lower surface 2021 of the bridge chip can remain parallel to the flat portion 20121, which helps to ensure good contact between the bridge chip 202 and the heterogeneous substrate 201, thereby improving the yield of the overall packaging structure 2a.

[0043] In some optional embodiments, the package structure 2 a further includes a first molding layer 203 configured to cover the upper surface of the first circuit layer 2012 .

[0044] Here, the first molding layer 203 can protect the first circuit layer 2012 and prevent the external environment from causing damage to the first circuit layer 2012.

[0045] The materials of the first molding layer 203 may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0046] In some optional embodiments, reference Figure 2 and Figure 14 The first mold sealing layer 203 includes a concave portion 2032 formed by a depression of the upper surface, and the concave portion 2032 exposes the flat portion 20121.

[0047] Here, by setting a recess 2032 in the first molding layer 203, the bridge chip 202 is set on the flat portion 20121 and buried in the first molding layer 203, which can significantly reduce the total thickness of the packaging structure and reduce the number of layers of redistribution circuit layers originally required.

[0048] In some optional embodiments, reference Figure 2 In the cross-sectional view, the horizontal width of the flat portion 20121 is greater than the horizontal width of the recessed portion 2032 .

[0049] Here, the horizontal width of the flat portion 20121 is set to be larger than the horizontal width of the recessed portion 2032, so that part of the flat portion 20121 located on both sides of the recessed portion 2032 can be encapsulated in the first sealing layer 203, so that the first sealing layer 203 can support the flat portion 20121 and improve its installation stability.

[0050] In some optional embodiments, in the cross-sectional view, the horizontal width of the recess 2032 is greater than the horizontal width of the bridge wafer 202 .

[0051] Here, the horizontal width of recess 2032 is greater than the horizontal width of bridge wafer 202, which also means that the horizontal width of flat portion 20121 is greater than the horizontal width of the bridge wafer. This, on the one hand, facilitates accurate positioning and installation of bridge wafer 202, simplifying the alignment and fixing steps during the manufacturing process. It also allows for a certain degree of installation error in bridge wafer 202, thereby improving the yield rate of the package structure. On the other hand, the fact that the horizontal width of flat portion 20121 is greater than the horizontal width of the bridge wafer allows bridge wafer 202 to be fully positioned on flat portion 20121, thereby providing a larger contact area for bridge wafer 202, ensuring electrical connection between bridge wafer 202 and first circuit layer 12, and ensuring good electrical conductivity.

[0052] In some optional embodiments, the package structure 2 a further includes a second molding layer 204 filling the recess 2032 .

[0053] The materials of the second molding layer 204 may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0054] The materials of the first encapsulation layer 203 and the second encapsulation layer 204 can be the same or different.

[0055] Here, the second molding layer 204 fills the recess 2032, which can protect the bridge chip 202 and the flat portion 20121, and can also make the bridge chip 202 more firmly fixed on the flat portion 20121. At the same time, it can also enhance the overall mechanical strength of the packaging structure and reduce the risk of deformation of the packaging structure when subjected to external force.

[0056] In some optional embodiments, the top surfaces of the first encapsulation layer 203 , the second encapsulation layer 204 , and the bridge wafer 202 are flush, thereby achieving consistency and flatness of the surface of the package structure 2 a .

[0057] refer to Figure 2 and Figure 3 , Figure 3 yes Figure 2 A local enlarged view of the rectangular dotted area in .

[0058] In some optional embodiments, the package structure 2 a further includes an adhesive layer 205 disposed between the bridge chip 202 and the flat portion 20121 .

[0059] Here, the adhesive layer 205 can be a liquid or film-like organic material, such as: non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive paste (ACP), anisotropic conductive film (ACF), polyimide (PI), epoxy resin (Epoxy), resin (Resin), PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), glue, etc.

[0060] By providing an adhesive layer 205 between the bridge chip 202 and the flat portion 20121 , the adhesive strength between the bridge chip 202 and the flat portion 20121 can be further improved, ensuring that the bridge chip 202 is firmly fixed on the flat portion 20121 , thereby improving the mechanical stability of the packaging structure.

[0061] In some optional embodiments, the package structure 2 a further includes a first metal pillar 206 , which is disposed on the first circuit layer 2012 and electrically connected to the first circuit layer 2012 , further achieving electrical connection between the first metal pillar 206 and the bridge chip 202 .

[0062] In some optional embodiments, the top surface of the first metal pillar 206 is flush with the top surface of the bridge wafer 202 , so as to achieve consistency and flatness of the surface of the package structure 2 a .

[0063] Continue to refer Figure 2 In some optional embodiments, the core 2011 includes a plurality of glass modules and there are gaps between each glass module.

[0064] In some optional embodiments, the heterogeneous substrate 201 further includes a resin layer 2013 configured to cover the core 2011 and fill the spaces between the glass modules.

[0065] In this way, the resin layer 2013 fills the gaps between the glass modules, which can enhance the overall mechanical strength of the heterogeneous substrate 201, so that the glass modules form a solid whole, reducing deformation or damage caused by external forces. In addition, the resin layer 2013 covers the core 2011, which can keep the upper surface of the heterogeneous substrate 201 flat.

[0066] In some optional embodiments, the bridge wafer 202 has a second metal pillar 2022 .

[0067] Here, the second metal pillars 2022 can provide reliable electrical connection points to achieve electrical connection between the bridge wafer 202 and other components.

[0068] In some optional embodiments, the heterogeneous substrate further includes a second circuit layer 2014 , which is configured to cover the lower surface of the core 2011 .

[0069] Here, since glass has high thermal stability and anti-warping ability, using glass as the core 2011 can provide the heterogeneous substrate 201 with excellent thermal stability and anti-warping ability, can maintain the flatness of the upper surface of the heterogeneous substrate 201, and can also keep the second circuit layer 2014 arranged under the core 2011 flat.

[0070] In some optional embodiments, the packaging structure further includes a third molding layer 207 configured to cover the upper surface of the second circuit layer 2014 .

[0071] The materials of the third molding layer 207 may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0072] Here, the third molding layer 207 can protect the second circuit layer 2014 and prevent the external environment from causing damage to the second circuit layer 2014.

[0073] In some optional embodiments, the package structure 2 a further includes a solder mask layer 208 disposed on the third molding layer 207 .

[0074] Above, an embodiment 2a of the packaging structure of the present invention is introduced.

[0075] refer to Figure 4 , Figure 4 It is a structural diagram of an embodiment 3a of the packaging structure according to the present utility model.

[0076] Figure 4 The package structure 3a shown is similar to Figure 2The package structure 2a shown in FIG is different in that:

[0077] There is no adhesive layer 205 between the bridge chip 202 and the flat part 20121. Instead, the bridge chip 202 is directly placed in the first molding layer 203. Therefore, the first molding layer 203 will fill the gap between the flat part 20121 and the bridge chip 202, and the effect of embodiment 2a can also be achieved.

[0078] Above, an embodiment 3a of the packaging structure of the present invention is introduced.

[0079] refer to Figure 5-Figure 17 , Figure 5-Figure 17 It is a schematic diagram of the manufacturing steps of an embodiment 2a of the semiconductor packaging structure according to the present invention.

[0080] refer to Figure 5 , providing an adhesive film 209 and bismaleimide triazine 210.

[0081] Here, a cavity may be formed by the adhesive film 209 and the bismaleimide triazine 210 .

[0082] refer to Figure 6 , providing core 2011.

[0083] Here, the material of the core 2011 can be glass.

[0084] Here, the core 2011 includes a plurality of glass modules with spaces between the glass modules. The plurality of glass modules can be adhered to an adhesive film to form the core 2011 .

[0085] Since glass has high thermal stability and anti-warping capability, using glass as the core 2011 can provide the heterogeneous substrate 201 with excellent thermal stability and anti-warping capability.

[0086] refer to Figure 7 , filling and laminating resins.

[0087] Here, resin can be filled into the spaces between the glass modules and covered on the core 2011 by filling and laminating to form a partial resin layer 2013. This can enhance the overall mechanical strength of the heterogeneous substrate 201, allowing the glass modules to form a solid whole and reduce deformation or damage caused by external forces.

[0088] refer to Figure 8 , a portion of the resin layer 2013 is etched / grinded.

[0089] Here, part of the resin layer 2013 may be etched / grinded to remove excess resin and remove uneven portions of the surface of the resin layer 2013 to make the surface of the resin layer 2013 smoother.

[0090] refer to Figure 9 , remove the adhesive film 209 and perform resin lamination on the lower surface of the core 2011.

[0091] Here, the adhesive film 209 on the lower surface of the core 2011 may be removed by heating, and after the adhesive film 209 is removed, a resin may be laminated on the lower surface of the core 2011 to form the resin layer 2013 of the heterogeneous substrate 201 .

[0092] refer to Figure 10 , laminated PP and metal layers (polypropylene).

[0093] Here, polypropylene is laminated on the upper and lower surfaces of the resin layer 2013 , respectively. Polypropylene can be used as a dielectric material for the first wiring layer 2012 and the second wiring layer 2014 .

[0094] refer to Figure 11 , providing through holes and part of the first circuit layer 2012 and part of the second circuit layer 2014.

[0095] Here, through holes and a portion of the first circuit layer 2012 and a portion of the second circuit layer 2014 may be formed on the upper and lower surfaces of the resin layer 2013 by photolithography and electroplating processes.

[0096] refer to Figure 12 ,exist Figure 11 Based on the package structure, repeat the operation Figure 9 and Figure 10 The steps are repeated twice to form the final first circuit layer 2012 , the second circuit layer 2014 and the flat portion 20121 .

[0097] refer to Figure 13 , providing a first mold sealing layer 203 and a third mold sealing layer 207.

[0098] Here, a molding material may be laminated on the first wiring layer 2012 to form a first molding layer 203 , and a molding material may be laminated on the second wiring layer 2014 to form a third molding layer 207 .

[0099] The materials of the first molding layer 203 may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0100] Similarly, the material of the third molding layer 207 may also include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0101] refer to Figure 14 , providing a recess 2032 and a bridge chip 202.

[0102] Here, the first encapsulation layer 203 may be laser cut to form a recess 2032 to expose the flat portion 20121 . Then, an adhesive layer 205 may be disposed on the flat portion 20121 , and then the bridge chip 202 may be disposed above the flat portion 20121 .

[0103] Here, the adhesive layer 205 can be a liquid or film-like organic material, such as: non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive paste (ACP), anisotropic conductive film (ACF), polyimide (PI), epoxy resin (Epoxy), resin (Resin), PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), glue, etc.

[0104] By providing an adhesive layer 205 between the bridge chip 202 and the flat portion 20121 , the adhesive strength between the bridge chip 202 and the flat portion 20121 can be further improved, ensuring that the bridge chip 202 is firmly fixed on the flat portion 20121 , thereby improving the mechanical stability of the packaging structure.

[0105] Here, by setting a recess 2032 in the first molding layer 203, the bridge chip 202 can be set on the flat portion 20121 and buried in the first molding layer 203, which can significantly reduce the total thickness of the packaging structure and reduce the number of layers of redistribution circuit layers originally required.

[0106] refer to Figure 15 , providing a first metal pillar 206 and a second encapsulation layer 204 .

[0107] Here, the first molding layer 203 may be on the first circuit layer 2012 and electrically connected to the first circuit layer 2012 , and each metal pillar 206 may be surrounded by the first molding layer 203 .

[0108] The materials of the second molding layer 204 may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0109] The materials of the first encapsulation layer 203 and the second encapsulation layer 204 can be the same or different.

[0110] Here, the recess may be filled with molding material to form a second molding layer 204. The second molding layer 204 may protect the bridging chip 202 and the flat portion 20121, and may also more firmly fix the bridging chip 202 on the flat portion 20121. At the same time, it may also enhance the overall mechanical strength of the packaging structure and reduce the risk of deformation of the packaging structure when subjected to external forces.

[0111] refer to Figure 16 ,right Figure 15 The formed packaging structure is ground.

[0112] Here, the first encapsulation layer 203, the metal pillar 206 and the second encapsulation layer 204 can be ground so that the top surface of the first encapsulation layer 203, the second encapsulation layer 204 and the first metal pillar 206 are flush with the top surface of the bridge chip 202, thereby achieving consistency and flatness of the surface of the packaging structure 2a.

[0113] refer to Figure 17 , providing a solder mask layer 208.

[0114] Here, a solder resist layer 208 may be disposed on the third molding layer 207 to form a second packaging structure 2 a .

[0115] refer to Figures 18-29 , Figures 18-29 It is a schematic diagram of the manufacturing steps of an embodiment 3a of the semiconductor packaging structure according to the present invention.

[0116] refer to Figure 18 , providing an adhesive film 209 and bismaleimide triazine 210.

[0117] Here, a cavity may be formed by the adhesive film 209 and the bismaleimide triazine 210 .

[0118] refer to Figure 19 , providing core 2011.

[0119] Here, the material of the core 2011 can be glass.

[0120] Here, the core 2011 includes a plurality of glass modules with spaces between the glass modules. The plurality of glass modules can be adhered to an adhesive film to form the core 2011 .

[0121] Since glass has high thermal stability and anti-warping capability, using glass as the core 2011 can provide the heterogeneous substrate 201 with excellent thermal stability and anti-warping capability.

[0122] refer to Figure 20 , filling and laminating resins.

[0123] Here, resin can be filled into the spaces between the glass modules and covered on the core 2011 by filling and laminating to form a partial resin layer 2013. This can enhance the overall mechanical strength of the heterogeneous substrate 201, allowing the glass modules to form a solid whole and reduce deformation or damage caused by external forces.

[0124] refer to Figure 21 , a portion of the resin layer 2013 is etched / grinded.

[0125] Here, part of the resin layer 2013 may be etched / grinded to remove excess resin and remove uneven portions of the surface of the resin layer 2013 to make the surface of the resin layer 2013 smoother.

[0126] refer to Figure 22 , remove the adhesive film 209 and perform resin lamination on the lower surface of the core 2011.

[0127] Here, the adhesive film 209 on the lower surface of the core 2011 may be removed by heating, and after the adhesive film 209 is removed, a resin may be laminated on the lower surface of the core 2011 to form the resin layer 2013 of the heterogeneous substrate 201 .

[0128] refer to Figure 23 , laminated PP and metal layers (polypropylene).

[0129] Here, polypropylene is laminated on the upper and lower surfaces of the resin layer 2013 , respectively. Polypropylene can be used as a dielectric material for the first wiring layer 2012 and the second wiring layer 2014 .

[0130] refer to Figure 24 , providing through holes and part of the first circuit layer 2012 and part of the second circuit layer 2014.

[0131] Here, through holes and a portion of the first circuit layer 2012 and a portion of the second circuit layer 2014 may be formed on the upper and lower surfaces of the resin layer 2013 by photolithography and electroplating processes.

[0132] refer to Figure 25 ,exist Figure 24 Based on the package structure, repeat the operation Figure 23 and Figure 24 The steps are repeated twice to form the final first circuit layer 2012 , the second circuit layer 2014 and the flat portion 20121 .

[0133] refer to Figure 26 , providing a first mold sealing layer 203 and a third mold sealing layer 207.

[0134] Here, a molding material may be laminated on the first wiring layer 2012 to form a first molding layer 203 , and a molding material may be laminated on the second wiring layer 2014 to form a second molding layer 207 .

[0135] The materials of the first molding layer 203 may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0136] Similarly, the material of the third molding layer 207 may also include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0137] refer to Figure 27 , providing a bridge wafer 202 and a first metal pillar 206 .

[0138] Compared with Example 2a, after the first sealing layer 203 is formed, the bridge chip 202 can be directly pressed into the first sealing layer 203, and the effect of Example 2a can also be achieved. However, compared with the method of forming the recess 2032 by laser cutting to expose the flat portion 20121, and then setting the adhesive layer 205 on the flat portion 20121, and then setting the bridge chip 202 above the flat portion 20121, since the height to which the bridge chip 202 is pressed down is lower than the height of the recess 2032, the thickness of the entire packaging structure will be thicker than that of Example 2a.

[0139] Here, the first molded layer 203 may be on the first circuit layer 2012 and electrically connected to the first circuit layer 2012 , and each metal pillar 206 may be surrounded by the first molded layer 203 .

[0140] refer to Figure 28 ,right Figure 27 The formed packaging structure is ground.

[0141] Here, the first encapsulation layer 203, the metal pillar 206 and the second encapsulation layer 204 can be ground so that the top surface of the first encapsulation layer 203, the second encapsulation layer 204 and the first metal pillar 206 are flush with the top surface of the bridge chip 202, thereby achieving consistency and flatness of the surface of the packaging structure 2a.

[0142] refer to Figure 29 , providing a solder mask layer 208.

[0143] Here, a solder resist layer 208 may be disposed on the third molding layer 207 to form a second packaging structure 3 a .

[0144] Although the present invention has been described and illustrated with reference to specific embodiments of the present invention, these descriptions and illustrations do not limit the present invention. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present invention and the actual implementation. There may be other embodiments of the present invention that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present invention. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present invention.

Claims

1. A packaging structure, characterized in that: include: A heterogeneous substrate includes a core made of glass and a first circuit layer disposed above the core, wherein the first circuit layer has a flat portion disposed on an upper surface of the first circuit layer; The bridge chip is arranged above the flat portion, and the lower surface of the bridge chip is parallel to the flat portion.

2. The packaging structure according to claim 1, wherein: The packaging structure further includes: The first molding layer is configured to cover the upper surface of the first circuit layer.

3. The packaging structure according to claim 2, wherein: The first molding layer includes a concave portion formed by a recessed upper surface, and the concave portion exposes the flat portion.

4. The packaging structure according to claim 3, wherein: In the cross-sectional view, the horizontal width of the flat portion is greater than the horizontal width of the concave portion.

5. The packaging structure according to claim 3, wherein: In the cross-sectional view, the horizontal width of the recess is greater than the horizontal width of the bridge wafer.

6. The packaging structure according to claim 3, wherein: The packaging structure further includes: The second mold sealing layer fills the concave portion.

7. The packaging structure according to claim 6, wherein: Top surfaces of the first encapsulation layer, the second encapsulation layer, and the bridge chip are flush.

8. The packaging structure according to claim 1, wherein: The packaging structure further includes: The adhesive layer is disposed between the bridge chip and the flat portion.

9. The packaging structure according to claim 1, wherein: The packaging structure further includes: The first metal column is disposed on the first circuit layer and electrically connected to the first circuit layer.

10. The packaging structure according to claim 9, wherein: A top surface of the first metal pillar is flush with a top surface of the bridge wafer.

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