Low-EMI driving circuit, chip and electronic equipment

Abstract

The utility model discloses a low-EMI drive circuit, a chip and electronic equipment, and belongs to the technical field of electronic circuits. A first pulse direct current is output through a first variable current source according to a first control signal; the second variable current source conducts the second pulse direct current to the power ground according to the second control signal; the current limiting circuit is used for limiting the first pulse direct current and the second pulse direct current; a parasitic capacitor of the first switching circuit and a parasitic capacitor of the second switching circuit are charged according to the first pulse direct current and are discharged according to the second pulse direct current so as to output a first voltage and a second voltage respectively; the first switching circuit outputs a high-level pulse based on the first voltage; the second switching circuit outputs a low-level pulse based on the second voltage; wherein the high-level pulse and the low-level pulse jointly form a driving signal; the duration of the edge of the pulse direct current is greater than the preset duration; at most one of the first variable current source and the second variable current source works at the same moment; and the electromagnetic radiation of the driving circuit is reduced.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and in particular relates to a low-EMI driving circuit and chip, and electronic equipment. Background Art

[0002] Related low electromagnetic interference (EMI) drive circuits usually use filter inductors and filter capacitors to suppress spike voltages to reduce electromagnetic radiation; however, this method can only suppress the electromagnetic radiation caused by spike voltages, and cannot eliminate the electromagnetic radiation generated by the pulses of the drive signal itself.

[0003] Moreover, in the field of chip design, for example, in the circuit design of chip products such as digital audio power amplifiers and motor driver chips, when the internal driving circuit part of the chip encounters EMI (electromagnetic interference) design problems, the above-mentioned method of setting the filter inductor and filter capacitor will also cause the filter inductor and filter capacitor to occupy a larger layout area, and due to different process angles under different processes, the inductance value of the filter inductor and the capacitance value of the filter capacitor have large errors and poor accuracy.

[0004] Therefore, the related low-EMI driving circuit has poor EMI suppression capability, poor accuracy and a large layout area. Utility Model Content

[0005] The purpose of this application is to provide a low-EMI driving circuit, chip, and electronic device, aiming to solve the problems of poor EMI suppression capability, poor precision, and large layout area of ​​related low-EMI driving circuits.

[0006] The embodiment of the present application provides a low EMI driving circuit, including:

[0007] a first variable current source, configured to receive a first control signal and output a first pulsed direct current according to the first control signal;

[0008] a second variable current source, configured to receive a second control signal and conduct a second pulsed direct current to a power ground according to the second control signal;

[0009] a current limiting circuit, connected between the first variable current source and the second variable current source, for limiting the current of the first pulsed direct current and the second pulsed direct current;

[0010] The parasitic capacitance of the first switching circuit is configured to be charged according to the first pulsed direct current and discharged according to the second pulsed direct current to output a first voltage;

[0011] The parasitic capacitance of the second switching circuit is configured to be charged according to the first pulsed direct current and discharged according to the second pulsed direct current to output a second voltage;

[0012] a first switch circuit, connected to the current limiting circuit and the first variable current source, configured to output a high-level pulse based on a first voltage;

[0013] a second switch circuit, connected to the current limiting circuit and the second variable current source, configured to output a low-level pulse based on a second voltage;

[0014] Among them, the high-level pulse and the low-level pulse together constitute a driving signal; the edge duration of the pulsed direct current is greater than a preset duration; at the same time, at most one of the first variable current source and the second variable current source works.

[0015] In one embodiment, the first variable current source includes n first current sources and n first switches;

[0016] The positive electrodes of the n first current sources are commonly connected to a power supply;

[0017] The negative electrodes of the first current sources are connected to the first ends of the first switches in a one-to-one correspondence;

[0018] The second ends of the n first switches serve together as a first pulsed direct current output end of the first variable current source, connected to the current limiting circuit, the first switch, and the parasitic capacitance of the first switch to output the first pulsed direct current;

[0019] The control terminal of the i-th first switch serves as the i-th first sub-control signal input terminal of the first variable current source to receive the i-th first sub-control signal;

[0020] The first control signal includes n first sub-control signals, where n is an integer greater than 1, and i is a positive integer less than or equal to n;

[0021] Under the control of the first control signal, the first switch from the first switch to the nth switch is sequentially turned on, and the first switch from the nth switch to the first switch is sequentially turned off.

[0022] In one embodiment, the second variable current source includes m second current sources and m second switches;

[0023] The positive electrodes of the m second current sources serve together as a second pulsed direct current input terminal of the second variable current source, and are connected to the current limiting circuit, the second switch, and the parasitic capacitance of the second switch to receive the second pulsed direct current;

[0024] The negative electrodes of the second current sources are connected to the first terminals of the second switches in a one-to-one correspondence;

[0025] The second ends of the m second switches are commonly connected to the power ground;

[0026] The control terminal of the j-th second switch serves as the j-th second sub-control signal input terminal of the second variable current source to receive the j-th second sub-control signal;

[0027] The second control signal includes m second sub-control signals, where m is an integer greater than 1, and j is a positive integer less than or equal to m;

[0028] Under the control of the second control signal, the first second switch to the mth second switch are sequentially turned on, and the nth second switch to the first second switch are sequentially turned off.

[0029] In one embodiment, the first variable current source includes a third current source and a first field effect transistor;

[0030] The positive electrode of the third current source is connected to the power supply;

[0031] The cathode of the third current source is connected to the drain of the first field effect transistor;

[0032] The source of the first field effect transistor serves as a first pulsed direct current output end of the first variable current source, and is connected to the current limiting circuit, the first switch, and the parasitic capacitance of the first switch to output the first pulsed direct current;

[0033] The gate of the first field effect transistor serves as a first control signal input terminal of the first variable current source to receive the first control signal;

[0034] The edge duration of the first control signal is greater than a preset duration.

[0035] In one embodiment, the second variable current source includes a fourth current source and a second field effect transistor;

[0036] The positive electrode of the fourth current source serves as the second pulsed direct current input terminal of the second variable current source, and is connected to the current limiting circuit, the second switch, and the parasitic capacitance of the second switch to receive the second pulsed direct current;

[0037] The cathode of the fourth current source is connected to the drain of the second field effect transistor;

[0038] The source of the second field effect transistor is connected to the power ground;

[0039] The gate of the second field effect transistor serves as a second control signal input terminal of the first variable current source to receive the second control signal;

[0040] The duration of the edge of the second control signal is greater than a preset duration.

[0041] In one embodiment, the current limiting circuit includes a first resistor;

[0042] The first end of the first resistor serves as a first pulsed direct current input end and a second pulsed direct current input end of the current limiting circuit, and is connected to the first variable current source, the first switch, and the parasitic capacitance of the first switch to receive the first pulsed direct current and the second pulsed direct current;

[0043] The second end of the first resistor serves as the first pulsed DC output end and the second pulsed DC output end of the current limiting circuit, and is connected to the second variable current source, the second switch and the parasitic capacitance of the second switch to output the first pulsed DC and the second pulsed DC.

[0044] In one embodiment, the first switch circuit includes a first PMOS transistor;

[0045] The source of the first PMOS tube is connected to a power supply;

[0046] The gate of the first PMOS transistor serves as a first voltage input terminal of the first switch circuit, and is connected to the first variable current source and the current limiting circuit to access the first voltage;

[0047] The drain of the first PMOS transistor serves as a high-level pulse output terminal of the first switch circuit and is connected to the second switch to output the high-level pulse;

[0048] The parasitic capacitance of the first PMOS transistor is the parasitic capacitance of the first switch circuit.

[0049] In one embodiment, the second switch circuit includes a first NMOS transistor;

[0050] The source of the first NMOS tube is connected to the power ground;

[0051] The gate of the first NMOS transistor serves as a second voltage input terminal of the second switch circuit, and is connected to the second variable current source and the current limiting circuit to access the second voltage;

[0052] The drain of the first NMOS transistor serves as a low-level pulse output terminal of the second switch circuit and is connected to the first switch to output the low-level pulse;

[0053] The parasitic capacitance of the first NMOS transistor is the parasitic capacitance of the second switch circuit.

[0054] The utility model embodiment further provides a chip, the chip includes low EMI's drive circuit of above.

[0055] The utility model embodiment further provides an electronic equipment, the electronic equipment includes low EMI's drive circuit of above.

[0056] The utility model embodiment compared with prior art has the beneficial effect that because the length of the edge of the first pulse direct current is greater than the preset length, the slope of the first voltage rise is reduced, the rising edge length of the high level pulse is increased, and the length of the edge of the second pulse direct current is greater than the preset length, the slope of the second voltage drop is reduced, the falling edge length of the low level pulse is increased, the length of the edge of the drive signal is increased, the rising time and the falling time of the drive waveform are increased, and the electromagnetic radiation of the drive circuit is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical utility model in the utility model embodiment, the drawings needed to be used in the embodiment description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained according to these drawings without creative labor.

[0058] Figure 1 A structural schematic diagram of the low EMI drive circuit provided by an embodiment of the application is shown in the figure.

[0059] Figure 2 A partial example circuit schematic diagram of the low EMI drive circuit provided by an embodiment of the application is shown in the figure.

[0060] Figure 3 Another partial example circuit schematic diagram of the low EMI drive circuit provided by an embodiment of the application is shown in the figure.

[0061] Figure 4 A waveform diagram of the low EMI drive circuit is shown in the figure. Figure 2

[0062] A waveform diagram of the low EMI drive circuit is shown in the figure. Figure 5 Figure 3 A waveform diagram of the low EMI drive circuit is shown in the figure. DETAILED DESCRIPTION

[0063] ​In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0064] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0065] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0067] Figure 1 The following is a schematic diagram showing the structure of a low EMI driving circuit provided by a preferred embodiment of the present application. For ease of explanation, only the parts related to this embodiment are shown, which are described in detail as follows:

[0068] The low EMI driving circuit includes a first variable current source 01 , a second variable current source 02 , a current limiting circuit 03 , a first switch circuit 04 , a second switch circuit 05 , a parasitic capacitor CP1 of the first switch circuit 04 , and a parasitic capacitor CN1 of the second switch circuit 05 .

[0069] The first variable current source 01 is used to receive a first control signal and output a first pulsed direct current according to the first control signal.

[0070] The second variable current source O2 is used to receive the second control signal and conduct the second pulsed direct current to the power ground according to the second control signal.

[0071] The current limiting circuit 03 is connected between the first variable current source 01 and the second variable current source 02 and is used to limit the current of the first pulse direct current and the second pulse direct current.

[0072] The parasitic capacitor CP1 of the first switch circuit 04 is configured to be charged according to the first pulsed direct current and discharged according to the second pulsed direct current to output a first voltage V1 .

[0073] The parasitic capacitor CN1 of the second switch circuit 05 is configured to be charged according to the first pulsed direct current and discharged according to the second pulsed direct current to output a second voltage V2.

[0074] The first switch circuit 04 is connected to the current limiting circuit 03 and the first variable current source 01 , and is configured to output a high-level pulse based on the first voltage V1 .

[0075] The second switch circuit 05 is connected to the current limiting circuit 03 and the second variable current source 02 , and is configured to output a low-level pulse based on the second voltage V2 .

[0076] Among them, the high-level pulse and the low-level pulse together constitute the driving signal VOUT; the edge duration of the pulsed direct current is greater than the preset duration; at the same time, at most one of the first variable current source 01 and the second variable current source 02 is working.

[0077] Figure 2 FIG1 shows a partial exemplary circuit structure of a low EMI driving circuit provided by an embodiment of the present utility model. Figure 3 Another exemplary circuit structure of a low EMI driving circuit provided by an embodiment of the present invention is shown. For ease of illustration, only the portion related to the embodiment of the present invention is shown, and is described in detail as follows:

[0078] like Figure 2 As shown, the first variable current source O1 includes n first current sources I1 and n first switches K1.

[0079] The positive electrodes of the n first current sources I1 are commonly connected to the power supply VDD; the negative electrodes of the first current sources I1 are connected one-to-one with the first ends of the first switches K1; the second ends of the n first switches K1 serve together as the first pulsed direct current output end of the first variable current source 01, and are connected to the current limiting circuit 03, the first switch 04 and the parasitic capacitor CP1 of the first switch 04 to output the first pulsed direct current; the control end of the i-th first switch K1 serves as the i-th first sub-control signal input end of the first variable current source 01 to receive the i-th first sub-control signal; wherein the first control signal includes n first sub-control signals, n is an integer greater than 1, and i is a positive integer less than or equal to n; under the control of the first control signal, the 1st first switch 04 to the nth first switch 04 are turned on in sequence, and the nth first switch 04 to the 1st first switch 04 are turned off in sequence.

[0080] It is understood that the first through nth first sub-control signals sequentially transition to active levels, and the nth through 1st first sub-control signals sequentially transition to inactive levels. The first current source I1 may be a current mirror; the currents of the first through nth first current sources I1 sequentially increase.

[0081] The first variable current source 01 includes n first current sources I1 and n first switches K1, so that each first switch K1 is turned on and off in sequence. The first control signal is only a digital signal, so the control circuit of the low EMI driving circuit is a digital circuit, which simplifies the design of the above control circuit.

[0082] like Figure 2 As shown, the second variable current source O2 includes m second current sources I2 and m second switches K2.

[0083] The positive electrodes of the m second current sources I2 serve together as the second pulsed direct current input terminal of the second variable current source 02, and are connected to the current limiting circuit 03, the second switch 05 and the parasitic capacitor CN1 of the second switch 05 to receive the second pulsed direct current; the negative electrodes of each second current source I2 are connected one-to-one with the first terminals of each second switch K2; the second terminals of the m second switches K2 are commonly connected to the power ground; the control terminal of the jth second switch K2 serves as the jth second sub-control signal input terminal of the second variable current source 02 to receive the jth second sub-control signal; wherein the second control signal includes m second sub-control signals, m is an integer greater than 1, and j is a positive integer less than or equal to m; under the control of the second control signal, the first second switch 05 to the mth second switch 05 are turned on in sequence, and the nth second switch 05 to the first second switch 05 are turned off in sequence.

[0084] It is understood that the first through mth second sub-control signals sequentially transition to active levels, and the mth through first second sub-control signals sequentially transition to inactive levels. The second current source I2 may be a current mirror; the currents of the first through mth second current sources I2 sequentially decrease.

[0085] The second variable current source 02 includes m second current sources I2 and m second switches K2, so that each second switch K2 is turned on and off in sequence, and the second control signal is only a digital signal, so that the control circuit of the low EMI drive circuit is a digital circuit, which simplifies the design of the above control circuit.

[0086] like Figure 3 As shown, the first variable current source O1 includes a third current source I3 and a first field effect transistor M1.

[0087] The positive electrode of the third current source I3 is connected to the power supply VDD; the negative electrode of the third current source I3 is connected to the drain of the first field effect transistor M1; the source of the first field effect transistor M1 serves as the first pulse direct current output end of the first variable current source 01, and is connected to the current limiting circuit 03, the first switch 04 and the parasitic capacitor CP1 of the first switch 04 to output the first pulse direct current; the gate of the first field effect transistor M1 serves as the first control signal input end of the first variable current source 01 to receive the first control signal.

[0088] The edge duration of the first control signal is greater than the preset duration, that is, the first control signal is an analog signal. The first variable current source 01 only includes a current source and a field effect transistor, so the circuit of the first variable current source 01 is simple.

[0089] like Figure 3 As shown, the second variable current source O2 includes a fourth current source I4 and a second field effect transistor M2.

[0090] The positive electrode of the fourth current source I4 serves as the second pulse direct current input terminal of the second variable current source 02, and is connected to the current limiting circuit 03, the second switch 05 and the parasitic capacitor CN1 of the second switch 05 to access the second pulse direct current; the negative electrode of the fourth current source I4 is connected to the drain of the second field effect transistor M2; the source of the second field effect transistor M2 is connected to the power ground; the gate of the second field effect transistor M2 serves as the second control signal input terminal of the first variable current source 01 to access the second control signal; the edge duration of the second control signal is greater than the preset duration.

[0091] The edge duration of the second control signal is greater than the preset duration, that is, the second control signal is an analog signal. The second variable current source 02 only includes a current source and a field effect transistor, so the circuit of the second variable current source 02 is simple.

[0092] like Figure 2 and Figure 3 As shown, the current limiting circuit 03 includes a first resistor R1.

[0093] The first end of the first resistor R1 serves as the first pulse DC input end and the second pulse DC input end of the current limiting circuit 03, and is connected to the first variable current source 01, the first switch 04 and the parasitic capacitor CP1 of the first switch 04 to connect to the first pulse DC and the second pulse DC; the second end of the first resistor R1 serves as the first pulse DC output end and the second pulse DC output end of the current limiting circuit 03, and is connected to the second variable current source 02, the second switch 05 and the parasitic capacitor CN1 of the second switch 05 to output the first pulse DC and the second pulse DC.

[0094] like Figure 2 and Figure 3 As shown, the first switch circuit 04 includes a first PMOS transistor PM1.

[0095] The source of the first PMOS transistor PM1 is connected to the power supply VDD; the gate of the first PMOS transistor PM1 serves as the first voltage V1 input terminal of the first switch circuit 04, and is connected to the first variable current source 01 and the current limiting circuit 03 to access the first voltage V1; the drain of the first PMOS transistor PM1 serves as the high-level pulse output terminal of the first switch circuit 04, and is connected to the second switch circuit 05 to output a high-level pulse; wherein the parasitic capacitance CP1 of the first PMOS transistor PM1 is the parasitic capacitance CP1 of the first switch circuit 04.

[0096] It is understood that the parasitic capacitor CP1 of the first PMOS transistor PM1 is charged by the first pulsed DC power and discharged by the second pulsed DC power to output the first voltage V1. The parasitic capacitor CP1 of the first PMOS transistor PM1 is the equivalent capacitance of the electrode of the gate of the first PMOS transistor PM1 to ground.

[0097] like Figure 2 and Figure 3 As shown, the second switch circuit 05 includes a first NMOS transistor NM1.

[0098] The source of the first NMOS transistor NM1 is connected to the power ground; the gate of the first NMOS transistor NM1 serves as the second voltage V2 input terminal of the second switch circuit 05, and is connected to the second variable current source 02 and the current limiting circuit 03 to receive the second voltage V2; the drain of the first NMOS transistor NM1 serves as the low-level pulse output terminal of the second switch circuit 05, and is connected to the first switch circuit 04 to output a low-level pulse; wherein the parasitic capacitor CN1 of the first NMOS transistor NM1 is the parasitic capacitor CN1 of the second switch circuit 05.

[0099] It is understood that the first NMOS transistor NM1 is charged by the first pulsed DC power and discharged by the second pulsed DC power to output the second voltage V2. The parasitic capacitance CN1 of the first NMOS transistor NM1 is the equivalent capacitance of the electrode of the gate of the first NMOS transistor NM1 to ground.

[0100] The following is combined with the working principle Figures 2 to 3 As shown for further explanation:

[0101] Figure 2 The waveform of the low EMI drive circuit is shown in Figure 4 It is worth emphasizing that Figure 4 Taking three first current sources I1 and three second current sources I2 as an example, at time T0 to T1 (during duration t11), the first first sub-control signal S11 to the third first sub-control signal S13 sequentially jump to the active level, the first pulsed DC output of the first variable current source O1 increases in a step-wise manner, the waveform of the first voltage V1 output by the parasitic capacitor of the first PMOS transistor PM1 increases in a step-wise manner during this duration t11, and the waveform of the second voltage V2 output by the parasitic capacitor of the first NMOS transistor NM1 slowly increases during this duration t11 and reaches a maximum value between time T1 and T2 (during duration t12), causing the first NMOS transistor NM1 to output a low-level pulse, wherein the falling edge of the low-level pulse slowly decreases during durations t11 and t12. Then, from time T3 to T4, the third first sub-control signal S13 to the first first sub-control signal S11 successively jump to the invalid level, and from time T4 to T5 (within the time length t21), the first second sub-control signal S21 to the third second sub-control signal S23 successively jump to the valid level. The second pulsed direct current flowing through the second variable current source O2 increases stepwise within the time length t21, and the waveform of the second voltage V2 output by the parasitic capacitance of the first NMOS tube NM1 decreases stepwise within the time length t21. The waveform of the second voltage V2 output by the parasitic capacitance of the first PMOS tube PM1 decreases stepwise within the time length t21. The waveform of the first voltage V1 slowly decreases within the time duration t21 and reaches a minimum value at the subsequent time T5 to T6 (within the time duration t22). The first PMOS transistor PM1 outputs a high-level pulse, wherein the rising edge of the high-level pulse slowly increases within the time durations t21 and t22. Then, at the time durations T7 to T8, the third second sub-control signal S23 to the first second sub-control signal S21 successively jump to an invalid level; thereafter, the first first sub-control signal to the third first sub-control signal successively jump to a valid level within the time duration t11, and the above steps are repeated.

[0102] Figure 3 The waveform of the low EMI drive circuit is shown in Figure 5As shown, at T0 to T1 moment (in time t11), the first control signal S1 jumps to the active level, the waveform of the first pulse direct current output by the first variable current source 01 increases in a ramp shape, the waveform of the first voltage V1 output by the parasitic capacitance of the first PMOS tube PM1 gradually rises in the time t11, the waveform of the second voltage V2 output by the parasitic capacitance of the first NMOS tube NM1 slowly increases in the time t11, and reaches the maximum value at the subsequent T1 to T2 moment (in time t12), so that the first NMOS tube NM1 outputs a low level pulse, wherein the falling edge of the low level pulse slowly decreases in the time t11 and the time t12. Then, at T3 to T4 moment, the first control signal S1 jumps to the inactive level, at T4 to T5 moment (in time t21), the second control signal S2 jumps to the active level, the waveform of the second pulse direct current flowing through the second variable current source 02 increases in a ramp shape in the time t21, the waveform of the second voltage V2 output by the parasitic capacitance of the first NMOS tube NM1 decreases in a ramp shape in the time t21, the waveform of the first voltage V1 output by the parasitic capacitance of the first PMOS tube PM1 slowly decreases in the time t21, and reaches the minimum value at the subsequent T5 to T6 moment (in time t22), the first PMOS tube PM1 outputs a high level pulse, wherein the rising edge of the high level pulse slowly increases in the time t21 and the time t22, and then, at T7 to T8 moment, the second control signal S2 jumps to the inactive level in turn; after that, the first control signal S1 jumps to the active level in the time t11, and the above steps are repeated.

[0103] It should be noted that the time constant of the time t12 is R1C N1 , and the time constant of the time t22 is R1C P1 .

[0104] In the design of the circuit, different temperature coefficients of the resistors can be selected according to the design needs to achieve better effects under different temperature conditions. For example, the first resistor R1 with a negative temperature coefficient can be taken, and the delay time is reduced under high temperature conditions to compensate for other delay characteristics of the circuit.

[0105] The chip includes the low-EMI driving circuit.

[0106] The electronic device includes the low-EMI driving circuit.

[0107] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the application.

[0108] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A low EMI driving circuit, characterized in that: include: a first variable current source, configured to receive a first control signal and output a first pulsed direct current according to the first control signal; a second variable current source, configured to receive a second control signal and conduct a second pulsed direct current to a power ground according to the second control signal; a current limiting circuit, connected between the first variable current source and the second variable current source, for limiting the current of the first pulsed direct current and the second pulsed direct current; The parasitic capacitance of the first switching circuit is configured to be charged according to the first pulsed direct current and discharged according to the second pulsed direct current to output a first voltage; The parasitic capacitance of the second switching circuit is configured to be charged according to the first pulsed direct current and discharged according to the second pulsed direct current to output a second voltage; a first switch circuit, connected to the current limiting circuit and the first variable current source, configured to output a high-level pulse based on a first voltage; a second switch circuit, connected to the current limiting circuit and the second variable current source, configured to output a low-level pulse based on a second voltage; The high-level pulse and the low-level pulse together constitute a driving signal; the edge duration of the pulsed direct current is greater than a preset duration; and at the same time, at most one of the first variable current source and the second variable current source works.

2. The low EMI driving circuit according to claim 1, wherein: The first variable current source includes n first current sources and n first switches; The positive electrodes of the n first current sources are commonly connected to a power supply; The negative electrodes of the first current sources are connected to the first ends of the first switches in a one-to-one correspondence; The second ends of the n first switches serve together as a first pulsed direct current output end of the first variable current source, connected to the current limiting circuit, the first switch, and the parasitic capacitance of the first switch to output the first pulsed direct current; The control terminal of the i-th first switch serves as the i-th first sub-control signal input terminal of the first variable current source to receive the i-th first sub-control signal; The first control signal includes n first sub-control signals, where n is an integer greater than 1, and i is a positive integer less than or equal to n; Under the control of the first control signal, the first switch from the first switch to the nth switch is sequentially turned on, and the first switch from the nth switch to the first switch is sequentially turned off.

3. The low EMI driving circuit according to claim 1, wherein: The second variable current source includes m second current sources and m second switches; The positive electrodes of the m second current sources serve together as a second pulsed direct current input terminal of the second variable current source, and are connected to the current limiting circuit, the second switch, and the parasitic capacitance of the second switch to receive the second pulsed direct current; The negative electrodes of the second current sources are connected to the first terminals of the second switches in a one-to-one correspondence; The second ends of the m second switches are commonly connected to the power ground; The control terminal of the j-th second switch serves as the j-th second sub-control signal input terminal of the second variable current source to receive the j-th second sub-control signal; The second control signal includes m second sub-control signals, where m is an integer greater than 1, and j is a positive integer less than or equal to m; Under the control of the second control signal, the first second switch to the mth second switch are sequentially turned on, and the nth second switch to the first second switch are sequentially turned off.

4. The low EMI driving circuit according to claim 1, wherein: The first variable current source includes a third current source and a first field effect transistor; The positive electrode of the third current source is connected to the power supply; The cathode of the third current source is connected to the drain of the first field effect transistor; The source of the first field effect transistor serves as a first pulsed direct current output end of the first variable current source, and is connected to the current limiting circuit, the first switch, and the parasitic capacitance of the first switch to output the first pulsed direct current; The gate of the first field effect transistor serves as a first control signal input terminal of the first variable current source to receive the first control signal; The duration of the edge of the first control signal is greater than a preset duration.

5. The low EMI driving circuit according to claim 1, wherein: The second variable current source includes a fourth current source and a second field effect transistor; The positive electrode of the fourth current source serves as the second pulsed direct current input terminal of the second variable current source, and is connected to the current limiting circuit, the second switch, and the parasitic capacitance of the second switch to receive the second pulsed direct current; The cathode of the fourth current source is connected to the drain of the second field effect transistor; The source of the second field effect transistor is connected to the power ground; The gate of the second field effect transistor serves as a second control signal input terminal of the first variable current source to receive the second control signal; The duration of the edge of the second control signal is greater than a preset duration.

6. The low EMI driving circuit according to claim 1, wherein: The current limiting circuit includes a first resistor; The first end of the first resistor serves as a first pulsed direct current input end and a second pulsed direct current input end of the current limiting circuit, and is connected to the first variable current source, the first switch, and the parasitic capacitance of the first switch to receive the first pulsed direct current and the second pulsed direct current; The second end of the first resistor serves as the first pulsed DC output end and the second pulsed DC output end of the current limiting circuit, and is connected to the second variable current source, the second switch and the parasitic capacitance of the second switch to output the first pulsed DC and the second pulsed DC.

7. The low EMI driving circuit according to any one of claims 1 to 6, wherein: The first switch circuit includes a first PMOS transistor; The source of the first PMOS tube is connected to a power supply; The gate of the first PMOS transistor serves as a first voltage input terminal of the first switch circuit, and is connected to the first variable current source and the current limiting circuit to access the first voltage; The drain of the first PMOS transistor serves as a high-level pulse output terminal of the first switch circuit and is connected to the second switch circuit to output the high-level pulse; The parasitic capacitance of the first PMOS transistor is the parasitic capacitance of the first switch circuit.

8. The low EMI driving circuit according to any one of claims 1 to 6, wherein: The second switch circuit includes a first NMOS transistor; The source of the first NMOS tube is connected to the power ground; The gate of the first NMOS transistor serves as a second voltage input terminal of the second switch circuit, and is connected to the second variable current source and the current limiting circuit to access the second voltage; The drain of the first NMOS transistor serves as a low-level pulse output terminal of the second switch circuit and is connected to the first switch circuit to output the low-level pulse; The parasitic capacitance of the first NMOS transistor is the parasitic capacitance of the second switch circuit.

9. A chip, characterized in that: The chip includes the low EMI driving circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the low EMI driving circuit according to any one of claims 1 to 8.

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