Dual-mode input switching circuit

Abstract

The utility model provides a dual-mode input switching circuit, and relates to the field of switching circuits. Comprising a switching signal input interface, an input interface connected with an external voltage and current element and an output interface connected with an ADC unit, and further comprises a switching circuit, a first switching circuit, a second switching circuit and a resistance circuit which are connected with the switching signal input interface, the first switching circuit and the second switching circuit are both connected with the resistance circuit through electrical switches, the output interface is connected with the resistance circuit, and the switching circuit outputs different signals according to a voltage or current element connected with the input interface, so that the first switching circuit or the second switching circuit is switched on, and different resistors in the resistance circuit are switched on; in this way, the ADC unit collects different voltages, so that the circuit can be suitable for voltage and current modes, and independent circuits do not need to be arranged for the voltage and current modes.

Description

Technical Field

[0001] The utility model relates to a switching circuit, in particular to a dual-mode input switching circuit, belonging to the technical field of circuit design. Background Art

[0002] Voltage and current mode refers to using voltage or current as a control signal to adjust the circuit's operating state. In industrial automation, sensors often output both current and voltage signals, so the corresponding interface circuit must be configured for either current or voltage mode. However, configuring interface circuits for both voltage and current modes would undoubtedly increase circuit complexity. Therefore, it is necessary to provide a circuit that can operate in both voltage and current modes, eliminating the need for separate interface circuits for current and voltage modes. Utility Model Content

[0003] The utility model is implemented through the following technical solutions: a dual-mode input switching circuit, including a switching signal input interface, an input interface connected to an external voltage and current element, and an output interface connected to an ADC unit, and further including a switching circuit 5 connected to the switching signal input interface, a first switch circuit 7, a second switch circuit 6, and a resistor circuit 4, the switching circuit 5 is connected to the first switch circuit 7, the first switch circuit 7 and the second switch circuit 6 are both electrically connected to the resistor circuit 4, and the output interface is connected to the resistor circuit 4;

[0004] The input interface includes a first input interface 10 and a second input interface 11. An overvoltage protection circuit is provided between the first input interface 10 and the second input interface 11. The overvoltage protection circuit includes two TVS tubes. The first input interface 10 and the second input interface 11 are both grounded through the TVS tubes.

[0005] The switching circuit 5 includes an NPN transistor Q8-A and a PNP transistor Q7-A, the base of the NPN transistor Q8-A is connected to the switching signal input interface through a resistor R14-B, and the emitter is connected to a negative 2.5V power supply;

[0006] The base of the PNP transistor Q7-A is connected to the collector of the NPN transistor Q8-A, and the emitter of the PNP transistor Q7-A is connected to the power supply;

[0007] The first switch circuit 7 includes a MOS transistor Q4-A and a MOS transistor Q4-B. The sources of the MOS transistors Q4-A and Q4-B are connected to a +2.5V power supply via a resistor R10-A. The gates of the MOS transistors Q4-A and Q4-B are connected to the collector of a PNP transistor Q7-A. The drain of the MOS transistor Q4-B is grounded, and the drain of the MOS transistor Q4-A is connected to the second output interface 21 via a protection element F3.

[0008] Preferably, the second input interface 11 is provided with an anti-reverse connection circuit, and the anti-reverse connection circuit includes a protection device F2 and a capacitor C31 connected in parallel between the second input interface 11 and the ground.

[0009] Preferably, the second switching circuit 6 includes MOS transistors Q5-A, Q5-B, Q6-A, and Q6-B. MOS transistor Q5-A is connected to the gate of MOS transistor Q5-B, which is connected to the collector of NPN transistor Q8-A. The gates of MOS transistors Q6-A and Q6-B are both connected to the collector of NPN transistor Q8-A. The sources of MOS transistors Q5-A and Q5-B, and the sources of MOS transistors Q6-A and Q6-B are all connected to a +2.5V power supply via resistor R10-B. The drain of MOS transistor Q6-A is connected to the second output interface 21, and the drains of MOS transistors Q6-B and MOS transistor Q5-B are connected to the second input interface 11. MOS transistor Q5-A is connected to the first output interface 20 via a parallel resistor R9 and capacitor 24.

[0010] Preferably, the resistance circuit 4 includes a resistor R6 and a resistor R7, wherein the resistor R6 and the resistor R7 are connected in parallel, one end of each resistor R6 and the resistor R7 are connected to the first input interface 10, the other end of each resistor R6 and the resistor R7 are connected to one end of the protection element F3, and the other end of each resistor R6 and the resistor R7 are connected to the drain of the MOS tube Q6-A through the resistor R11.

[0011] Preferably, the resistance circuit 4 further includes a resistor R8 and a resistor R12, and the resistor R8 and the resistor R12 are connected in series between the first input interface 10 and the first output interface 20, one end of the resistor R8 and the resistor R6 are connected to one end of the resistor R7, and the other end of the resistor R8 and the resistor R9 are connected to one end of the capacitor C24.

[0012] The utility model provides a dual-mode input switching circuit, which has the following beneficial effects:

[0013] The present invention causes the switching circuit to output different signals according to the voltage or current element connected to the input interface, thereby turning on the first or second switch circuit and turning on different resistors in the resistance circuit. In this way, the ADC unit collects different voltages. This makes it applicable to both voltage and current modes, without the need to set up separate circuits for the voltage and current modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural diagram for implementing the utility model. DETAILED DESCRIPTION

[0015] Please see the attached Figure 1 , an embodiment of the utility model provides a dual-mode input switching circuit, including an input interface connected to an external voltage and current element and an output interface connected to an ADC unit, and also including a switching circuit 5 connected to the switching signal input interface, a first switch circuit 7, a second switch circuit 6 and a resistor circuit 4, the switching circuit 5 is connected to the first switch circuit 7, the first switch circuit 7 and the second switch circuit 6 are both electrically connected to the resistor circuit 4, and the output interface is connected to the resistor circuit 4. According to the signal input by the switching signal input interface according to the type of element connected to the input interface, the first switch circuit 7 or the second switch circuit 6 is turned on, and the resistor circuit 4 outputs different resistance values;

[0016] The input interface includes a first input interface 10 and a second input interface 11. An overvoltage protection circuit is provided between the first input interface 10 and the second input interface 11. The overvoltage protection circuit includes two TVS tubes. The first input interface 10 and the second input interface 11 are both grounded through the TVS tubes.

[0017] The switching circuit 5 includes an NPN transistor Q8-A and a PNP transistor Q7-A. The base of the NPN transistor Q8-A is connected to the switching signal input interface through a resistor R14-B, and the emitter is connected to a negative 2.5V power supply.

[0018] The base of the PNP transistor Q7-A is connected to the collector of the NPN transistor Q8-A, and the emitter of the PNP transistor Q7-A is connected to the power supply;

[0019] The first switch circuit 7 includes a MOS transistor Q4-A and a MOS transistor Q4-B. The sources of the MOS transistors Q4-A and Q4-B are both connected to a +2.5V power supply via a resistor R10-A. The gates of the MOS transistors Q4-A and Q4-B are both connected to the collector of a PNP transistor Q7-A. The drain of the MOS transistor Q4-B is grounded, and the drain of the MOS transistor Q4-A is connected to the second output interface 21 via a protection element F3.

[0020] The second input interface 11 is provided with an anti-reverse connection circuit, which includes a protection device F2 and a capacitor C31 connected in parallel between the second input interface 11 and the ground.

[0021] The second switch circuit 6 includes MOS transistors Q5-A, Q5-B, Q6-A, and Q6-B. MOS transistor Q5-A is connected to the gate of MOS transistor Q5-B, which is connected to the collector of NPN transistor Q8-A. The gates of MOS transistors Q6-A and Q6-B are both connected to the collector of NPN transistor Q8-A. The sources of MOS transistors Q5-A and Q5-B, and the sources of MOS transistors Q6-A and Q6-B are all connected to a +2.5V power supply via resistor R10-B. The drain of MOS transistor Q6-A is connected to the second output interface 21, while the drains of MOS transistors Q6-B and Q5-B are connected to the second input interface 11. MOS transistor Q5-A is connected to the first output interface 20 via a parallel resistor R9 and capacitor 24.

[0022] The resistor circuit 4 includes a resistor R6 and a resistor R7, which are connected in parallel. One end of each resistor R6 and resistor R7 is connected to the first input interface 10, and the other end of each resistor R6 and resistor R7 is connected to one end of the protection element F3. The other end of each resistor R6 and resistor R7 is connected to the drain of the MOS transistor Q6-A through the resistor R11.

[0023] The resistor circuit 4 also includes a resistor R8 and a resistor R12. The resistor R8 and the resistor R12 are connected in series between the first input interface 10 and the first output interface 20. One end of the resistor R8 and the resistor R6 are connected to one end of the resistor R7. The other end of the resistor R8 and the resistor R9 are connected to one end of the capacitor C24.

[0024] When a current signal is connected (i.e., current mode), the switching signal input interface 30 is set to a high potential (such as connected to the MCU's GPIO, output 1), the NPN transistor Q8-A is turned on, the base of the PNP transistor Q7-A is turned on at a low level, and the MOS transistor Q4-A and the MOS transistor Q4-B are turned on, thus forming a parallel circuit of the resistor R6 and the resistor R7. In this way, the first and second output interfaces 20 and 21 collect the voltage across the resistor R6 and output it to the ADC unit. At this time, the second switch circuit 6 is not turned on.

[0025] When a voltage signal is applied (voltage mode), the switching signal input interface 30 is set to a low voltage (e.g., connected to the MCU's GPIO, e.g., outputting 0), NPN transistor Q8-A and PNP transistor Q7-A are turned off, and the second switch circuit 6 is turned on. Resistors R8, R9, MOS transistors Q5-A, and Q5-B form a path. Thus, the first and second output interfaces 20 and 21 collect the divided voltage on resistor R9 and output it to the ADC unit. Because the ADC unit's input voltage is 0-3.3V, if the input voltage exceeds this range, resistors R8 and R9 divide the voltage to obtain the appropriate output voltage.

[0026] In addition, the first input interface 10 and the second input interface 11 are further connected to inductors L1 and L2 , and high-frequency interference signals can be suppressed by the inductors L1 and L2 .

[0027] Compared with the prior art, the present invention causes the switching circuit to output different signals according to the voltage or current element connected to the input interface, thereby turning on the first or second switch circuit and different resistors in the resistance circuit. In this way, the ADC unit collects different voltages. This makes it applicable to both voltage and current modes, and there is no need to set up separate circuits for voltage and current modes.

[0028] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements are intended to fall within the scope of the present invention. The scope of protection claimed in this invention is defined by the appended claims and their equivalents.

Claims

1. A dual-mode input switching circuit, comprising a switching signal input interface, an input interface connected to external voltage and current components, and an output interface connected to an ADC unit, characterized in that: It also includes a switching circuit (5) connected to the switching signal input interface, a first switch circuit (7), a second switch circuit (6) and a resistance circuit (4), wherein the switching circuit (5) is connected to the first switch circuit (7), the first switch circuit (7) and the second switch circuit (6) are both electrically connected to the resistance circuit (4), and the output interface is connected to the resistance circuit (4); The input interface comprises a first input interface (10) and a second input interface (11); an overvoltage protection circuit is provided between the first input interface (10) and the second input interface (11); the overvoltage protection circuit comprises two TVS tubes; the first input interface (10) and the second input interface (11) are both grounded via the TVS tubes; The switching circuit (5) includes an emitter, an NPN transistor Q8-A and a PNP transistor Q7-A, the base of the NPN transistor Q8-A is connected to the switching signal input interface via a resistor R14-B, and the emitter is connected to a negative 2.5V power supply; The base of the PNP transistor Q7-A is connected to the collector of the NPN transistor Q8-A, and the emitter of the PNP transistor Q7-A is connected to the power supply; The first switch circuit (7) includes a MOS transistor Q4-A and a MOS transistor Q4-B, wherein the sources of the MOS transistor Q4-A and the MOS transistor Q4-B are connected to a +2.5V power supply via a resistor R10-A; the gates of the MOS transistor Q4-A and the MOS transistor Q4-B are connected to the collector of a PNP-type triode Q7-A; the drain of the MOS transistor Q4-B is grounded, and the drain of the MOS transistor Q4-A is connected to a second output interface (21) via a protection element F3.

2. The dual-mode input switching circuit according to claim 1, wherein: The second input interface (11) is provided with an anti-reverse connection circuit, which comprises a protection device F2 and a capacitor C31 connected in parallel between the second input interface (11) and the ground.

3. The dual-mode input switching circuit according to claim 1, wherein: The second switch circuit (6) comprises MOS transistors Q5-A, Q5-B, Q6-A, and Q6-B. The MOS transistor Q5-A is connected to the gate of the MOS transistor Q5-B, the MOS transistor Q5-A is connected to the collector of the NPN transistor Q8-A, and the gates of the MOS transistors Q6-A and Q6-B are both connected to the collector of the NPN transistor Q8-A. The sources of the MOS transistors Q5-A and Q5-B, and the sources of the MOS transistors Q6-A and Q6-B are all connected to a +2.5V power supply via a resistor R10-B. The drain of the MOS transistor Q6-A is connected to the second output interface (21), and the drains of the MOS transistors Q6-B and Q5-B are connected to the second input interface (11). The MOS transistor Q5-A is connected to the first output interface (20) via a resistor R9 and a capacitor C24 connected in parallel.

4. The dual-mode input switching circuit according to claim 1, wherein: The resistor circuit (4) includes a resistor R6 and a resistor R7, wherein the resistor R6 and the resistor R7 are connected in parallel, one end of each resistor R6 and the resistor R7 are connected to the first input interface (10), the other end of each resistor R6 and the resistor R7 are connected to one end of the protection element F3, and the other end of each resistor R6 and the resistor R7 are connected to the drain of the MOS tube Q6-A via a resistor R11.

5. The dual-mode input switching circuit according to claim 1, wherein: The resistance circuit (4) further includes a resistor R8 and a resistor R12, wherein the resistor R8 and the resistor R12 are connected in series between the first input interface (10) and the first output interface (20), one end of the resistor R8 and the resistor R6 are both connected to one end of the resistor R7, and the other end of the resistor R8 and the resistor R9 are both connected to one end of the capacitor C24.

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