Electronic circuit

Abstract

The utility model relates to an electronic circuit. An electronic circuit includes: a reference voltage circuit; and a circuit for checking a start-up operation of the reference voltage circuit. The reference voltage circuit includes a first stack of first and second transistors that receive first and second control signals, respectively. The startup check circuit includes a first basic test circuit including a second stack of third and fourth transistors receiving first and second control signals, respectively. An output of the first basic test circuit transmits a first binary signal indicative of a correct start-up operation of the reference voltage circuit.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of priority of French Patent Application No. 2211019, filed on October 24, 2022, the contents of which are hereby incorporated by reference in its entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present disclosure relates generally to reference voltage circuits, and in particular to electronic circuits comprising a reference voltage circuit and a circuit for checking the start-up operation, i.e. the booting, of the reference voltage circuit. BACKGROUND

[0004] A reference voltage circuit is an electronic circuit that delivers a reference voltage, i.e. a constant voltage substantially independent of temperature and supply voltage. This reference voltage is used by other elements of the electronic circuit. The reference voltage circuit is powered by a voltage source external to the electronic circuit.

[0005] For certain applications, for example for banking applications, it is necessary to verify that the reference voltage circuit is correctly booted when the supply voltage increases from zero volts to the nominal value. For this purpose, the electronic circuit comprises a start-up check circuit that can replicate the overall structure of the reference voltage circuit. The reference voltage circuit delivers a test signal representative of the state of the internal nodes and this test signal is compared with the same signal delivered by the start-up check circuit. If the start-up operation of the reference voltage circuit occurs normally, it is assumed that the test signals delivered by the reference voltage circuit and the start-up check circuit must be identical. When the test signals delivered by the reference circuit and the start-up check circuit are different, it means that the start-up operation of the reference voltage circuit did not occur correctly.

[0006] The drawback of such a start-up check circuit is that, because it generally replicates the structure of the reference voltage circuit, it has a complex structure and it occupies a considerable surface area in the total surface area of the electronic circuit, in particular when this circuit is formed in an integrated manner.

[0007] There is a need in the art to overcome all or part of the drawbacks of known electronic circuits comprising a reference voltage circuit and a circuit for checking the start-up operation of the reference voltage circuit. SUMMARY

[0008] According to one aspect of the present application, an electronic circuit is disclosed, characterized in that the electronic circuit comprises: a reference voltage circuit; and a start-up check circuit configured to check a start-up operation of the reference voltage circuit; wherein the reference voltage circuit comprises: at least one first stack of a first transistor and a second transistor, wherein the first transistor comprises a first control terminal configured to receive a first control signal, and wherein the second transistor comprises a second control terminal configured to receive a second control signal; wherein the start-up check circuit comprises: at least one first basic test circuit comprising a second stack of a third transistor and a fourth transistor configured to transmit a first binary signal, wherein the third transistor is of the same type as the first transistor and comprises a third control terminal configured to receive the first control signal, and wherein the fourth transistor is of the same type as the second transistor and comprises a fourth control terminal configured to receive the second control signal.

[0009] According to at least one embodiment of the present application, the reference voltage circuit is configured to be connected to a source of a supply voltage and a source of a reference potential, wherein the first transistor and the second transistor are coupled in series between the source of the supply voltage and the source of the reference potential, and wherein the third transistor and the fourth transistor are coupled in series between the source of the supply voltage and the source of the reference potential.

[0010] According to at least one embodiment of the present application, the first transistor, the second transistor, the third transistor, and the fourth transistor are MOS transistors.

[0011] According to at least one embodiment of the present application, the first transistor and the second transistor are of the same type, wherein the first basic test circuit further comprises a fifth transistor in series with a sixth transistor, wherein the fifth transistor comprises a fifth control terminal configured to receive the first control signal, wherein the sixth transistor comprises a sixth control terminal configured to receive a signal at an intermediate node of the second stack, and wherein the first binary signal corresponds to a voltage at a junction node between the fifth transistor and the sixth transistor.

[0012] According to at least one embodiment of the present application, the reference voltage circuit further comprises at least one third stack of seventh and eighth transistors, wherein the seventh transistor comprises a seventh control terminal configured to receive a third control signal, and wherein the eighth transistor comprises an eighth control terminal configured to receive a fourth control signal; and the start-up check circuit further comprises at least one second basic test circuit comprising a fourth stack of ninth and tenth transistors configured to transmit a second binary signal, wherein the ninth transistor is of the same type as the seventh transistor and comprises a ninth control terminal configured to receive the third control signal, and wherein the tenth transistor is of the same type as the eighth transistor and comprises a tenth control terminal configured to receive the fourth control signal.

[0013] According to at least one embodiment of the present application, the third control signal is the same as the first control signal.

[0014] According to at least one embodiment of the present application, the reference voltage circuit is configured to be connected to a source of a supply voltage and a source of a reference potential, wherein the first and second transistors are coupled in series between the source of the supply voltage and the source of the reference potential, and wherein the third and fourth transistors are coupled in series between the source of the supply voltage and the source of the reference potential.

[0015] According to at least one embodiment of the present application, the seventh and eighth transistors are coupled in series between the source of the supply voltage and the source of the reference potential, and wherein the ninth and tenth transistors are coupled in series between the source of the supply voltage and the source of the reference potential.

[0016] According to at least one embodiment of the present application, the seventh and eighth transistors are of different types, and wherein the second binary signal corresponds to a voltage at a junction node between the ninth and tenth transistors.

[0017] According to at least one embodiment of the present application, the seventh, eighth, ninth, and tenth transistors are MOS transistors.

[0018] According to at least one embodiment of the present application, the electronic circuit further comprises: a proportional-to-absolute temperature (PTAT) circuit; a first amplification stage; and a second amplification stage; wherein the first amplification stage comprises eleventh and twelfth transistors; and wherein the second control signal is a voltage at a power terminal of the eleventh transistor, and the fourth control signal is a voltage at a power terminal of the twelfth transistor.

[0019] According to one aspect of the present application, an electronic circuit is disclosed, characterized in that the electronic circuit comprises: a reference voltage circuit comprising a first transistor stack; and a start-up check circuit configured to check a start-up operation of the reference voltage circuit; wherein the start-up check circuit comprises a second transistor stack; wherein the second transistor stack is a replica of the first transistor stack; wherein one or more signals input to the first transistor stack are also input to the second transistor stack; and wherein an output of the second transistor stack provides a first test signal.

[0020] According to at least one embodiment of the present application, the reference voltage circuit further comprises a third transistor stack; the start-up check circuit further comprises a fourth transistor stack; the fourth transistor stack is a replica of the third transistor stack; one or more signals input to the third transistor stack are also input to the fourth transistor stack; and an output of the fourth transistor stack provides a second test signal.

[0021] According to at least one embodiment of the present application, the electronic circuit further comprises a logic circuit configured to logically combine the first test signal and the second test signal to generate a test output signal indicative of a correct start-up operation of the reference voltage circuit.

[0022] According to at least one embodiment of the present application, the reference voltage circuit is configured to be connected to a source of a supply voltage and a source of a reference potential, wherein the first transistor stack is coupled between the source of the supply voltage and the source of the reference potential, and wherein the second transistor stack is coupled between the source of the supply voltage and the source of the reference potential.

[0023] In one embodiment, when these circuits are formed in an integrated manner, the area occupied by the start-up check circuit is reduced relative to the area occupied by the reference voltage circuit.

[0024] In one embodiment, the start-up check circuit is simple in structure.

[0025] An electronic circuit comprises a reference voltage circuit and a circuit for checking a start-up operation of the reference voltage circuit. The reference voltage circuit comprises at least one first stack of a first transistor and a second transistor, the first transistor comprising a first control terminal receiving a first control signal, the second transistor comprising a second control terminal receiving a second control signal. The start-up check circuit comprises at least one first basic test circuit comprising a second stack of a third transistor and a fourth transistor, the third transistor being of the same type as the first transistor and comprising a third control terminal receiving the first control signal, the fourth transistor being of the same type as the second transistor and comprising a fourth control terminal receiving the second control signal, the first basic test circuit being configured to transmit a first binary signal.

[0026] According to one embodiment, the reference voltage circuit is intended to be connected to a source of a supply voltage and to a source of a reference potential. The first transistor and the second transistor are coupled in series between the source of the supply voltage and the source of the reference potential, and the third transistor and the second transistor are coupled in series between the source of the supply voltage and the source of the reference potential.

[0027] According to one embodiment, the first transistor, the second transistor, the third transistor and the fourth transistor are MOS transistors.

[0028] According to one embodiment, the first transistor is of the same type as the second transistor, and the first basic test circuit further comprises a fifth transistor in series with a sixth transistor, the fifth transistor comprising a fifth control terminal receiving the first control signal, and the sixth transistor comprising a sixth control terminal receiving a signal at an intermediate node of the second stack, the first binary signal corresponding to a voltage at a junction node between the fifth transistor and the sixth transistor.

[0029] According to one embodiment, the reference voltage circuit comprises at least one third stack of a seventh transistor and an eighth transistor, the seventh transistor comprising a seventh control terminal receiving a third control signal, the eighth transistor comprising an eighth control terminal receiving a fourth control signal, and the start-up check circuit comprises at least one second basic test circuit comprising a fourth stack of a ninth transistor and a tenth transistor, the ninth transistor being of the same type as the seventh transistor and comprising a ninth control terminal receiving the third control signal, the tenth transistor being of the same type as the eighth transistor and comprising a tenth control terminal receiving the fourth control signal, the second basic test circuit being configured to transmit a second binary signal.

[0030] According to one embodiment, the third control signal is the same as the first control signal.

[0031] According to one embodiment, the seventh transistor and the eighth transistor are coupled in series between a source of the supply voltage and a source of the reference potential, and the ninth transistor and the tenth transistor are coupled in series between a source of the supply voltage and a source of the reference potential.

[0032] According to one embodiment, the seventh transistor and the eighth transistor are of different types, and the second binary signal corresponds to a voltage at a junction node between the ninth transistor and the tenth transistor.

[0033] According to one embodiment, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are MOS transistors.

[0034] According to one embodiment, the electronic circuit comprises: an absolute temperature proportional (PTAT) circuit; a first amplification stage; and a second amplification stage, the first amplification stage comprising an eleventh transistor and a twelfth transistor, and the second control signal is a voltage at a power terminal of the eleventh transistor, and the fourth control signal is a voltage at a power terminal of the twelfth transistor.

[0035] One embodiment also provides a method of designing an electronic circuit comprising a reference voltage circuit and a circuit for checking a start-up operation of the reference voltage circuit, the method comprising the steps of: determining at least one first stack of a first transistor and a second transistor in the reference voltage circuit, the first transistor comprising a first control terminal receiving a first control signal, the second transistor comprising a second control terminal receiving a second control signal; and adding at least one first basic test circuit in a start-up check circuit, the at least one first basic test circuit comprising a second stack of a third transistor and a fourth transistor, the third transistor being of the same type as the first transistor and comprising a third control terminal receiving the first control signal, the fourth transistor being of the same type as the second transistor and comprising a fourth control terminal receiving the second control signal, the first basic test circuit being configured to transmit a first binary signal. BRIEF DESCRIPTION OF DRAWINGS

[0036] The above features and advantages and other will be more fully described in the remaining disclosure of specific embodiments given by way of illustration and not limitation, below with reference to the drawings, in which:

[0037] Figure 1 shows an electrical diagram of a reference voltage circuit and a start-up check circuit;

[0038] Figure 2One embodiment of a reference voltage circuit is shown;

[0039] Figure 3 is a block diagram of one embodiment of a circuit for checking start-up operation of a reference voltage circuit;

[0040] Figure 4 One embodiment of a circuit including a reference voltage circuit and a start-up check circuit is shown; Figure 2

[0041] Figure 5 One embodiment of a basic test circuit for a start-up check circuit is shown; Figure 4

[0042] Figure 6 One embodiment of another basic test circuit for a start-up check circuit is shown; Figure 4

[0043] Figure 7 A timing diagram showing voltages of the circuit of Figure 2

[0044] Figure 8 Another embodiment of a reference voltage circuit is shown. DETAILED DESCRIPTION

[0045] In the various drawings, like features have been designated by like reference numerals. In particular, structural and / or functional features common among the various embodiments can have the same reference numerals and can have the same structural, dimensional, and material properties. For the sake of clarity, only the steps and elements necessary for an understanding of the embodiments described herein have been illustrated and described.

[0046] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection in the absence of any intervening elements other than a conductor, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0047] Unless otherwise specified, the expressions "about," "approximately," "substantially," and "around" mean within 10% and preferably within 5%.

[0048] ​​​​Also, a "binary signal" is a signal that alternates between a first constant state (e.g. a low state, labelled "0") and a second constant state (e.g. a high state, labelled "1"). The high and low states of different binary signals of the same electronic circuit can be different. In fact, a binary signal can correspond to a voltage or current that can not be perfectly constant in the high or low state. In the following description, the source and drain of a MOS transistor are referred to as "power terminals" of the MOS transistor, and the collector and emitter of a bipolar transistor are referred to as "power terminals" of the bipolar transistor. Also, the gate of a MOS transistor is referred to as a "control terminal" of the MOS transistor, and the base of a bipolar transistor is referred to as a "control terminal" of the bipolar transistor. Also, when talking about a voltage at a node, the difference between the potential at said node and a reference potential (e.g. ground, considered equal to 0 V) is considered, unless otherwise indicated.

[0049] Figure 1 Partially and schematically shown is an electronic circuit 10 comprising a reference voltage circuit 12, which is powered by a supply voltage Vcc and which delivers a reference voltage Vbg, i.e. a voltage that is substantially constant and independent of temperature and supply voltage.

[0050] For certain applications, e.g. for banking applications, it is necessary to check whether the reference voltage circuit 12 has been started correctly when the supply voltage Vcc increases from 0 to a nominal value. For this purpose, the electronic circuit 10 comprises a start-up check circuit 14. According to an example, the start-up check circuit 14 can partly or wholly replicate the structure of the reference voltage circuit 12 (in other words, a replica circuit is used). The reference voltage circuit 12 delivers a binary signal Checkl that is representative of the state of the internal nodes of the reference voltage circuit 12, and the start-up check circuit 14 delivers the same binary signal Check2. A logic circuit 16 (e.g. an AND-type logic gate) receives as input the binary signals Checkl and Check2 and delivers a binary signal Check. If the start-up operation of the reference voltage circuit 12 has occurred properly, it is assumed that the binary signal Checkl and the binary signal Check2 must be identical. The binary signal Check is for example in the logic state "1". When the binary signal Check is in the logic state "0", this means that the start-up operation of the reference voltage circuit 12 has not occurred properly.

[0051] A drawback of the check circuit 14 is that, since it at least partly replicates the structure of the reference voltage circuit 12, it has a complex structure and, when the circuit 10 is formed in an integrated manner, it occupies a considerable surface area out of the total surface area of the circuit 10.

[0052] Figure 2 is an electrical diagram of one embodiment of a reference voltage circuit 20.

[0053] The reference voltage circuit 20 comprises a proportional-to-absolute temperature (PTAT) circuit 30 for transmitting a bias voltage pbias, a first amplification stage 40 and a second amplification stage 50.

[0054] The PTAT circuit 30 comprises a bipolar transistor TB1, for example of NPN type, whose emitter is coupled, preferably connected, to one terminal of a resistor R1, whose other terminal is coupled, preferably connected, to a source of low reference potential GND, for example ground, a bipolar transistor TB2, for example of NPN type, whose emitter is coupled, preferably connected, to a source of low reference potential GND and whose base is coupled, preferably connected, to the collector of the bipolar transistor TB2 and to the base of the bipolar transistor TB1, an insulated gate field effect transistor TM1, also known as MOS transistor, for example with P channel, whose source is coupled, preferably connected, to a source of power supply voltage Vcc, whose drain is coupled, preferably connected, to the collector of the bipolar transistor TB1 and whose gate is coupled, preferably connected, to the drain, and a MOS transistor TM2, for example with P channel, whose source is coupled, preferably connected, to a source of power supply voltage Vcc, whose drain is coupled, preferably connected, to the collector of the bipolar transistor TB2 and whose gate is coupled to the gate of the MOS transistor TM1. The voltage pbias refers to the voltage at the gate of the MOS transistor TM2.

[0055] The reference voltage circuit 20 further comprises a circuit for starting the PTAT circuit 30, in Figure 2 not shown in the figure.

[0056] The first amplification stage 40 comprises a bipolar transistor TB3, for example of the NPN type, the emitter of which is coupled, preferably connected, to one terminal of a resistor R3, the other terminal of which is coupled, preferably connected, to a source of low reference potential GND; a bipolar transistor TB4, for example of the NPN type, the base of which is coupled, preferably connected, to the base of the bipolar transistor TB3; a MOS transistor TM3, for example with P channel, the source of which is coupled, preferably connected, to a source of supply voltage Vcc, the drain of which is coupled, preferably connected, to the collector C TB3 of the bipolar transistor TB3, and the gate of which is coupled, preferably connected, to the gate of the MOS transistor TM2; a MOS transistor TM4, for example with P channel, the source of which is coupled, preferably connected, to a source of supply voltage Vcc, the drain of which is coupled, preferably connected, to the collector C TB4 of the bipolar transistor TB4, and the gate of which is coupled, preferably connected, to the gate of the MOS transistor TM2; a MOS transistor TM5, for example with P channel, the source of which is coupled, preferably connected, to a source of supply voltage Vcc, and the gate of which is coupled, preferably connected, to the gate of the MOS transistor TM2; a MOS transistor TM6, for example with P channel, the source of which is coupled, preferably connected, to the drain of the transistor TM5, the gate of which is coupled, preferably connected, to the collector C TB3 of the bipolar transistor TB3, and the drain of which is coupled, preferably connected, to a source of low reference potential GND; and a MOS transistor TM7, for example with P channel, the source of which is coupled, preferably connected, to the drain of the MOS transistor TM5, the gate of which is coupled, preferably connected, to the base of the bipolar transistor TB4, and the drain of which is coupled, preferably connected, to the base of the bipolar transistor TB4.

[0057] The second amplification stage 50 comprises a MOS transistor TM8, for example with P channel, the source of which is coupled, preferably connected, to the source of the supply voltage Vcc and the gate of which is coupled, preferably connected, to the gate of the transistor TM2; a MOS transistor TM9, for example with N channel, the source of which is coupled, preferably connected, to the source of the low reference potential GND, the drain of which is coupled, preferably connected, to the drain of the MOS transistor TM8 and the gate of which is coupled, preferably connected, to the collector C TB4 of the transistor TB4; a bipolar transistor TB5, for example of the NPN type, the base of which is coupled, preferably connected, to the drain of the MOS transistor TM9; a MOS transistor TM10, for example with N channel, the drain of which is coupled, preferably connected, to the source of the supply voltage Vcc, the source of which is coupled, preferably connected, to the collector of the bipolar transistor TB5 and the gate of which receives the voltage ncasc; and a resistor R4, one terminal of which is coupled, preferably connected, to the emitter of the bipolar transistor TB5 and the other terminal of which is coupled, preferably connected, to the emitter of the transistor TB4; a resistor R5, one terminal of which is coupled, preferably connected, to the emitter of the bipolar transistor TB4 and the other terminal of which is coupled, preferably connected, to the source of the low reference potential GND; and a resistor R6, one terminal of which is coupled, preferably connected, to the base of the bipolar transistor TB5 and the other terminal of which is coupled, preferably connected, to the source of the low reference potential GND.

[0058] In the remainder of the present disclosure, the voltage Vc TB3 is referred to as the voltage at the collector C TB3 of the bipolar transistor TB3 and the voltage Vc TB4 is referred to as the voltage at the collector C TB4 of the bipolar transistor TB4. The reference voltage Vbg transmitted by the circuit 20 corresponds to the voltage across the resistor R6. As a variant, the MOS transistor TM10 can be absent, so as to avoid the voltage at the collector of the bipolar transistor TB5 rising too high, the collector of the bipolar transistor TB5 then being connected to the source of the supply voltage Vcc.

[0059] Figure 3 is a block diagram of one embodiment of a design method of a start-up check circuit of a reference voltage circuit.

[0060] According to one embodiment, the method comprises a step 60 of analyzing a reference voltage circuit and a step 62 of determining a start-up check circuit adapted for the reference voltage circuit.

[0061] At step 60, an analysis of the reference voltage circuit is performed to determine the most critical MOS and / or bipolar transistor stack of the reference voltage circuit at startup of the reference voltage circuit. The transistor stack includes at least two transistors whose current conduction paths (e.g., source-drain paths of the MOS transistors) are connected in series between a source of the power supply voltage Vcc and a source of the low reference potential GND. The critical stack is a transistor stack of the reference voltage circuit that includes at least two transistors connected in series between a source of the power supply voltage Vcc and a source of the low reference potential GND, and for which, if the power supply voltage Vcc is not sufficiently high, the probability that the voltage at an intermediate node of the stack will not reach the target value is the highest.

[0062] According to one embodiment, the critical stack corresponds to a follower assembly. According to another embodiment, the critical stack corresponds to a branch of transistors comprising a differential pair.

[0063] for Figure 2 In the reference voltage circuit 20 shown in FIG, the first key stack corresponds to the stack formed by MOS transistors TM5 and TM6 forming the follower component. The second key stack corresponds to the stack formed by MOS transistors TM8 and TM9 forming the amplifier component.

[0064] In step 62, a start-up check circuit for the reference voltage circuit is determined. The start-up check circuit includes a basic test circuit for each critical stack determined in step 60. Each basic test circuit receives as input the voltage received by the critical stack being tested, and outputs a binary signal in a first logic state (e.g., logic state "1") when the voltage at the middle node of the critical stack being tested is sufficiently high, and outputs a binary signal in a second logic state (e.g., logic state "0") when the voltage at the middle node of the critical stack being tested is not sufficiently high. Depending on the structure of the reference voltage circuit, the start-up check circuit may include a single basic test circuit, two basic test circuits, or more than two basic test circuits. Preferably, the start-up check circuit includes at least two basic test circuits.

[0065] According to one embodiment, each basic test circuit is a copy of at least a stack of transistors (MOS or bipolar transistors) to be tested. The copied transistor stack of the basic test circuit receives the same signal as the tested transistor stack of the reference voltage circuit. An additional electronic component or components, such as a resistor, a diode, a MOS transistor with a diode assembly, etc., may also be arranged in series with the copied transistor stack of the basic test circuit. The additional electronic component or components are preferably located between the source of the low reference potential GND and the copied stack, and / or between the source of the power supply voltage Vcc and the copied stack, in order to regulate the voltage between the power terminals of the copied transistor stack.

[0066] According to one embodiment, in the case where the key stack under test comprises two MOS transistors of opposite types (e.g. a P-channel MOS transistor and an N-channel MOS transistor), the basic test circuit also comprises a stack of a P-channel MOS transistor and an N-channel MOS transistor, and the basic test signal corresponds to the voltage at the intermediate node between the P-channel MOS transistor and the N-channel MOS transistor. According to one embodiment, in the case where the key stack under test comprises two MOS transistors of the same type (e.g. two P-channel MOS transistors or two N-channel MOS transistors), the basic test circuit also comprises a first stack of two MOS transistors of this type, and further comprises a second stack of a P-channel MOS transistor and an N-channel MOS transistor. The gate of one of the P-channel MOS transistor or the N-channel MOS transistor of the second stack is coupled (preferably connected) to the intermediate node between the two transistors of the same type of the first stack, and the basic test signal corresponds to the voltage at the intermediate node between the P-channel MOS transistor and the N-channel MOS transistor of the second stack.

[0067] Figure 4 A reference voltage circuit 70 is shown assembled, comprising Figure 2 The reference voltage circuit 20 and the start-up check circuit 75 are shown in the middle. The start-up check circuit 75 comprises two basic test circuits 80 and 90. Each basic test circuit 80 and 90 is coupled to a source of supply voltage Vcc and a source of low reference potential GND. The first basic test circuit 80 receives as inputs the voltage Vc_TB3 at the collector C TB3 of the bipolar transistor TB3 and the voltage pbias at the gate of the transistor TM2, and transmits a basic binary test signal TEST1. The second basic test circuit 90 receives as inputs the voltage Vc TB4 at the collector C TB4 of the bipolar transistor TB4 and the voltage pbias at the gate of the transistor TM2, and transmits a basic binary test signal TEST2. According to one embodiment, the test circuit 75 further comprises an AND-type logic gate that receives the basic test signals TEST1 and TEST2 and transmits a binary start-up check signal TEST. When both basic test signals TEST1 and TEST2 are each in the logic state "1", the start-up check signal TEST is in the logic state "1", and when at least one of the basic test signals TEST1 and TEST2 is in the logic state "0", the start-up check signal TEST is in the logic state "0".

[0068] Figure 5 is an electrical diagram of one embodiment of the first basic test circuit 80.

[0069] The basic test circuit 80 comprises: a MOS transistor TM11 (for example, a replica of the transistor TM5) with P channel, whose source is coupled (preferably connected) to a source of the supply voltage Vcc and whose gate receives a voltage pbias; a MOS transistor TM12 (for example, a replica of the transistor TM6) with P channel, whose source is coupled (preferably connected) to the drain of the MOS transistor TM11 and whose gate receives a voltage Vc_TB3 at the collector of the bipolar transistor TB3; a resistor R7, one of whose terminals is coupled (preferably connected) to the drain of the MOS transistor TM12 and the other of whose terminals is coupled (preferably connected) to a source of the low reference potential GND; a MOS transistor TM13 with N channel, whose source is coupled (preferably connected) to a source of the low reference potential GND, whose drain is coupled (preferably connected) to the drain of the MOS transistor TM12 and whose gate is coupled (preferably connected) to the drain of the MOS transistor TM12; a MOS transistor TM14 with P channel, whose source is coupled (preferably connected) to a source of the supply voltage Vcc and whose gate receives a voltage pbias; a MOS transistor TM15 with N channel, whose source is coupled (preferably connected) to a source of the low reference potential GND, whose drain is coupled (preferably connected) to the drain of the MOS transistor TM14 and whose gate is coupled (preferably connected) to the drain of the MOS transistor TM12; and an inverter INV1, the input of which is coupled (preferably connected) to the drain of the transistor TM15.

[0070] The signal transmitted by the inverter INV1 corresponds to the first basic test signal TEST1.

[0071] Figure 6 is an electrical diagram of one embodiment of the second basic test circuit 90.

[0072] The basic test circuit 90 comprises: a MOS transistor TM16 (for example, a replica of the transistor TM8) with P channel, whose source is coupled (preferably connected) to a source of the supply voltage Vcc and whose gate is coupled (preferably connected) to the gate of the MOS transistor TM2; a MOS transistor TM17 (for example, a replica of the transistor TM9) with N channel, whose source is coupled (preferably connected) to a source of the low reference potential GND, whose drain is coupled (preferably connected) to the drain of the transistor TM16 and whose gate receives a voltage Vc_TB4 at the collector of the bipolar transistor TB4; and an inverter INV2, the input of which is coupled (preferably connected) to the drain of the transistor TM17.

[0073] The signal transmitted by the inverter INV2 corresponds to the second basic test signal TEST2. The start-up check circuit 75 has a simple structure and comprises a small number of electronic components. When these circuits are formed in an integrated manner, the surface area occupied by the start-up check circuit 75 is reduced with respect to the surface area occupied by the reference voltage circuit 20.

[0074] Figure 7 A timing diagram showing the voltages during the operation of the circuit 70, in which the circuit 70 comprises the reference voltage circuit 20 equipped with the start-up check circuit 75. In particular, Figure 7 A timing diagram showing the supply voltage Vcc, the reference voltage Vbg, the voltage Vc_TB3 at the collector of the bipolar transistor TB3, the first test signal TEST1, the voltage Vc_TB4 at the collector of the bipolar transistor TB4 and the second test signal TEST2.

[0075] The variation of the voltage Vcc is very slow, Figure 7 The timing diagram of Figure 6 actually represents the static operation of the circuit 75 for different values of the supply voltage Vcc. When the first basic test signal TEST1 is substantially equal to the supply voltage Vcc, it is in the logic state "1" and when it is substantially equal to 0 V, it is in the logic state "0". When the second basic test signal TEST2 is substantially equal to the supply voltage Vcc, it is in the logic state "1" and when it is substantially equal to 0 V, it is in the logic state "0".

[0076] In normal operation, the reference voltage Vbg transmitted by the reference voltage circuit 20 is equal to the desired value, which is currently equal to 1.2 V. In the range PI, i.e. for a supply voltage Vcc greater than approximately 1.4 V, the voltage Vbg has the desired value. In the range PI, the first basic test signal TEST1 is in the logic state "1" and the second basic test signal TEST2 is in the logic state "1". In the range P2, i.e. for a supply voltage Vcc less than 1.4 V, the voltage Vbg is less than the desired value. In the range P2, at least one of the first test signal TEST1 and the second test signal TEST2 is in the logic state "0". It should be noted in particular that, in the range P2, when the supply voltage Vcc is less than approximately 1 V, the first basic test signal TEST1 is in the logic state "0" and when the supply voltage Vcc is greater than approximately 1 V, it is in the logic state "1", and the second basic test signal TEST2 is in the logic state "0" in two different sub-ranges of the supply voltage Vcc, one of which ends at 1.5 V.

[0077] Figure 8 is an electrical diagram of another example of a reference voltage circuit 100.

[0078] The circuit 100 comprises a bipolar transistor TB8, for example of the PNP type, the emitter of which is coupled, preferably connected, to a first terminal of a resistor R8, the collector of which is coupled, preferably connected, to a source of low reference potential GND, and the base of which is coupled, preferably connected, to the collector; a bipolar transistor TB9, for example of the PNP type, the emitter of which is coupled, preferably connected, to a first terminal of a resistor R9, the collector of which is coupled, preferably connected, to a source of low reference potential GND, and the base of which is coupled, preferably connected, to the collector and to the base of the bipolar transistor TB8; a MOS transistor TM18, for example with P channel, the source of which is coupled, preferably connected, to a source of supply voltage Vcc, and the drain of which is coupled, preferably connected, to a second terminal of the resistor R8; a MOS transistor TM19, for example with P channel, the source of which is coupled, preferably connected, to a source of supply voltage Vcc, and the drain of which is coupled, preferably connected, to a second terminal of the resistor R9, and the gate of which is connected to the gate of the MOS transistor TM18; and an operational amplifier OP, the non-inverting input (+) of which is coupled, preferably connected, to the second terminal of the resistor R8, the inverting input (-) of which is coupled, preferably connected, to the first terminal of the resistor R9, and the output of which is coupled, preferably connected, to the gates of the MOS transistors TM18 and TM19.

[0079] The reference voltage circuit 100 transmits to the second terminal of the resistor R9 a reference voltage Vbg. The principle of operation of the reference voltage circuit 100 is as follows: the voltage across the resistor R9 increases with temperature, while the collector-emitter voltage of the bipolar transistor TB9 decreases with temperature, whereby, by choosing the resistors R8 and R9 appropriately, the reference voltage Vbg remains constant with temperature. In more detail, the bipolar transistor TB8 has an amplification factor greater than 1 with respect to the bipolar transistor TB9, whereby the base-emitter voltage Vbe_TB8 of the bipolar transistor TB8 is lower than the base-emitter voltage Vbe_TB9 of the bipolar transistor TB9. The difference AVbe between the voltages Vbe_TB8 and Vbe_TB9 is proportional to the absolute temperature. The operational amplifier OP equalizes the voltage at its inverting input to the voltage at its non-inverting input, so that the current flowing through the resistor R8 is equal to AVbe / R8. The current mirror formed by the MOS transistors TM18 and TM19 makes the current flowing through the resistor R9 also equal to AVbe / R8. The voltage Vbg is then equal to the sum of the voltage across the resistor R9 (equal to R9*AVbe / R8) and the base-emitter voltage of the bipolar transistor TB9. Figure 8 Many variants of the circuit are possible.

[0080] For the reference voltage circuit 100 of Figure 8 the reference voltage circuit 100 of Figure 3Implementations of the described design methodology result in determining at least one critical stack forming a part of an operational amplifier.

[0081] Various embodiments and variations have been described. Those of skill in the art will understand that certain features and variations of the various embodiments can be combined, and that other variations will occur to those of skill in the art.

[0082] Finally, actual implementations of the described embodiments and variations are within the capabilities of those of skill in the art, based on the above given functional description.

Claims

1. An electronic circuit, characterized in that The electronic circuit comprises: a reference voltage circuit; and a startup check circuit configured to check a startup operation of the reference voltage circuit; Wherein, the reference voltage circuit includes: at least one first stack of a first transistor and a second transistor, wherein the first transistor includes a first control terminal configured to receive a first control signal, and wherein the second transistor includes a second control terminal configured to receive a second control signal; Wherein, the startup check circuit includes: At least one first basic test circuit comprising a second stack of a third transistor and a fourth transistor configured to transmit a first binary signal, wherein the third transistor is of the same type as the first transistor and comprises a third control terminal configured to receive the first control signal, and wherein the fourth transistor is of the same type as the second transistor and comprises a fourth control terminal configured to receive the second control signal.

2. The electronic circuit according to claim 1, wherein: The reference voltage circuit is configured to be connected to a source of supply voltage and a source of reference potential, wherein the first transistor and the second transistor are coupled in series between the source of supply voltage and the source of reference potential, and wherein the third transistor and the fourth transistor are coupled in series between the source of supply voltage and the source of reference potential.

3. The electronic circuit according to claim 1, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are MOS transistors.

4. The electronic circuit according to claim 1, wherein: The first transistor and the second transistor are of the same type, wherein the first basic test circuit further comprises a fifth transistor connected in series with a sixth transistor, wherein the fifth transistor comprises a fifth control terminal configured to receive the first control signal, wherein the sixth transistor comprises a sixth control terminal configured to receive a signal at an intermediate node of the second stack, and wherein the first binary signal corresponds to a voltage at a junction node between the fifth transistor and the sixth transistor.

5. The electronic circuit according to claim 1, characterized in that : the reference voltage circuit further comprising at least one third stack of a seventh transistor and an eighth transistor, wherein the seventh transistor comprises a seventh control terminal configured to receive a third control signal, and wherein the eighth transistor comprises an eighth control terminal configured to receive a fourth control signal; and The start-up check circuit further comprises at least one second basic test circuit comprising a fourth stack of a ninth transistor and a tenth transistor configured to transmit a second binary signal, wherein the ninth transistor is of the same type as the seventh transistor and comprises a ninth control terminal configured to receive the third control signal, and wherein the tenth transistor is of the same type as the eighth transistor and comprises a tenth control terminal configured to receive the fourth control signal.

6. The electronic circuit according to claim 5, characterized in that The third control signal is the same as the first control signal.

7. The electronic circuit according to claim 5, characterized in that The reference voltage circuit is configured to be connected to a source of supply voltage and a source of reference potential, wherein the first transistor and the second transistor are coupled in series between the source of supply voltage and the source of reference potential, and wherein the third transistor and the fourth transistor are coupled in series between the source of supply voltage and the source of reference potential.

8. The electronic circuit according to claim 7, wherein: The seventh transistor and the eighth transistor are coupled in series between the source of the supply voltage and the source of the reference potential, and wherein the ninth transistor and the tenth transistor are coupled in series between the source of the supply voltage and the source of the reference potential.

9. The electronic circuit according to claim 5, wherein: The seventh transistor is of a different type than the eighth transistor, and wherein the second binary signal corresponds to a voltage at a junction node between the ninth transistor and the tenth transistor.

10. The electronic circuit according to claim 5, characterized in that The seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are MOS transistors.

11. The electronic circuit according to claim 5, wherein: The electronic circuit further comprises: Proportional to absolute temperature PTAT circuit; a first amplifier stage; and Second amplifier stage; wherein the first amplifying stage comprises an eleventh transistor and a twelfth transistor; and The second control signal is a voltage at a power terminal of the eleventh transistor, and the fourth control signal is a voltage at a power terminal of the twelfth transistor.

12. An electronic circuit, characterized in that: The electronic circuit comprises: a reference voltage circuit comprising a first transistor stack; and a startup check circuit configured to check a startup operation of the reference voltage circuit; Wherein, the startup check circuit includes a second transistor stack; wherein the second transistor stack is a replica of the first transistor stack; wherein one or more signals input to the first transistor stack are also input to the second transistor stack; and The output terminal of the second transistor stack provides a first test signal.

13. The electronic circuit according to claim 12, wherein: The reference voltage circuit further includes a third transistor stack; The startup check circuit further includes a fourth transistor stack; the fourth transistor stack being a replica of the third transistor stack; One or more signals input to the third transistor stack are also input to the fourth transistor stack; as well as An output terminal of the fourth transistor stack provides a second test signal.

14. The electronic circuit according to claim 13, wherein: The electronic circuit further includes a logic circuit configured to logically combine the first test signal and the second test signal to generate a test output signal indicating proper startup operation of the reference voltage circuit.

15. The electronic circuit according to claim 12, wherein: The reference voltage circuit is configured to be connected to a source of supply voltage and a source of reference potential, wherein the first transistor stack is coupled between the source of supply voltage and the source of reference potential, and wherein the second transistor stack is coupled between the source of supply voltage and the source of reference potential.

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