Joining tool

Abstract

The utility model provides a bonding tool for bonding a semiconductor crystal grain to a semiconductor wafer. The bonding tool includes a wafer chuck, an edge support, a hard board, and a buffer layer. The wafer chuck carries a semiconductor wafer and a semiconductor die placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor die are laterally surrounded by the edge support, and a top surface of the edge support is substantially flush with a surface of the semiconductor die. The rigid board is movably disposed over the semiconductor die, the edge support and the wafer chuck. When the hard board moves towards the edge support, the buffer layer is arranged on the bottom surface of the hard board, and the buffer layer is in contact with the top surface of the edge support and the semiconductor die.

Description

TECHNICAL FIELD

[0001] The present application relates to a bonding tool. BACKGROUND

[0002] Semiconductor packages are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor packages are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers or materials on a semiconductor substrate, and using the same to form circuit elements and components thereon. Typically, tens or hundreds of integrated circuits are fabricated on a single semiconductor wafer. Individual dies can be singulated along scribe lines to obtain the integrated circuits. The individual dies can then be individually packaged, for example, in a multi-chip package or other type of package.

[0003] The semiconductor industry continues to improve the packing density of various electronic elements (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more elements to be integrated in a given area. In some applications, these smaller electronic elements (e.g., integrated circuit dies) can also require smaller and reliable packages that use less area than previous packages. SUMMARY

[0004] According to some embodiments of the present application, a bonding tool is provided for bonding a semiconductor die to a semiconductor wafer. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor die placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor die are laterally surrounded by the edge support, and a top surface of the edge support is substantially flush with a surface of the semiconductor die. The hard plate is movably disposed on the semiconductor die, the edge support, and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate when the hard plate is moved toward the edge support, and the buffer layer is in contact with the top surface of the edge support and the semiconductor die.

[0005] According to some other embodiments of the present application, a bonding tool is provided for bonding a semiconductor die to a semiconductor wafer. The bonding tool includes a hard plate, an edge support, and a buffer layer. The hard plate is movably disposed on the semiconductor die. The edge support is disposed on a bottom surface of the hard plate, and the edge support includes an inlet channel and an outlet channel. The buffer layer is passed through the inlet channel and the outlet channel such that the buffer layer is fed between the hard plate and the semiconductor die, wherein the buffer layer is in contact with the semiconductor die and the hard plate when the hard plate and the edge support are moved toward the semiconductor wafer.

[0006] So that the foregoing features and advantages of the present application can be understood in more detail, more particular descriptions of the application will be rendered by reference to the following embodiments, which are suggested as examples of the application and are illustrated in the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1A-1D A chip-on-wafer (CoW) bonding process using a bonder is schematically illustrated in some embodiments of the present disclosure.

[0008] Figure 2 A chip-on-wafer (CoW) bonding process using a bonder is schematically illustrated in some embodiments of the present disclosure. Figures 1A-1D A top view of the relationship between the edge supports, semiconductor wafers, hard plates, and wafer chucks is illustrated.

[0009] Figures 3A-3D A chip-on-wafer (CoW) bonding process using a bonder is schematically illustrated in some embodiments of the present disclosure.

[0010] Figure 4 A chip-on-wafer (CoW) bonding process using a bonder is schematically illustrated in some embodiments of the present disclosure. Figures 3A-3D A top view of the relationship between the edge supports, semiconductor wafers, hard plates, and wafer chucks is illustrated. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments, or examples, for implementing different features of the present application. Specific examples of components and configurations are described herein to facilitate discussion of the present application. It should be understood by those skilled in the art, however, that these specific examples and configurations do not limit the present application. Indeed, any combination of these and / or other components described herein can be used to implement the present application in various examples. In addition, it should be understood by those skilled in the art that throughout descriptions provided herein, that common but well-understood features such as elements sharing structure or function and / or do not contribute to the essence of the aspects of the application can have been reduced in size or eliminated in the interest of clarity and conciseness, and that the present application should not be limited by such omissions. In addition, the present application can repeat the use of reference numbers and / or letters in various examples and / or throughout the following description specifying the application. This repetition of numbers and / or letters is for the purpose of simplicity and clarity and does not preferably imply a common relationship between the elements referred to by such like reference numbers and / or letters throughout the various examples of the application discussed herein.

[0012] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] Embodiments of the present invention may further include other features and processes. For example, the device may include a test structure to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) component. For example, the test structure may include a test pad formed in a redistribution layer or formed on a substrate, and the test pad allows for testing of the 3D package or 3DIC, the use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0014] Figures 1A-1D The figure schematically illustrates a chip-on-wafer (CoW) bonding process performed using a bonding tool in some embodiments of the present disclosure.

[0015] Please refer to Figure 1A , providing a semiconductor wafer 102. In some embodiments, semiconductor wafer 102 includes semiconductor chips arranged in an array, and the semiconductor chips in semiconductor wafer 102 may be logic dies, system-on-chip (SoC) dies, or other suitable semiconductor dies. Semiconductor wafer 102 may include a substrate 102a (e.g., a semiconductor substrate), through-substrate vias 102b embedded in substrate 102a, an interconnect structure 102c disposed on substrate 102a, and a bonding structure 102d disposed on interconnect structure 102c, wherein through-substrate via 102b is electrically connected to interconnect structure 102c. Substrate 102a of semiconductor wafer 102 may include a crystalline silicon wafer. Depending on design requirements, substrate 102a may include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions may be doped with p-type dopants or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured to form n-type fin field-effect transistors (n-type FinFETs) and / or p-type fin field-effect transistors (p-type FinFETs). In alternative embodiments, the substrate 102a may be made of other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0016] The through-substrate via 102b can be formed by etching, grinding, laser techniques, and / or combinations thereof, to form a recess in the substrate 102a. A thin barrier layer can be conformally deposited on the front side of the substrate 102a and in the opening by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, and / or combinations thereof. The barrier layer can include nitride or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, and / or combinations thereof. A conductive material is deposited on the thin barrier layer and in the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, and / or combinations thereof. The conductive material is, for example, copper, tungsten, aluminum, silver, gold, and / or combinations thereof. Excess conductive material and the barrier layer can be removed from the front side of the substrate 102a by, for example, chemical mechanical grinding (CMP). Thus, in some embodiments, the through-substrate via 102b can include a conductive material and a thin barrier layer between the conductive material and the substrate 102a. In some embodiments, the through-substrate via 102b can extend through one or more layers of the interconnect structure 102c and protrude into the substrate 102a. The through-substrate via 102b can be embedded in the substrate 102a and the interconnect structure 102c of the semiconductor wafer 102. At this stage, the through-substrate via 102b is not exposed at the back side of the substrate 102a.

[0017] The interconnect structure 102c can include one or more dielectric layers (e.g., one or more intermediate layers dielectric (ILD) layers, intermetallic dielectric (IMD) layers, or the like) and interconnect lines embedded in the one or more dielectric layers, where the interconnect lines are electrically connected to semiconductor components (e.g., fin field effect transistors) formed in the substrate 102a. The material in the one or more dielectric layers can include silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N y where x > 0 and y > 0), or other suitable dielectric materials. The interconnect lines can include metal lines. For example, the interconnect lines include copper lines, copper pads, aluminum pads, or combinations thereof.

[0018] The bonding structure 102d can include a bonding dielectric layer 102dl and a bonding conductor 102d2 embedded in the bonding dielectric layer 102dl. The material of the bonding dielectric layer 102dl can be silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N y, where x>0 and y>0) or other suitable dielectric materials, and the bonding conductor 102d2 can be a conductive via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding structure 102d can be formed by depositing a dielectric material using a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding dielectric layer 102d1 including openings or through-holes; and filling the openings or through-holes defined in the bonding dielectric layer 102d1 with a conductive material to form a bonding conductor 102d2 embedded in the bonding dielectric layer 102d1.

[0019] In some embodiments, semiconductor wafer 102 includes a semiconductor interposer, such as a silicon interposer or other suitable semiconductor interposer. In some alternative embodiments, semiconductor wafer 102 includes a reconstructed wafer, and the reconstructed wafer may include semiconductor chips arranged side-by-side and laterally encapsulated by an insulating encapsulation package.

[0020] like Figure 1A As shown, the semiconductor wafer 102 is placed on and held by the wafer chuck 110. The wafer chuck 110 may include a vacuum nozzle 112 in communication with a vacuum extractor (not shown) so that the wafer chuck 110 can stably support the semiconductor wafer 102.

[0021] refer to Figure 1B , a semiconductor die 104 is provided onto a semiconductor wafer 102 supported by a wafer chuck 110. The semiconductor chips in the semiconductor wafer 102 and the semiconductor die 104 may perform the same function or different functions. In some embodiments, the semiconductor die 104 and the semiconductor chips in the semiconductor wafer 102 are system-on-chip (SoC) dies that perform the same function or different functions.

[0022] Each semiconductor die 104 may include a substrate 104a (e.g., a semiconductor substrate), an interconnect structure 104b disposed on the substrate 104a, and a bonding structure 104c disposed on the interconnect structure 104b. The substrate 104a of each semiconductor die 104 may include a crystalline silicon wafer. Depending on design requirements, the substrate 104a may include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions may be doped with p-type dopants or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured as n-type fin field effect transistors (n-type FinFETs) and / or p-type fin field effect transistors (p-type FinFETs). In some alternative embodiments, the substrate 104a may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0023] The interconnect structure 104b may include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, or the like) and interconnect wiring embedded in the one or more dielectric layers, wherein the interconnect wiring is electrically connected to the semiconductor device (e.g., fin field effect transistor) formed in the substrate 104a. The material in the one or more dielectric layers may include silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0) or other suitable dielectric materials. The interconnect wiring may include metal wiring. For example, the interconnect wiring includes copper wiring, copper pads, aluminum pads, or a combination thereof.

[0024] The bonding structure 104c may include a bonding dielectric layer 104c1 and a bonding conductor 104c2 embedded in the bonding dielectric layer 104c1. The bonding dielectric layer 104c1 may be made of silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N ywhere x > 0 and y > 0) or other suitable dielectric material, and the bonding conductor 104c2 can be a conductive via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding structure 104c can be formed by depositing a dielectric material by a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process), patterning the dielectric material to form a bonding dielectric layer 104cl including openings or vias, and filling the openings or vias defined in the bonding dielectric layer 104cl with a conductive material to form the bonding conductor 104c2 embedded in the bonding dielectric layer 104cl.

[0025] Referring to Figure 1C The semiconductor die 104 is picked and placed onto the semiconductor wafer 102 through proper alignment. After the semiconductor die 104 is picked and placed onto the semiconductor wafer 102, an edge support 120 is provided on the wafer chuck 110 such that the semiconductor wafer 102 and the semiconductor die 104 are laterally surrounded by the edge support 120. In some embodiments, the edge support 120 is secured on the top surface 120a of the wafer chuck 110, for example, by screws or other suitable securing components, such that the top surface 120a of the edge support 120 is substantially flush with the surface (e.g., the back surface) of the substrate 104a of the semiconductor die 104. In some embodiments, the edge support 120 includes an annular support structure, and the edge support 120 is laterally spaced apart from the semiconductor wafer 102 and the semiconductor die 104 placed on the semiconductor wafer 102.

[0026] After the installation of the edge support 120, a hard plate 130 and a buffer layer 140 carried by the hard plate 130 are provided above the semiconductor die 104 and the semiconductor wafer 102 carried by the wafer chuck 110. The material of the hard plate 130 can be or include polyether ether ketone (PEEK), polyimide (PI), or other suitable plastic material. The buffer layer 140 can be or include a release film or other flexible and buffer film. The buffer layer 140 is provided on a bottom surface 130a of the hard plate 130. After the buffer layer 140 is provided on the bottom surface 130a of the hard plate 130, the buffer layer 140 is located between the hard plate 130 and the semiconductor die 104. The buffer layer 140 can be applied or supplied by a set of rollers 150 so that the buffer layer 140 can be supplied onto the bottom surface 130a of the hard plate 130. The buffer layer 140 can reduce the total thickness variation (TTV) problem of the semiconductor die 104 during a chip-on-wafer (CoW) bonding process performed subsequently. The set of rollers 150 can drive the movement of the buffer layer 140 so that different regions of the buffer layer 140 can be used to minimize the total thickness variation (TTV) problem of the semiconductor die 104 during the chip-on-wafer (CoW) bonding process performed subsequently.

[0027] Reference Figure 1C With Figure 1D After the semiconductor die 104 is picked and placed onto the semiconductor wafer 102, the hard plate 130 is driven to move toward the edge support 120 and the wafer chuck 110 so that the buffer layer 140 can be moved downward until the buffer layer 140 contacts the top surface of the edge support 120 and the surface (e.g., back surface) of the semiconductor die 104. After the buffer layer 140 is pressed onto the top surface of the edge support 120 and the surface (e.g., back surface) of the semiconductor die 104, a gap between the hard plate 130 and the semiconductor wafer 102 can be maintained by the edge support 120 disposed below the hard plate 130. For example, after the buffer layer 140 is pressed onto the semiconductor die 104, the gap between the hard plate 130 and the semiconductor wafer 102 can be maintained by the edge support 120 disposed on the wafer chuck 110.

[0028] After the buffer layer 140 is pressed onto the top surface of the edge support 120 and the surface (e.g., back surface) of the semiconductor die 104, an annealing process is performed so that the bonding structure 104c of the semiconductor die 104 contacts and bonds with the bonding structure 102d of the semiconductor wafer 102. After the annealing process is completed, the chip-on-wafer (CoW) bonding process of the semiconductor die 104 and the semiconductor wafer 102 is completed.

[0029] After the chip-on-wafer (CoW) bonding process described above, a dielectric-to-dielectric bonding interface is formed between the bonding dielectric layer 104c1 and the bonding dielectric layer 102d1, and a metal-to-metal bonding interface is formed between the bonding conductor 104c2 and the bonding conductor 102d2.

[0030] After the semiconductor die 104 is bonded to the semiconductor wafer 102, a chip probing process can be performed to increase yield.

[0031] Figure 2 schematically illustrates Figures 1A-1D a top view of the relationship between the edge support, the semiconductor wafer, the hard plate, and the wafer chuck.

[0032] As Figure 1C , Figure 1D and Figure 2 illustrated, a bonding tool 100 is provided to bond a semiconductor die 104 to a semiconductor wafer 102. The bonding tool 100 in this embodiment includes a wafer chuck 110, an edge support 120, a hard plate 130, and a buffer layer 140. The wafer chuck 110 carries the semiconductor wafer 102 and the semiconductor die 104 placed on the semiconductor wafer 102. The edge support 120 is disposed on the wafer chuck 110, the semiconductor wafer 102 and the semiconductor die 104 are laterally surrounded by the edge support 120, and a top surface 120a of the edge support 120 is substantially flush with a surface of the semiconductor die 104. The hard plate 130 is movably disposed on the semiconductor die 104, the edge support 120, and the wafer chuck 110. The buffer layer 140 is disposed on a bottom surface 130a of the hard plate 130, and the buffer layer 140 contacts the top surface 120a of the edge support 120 and the semiconductor die 104 when the hard plate 130 is moved toward the edge support 120. As Figure 2 illustrated, the wafer chuck 110 can be or include a circular chuck, and the hard plate 130 can be or include a circular hard plate. For example, the hard plate 130 includes a circular hard plate, and a diameter of the annular support structure 120 is less than a diameter of the circular hard plate 130. In addition, the bonding tool 100 can further include a set of rollers 150 to feed the buffer layer 140 onto the bottom surface 130a of the hard plate 130.

[0033] Figures 3A-3D schematically illustrates a chip-on-wafer (CoW) bonding process performed using a bonding tool according to some embodiments of the present disclosure.

[0034] Please refer to Figure 3Asemiconductor die in the semiconductor wafer 102 can be a logic die, a system-on-a-chip (SoC) die, or other suitable semiconductor die. The semiconductor wafer 102 can include a substrate 102a (e.g., a semiconductor substrate), through-substrate vias 102b embedded in the substrate 102a, interconnect structures 102c disposed on the substrate 102a, and bonding structures 102d disposed on the interconnect structures 102c, where the through-substrate vias 102b are electrically connected to the interconnect structures 102c. The substrate 102a of the semiconductor wafer 102 can include a crystalline silicon wafer. Depending on design requirements, the substrate 102a can include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions can be doped with p-type dopants or n-type dopants. The doped regions can be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions can be configured as n-type FinFETs and / or p-type FinFETs. In some alternative embodiments, the substrate 102a can be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0035] The through-substrate via 102b can be formed by forming a recess in the substrate 102a, e.g., by etching, grinding, laser techniques, and / or combinations thereof. A thin barrier layer can be conformally deposited over the front side of the substrate 102a and in the opening, e.g., by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, and / or combinations thereof. The barrier layer can include a nitride or oxynitride, e.g., titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, and / or combinations thereof. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, and / or combinations thereof. The conductive material is, e.g., copper, tungsten, aluminum, silver, gold, and / or combinations thereof. Excess conductive material and the barrier layer can be removed from the front side of the substrate 102a, e.g., by chemical mechanical grinding (CMP). Thus, in some embodiments, the through-substrate via 102b can include a conductive material and a thin barrier layer between the conductive material and the substrate 102a. In some embodiments, the through-substrate via 102b can extend through one or more layers of the interconnect structure 102c and protrude into the substrate 102a. The through-substrate via 102b can be embedded in the substrate 102a and the interconnect structure 102c of the semiconductor wafer 102. At this stage, the through-substrate via 102b is not exposed at the backside of the substrate 102a.

[0036] The interconnect structure 102c can include one or more dielectric layers (e.g., one or more intermediate layers dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect lines embedded in the one or more dielectric layers, where the interconnect lines are electrically connected to semiconductor components (e.g., fin field effect transistors) formed in the substrate 102a. The material of the one or more dielectric layers can include silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N y where x > 0 and y > 0), or other suitable dielectric materials. The interconnect lines can include metal lines. For example, the interconnect lines include copper lines, copper pads, aluminum pads, or combinations thereof.

[0037] The bonding structure 102d can include a bonding dielectric layer 102dl and a bonding conductor 102d2 embedded in the bonding dielectric layer 102dl. The material of the bonding dielectric layer 102dl can be silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N y, where x>0 and y>0) or other suitable dielectric materials, and the bonding conductor 102d2 can be a conductive via (e.g., a copper through-hole), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding structure 102d can be formed by the following steps: depositing a dielectric material by a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding dielectric layer 102d1 including openings or through-holes; and filling the openings or through-holes defined in the bonding dielectric layer 102d1 with a conductive material to form a bonding conductor 102d2 embedded in the bonding dielectric layer 102d1.

[0038] In some embodiments, semiconductor wafer 102 includes a semiconductor interposer, such as a silicon interposer or other suitable semiconductor interposer. In some alternative embodiments, semiconductor wafer 102 includes a reconstituted wafer, and the reconstituted wafer may include semiconductor chips arranged side by side and laterally encapsulated by an insulating encapsulation.

[0039] like Figure 3A As shown, the semiconductor wafer 102 is placed on and secured by a wafer chuck 210. The wafer chuck 210 may include a vacuum nozzle 212 in communication with a vacuum extractor (not shown) so that the wafer chuck 210 can stably support the semiconductor wafer 102.

[0040] refer to Figure 3B A semiconductor die 104 is provided on a semiconductor wafer 102 supported by a wafer chuck 210. The semiconductor die 104 and the semiconductor chips in the semiconductor wafer 102 may perform the same function or different functions. In some embodiments, the semiconductor die 104 and the semiconductor chips in the semiconductor wafer 102 are system-on-chip (SoC) dies that perform the same function or different functions.

[0041] Each semiconductor die 104 can include a substrate 104a (e.g., a semiconductor substrate), an interconnect structure 104b disposed on the substrate 104a, and a bonding structure 104c disposed on the interconnect structure 104b. The substrate 104a of each semiconductor die 104 can include a crystalline silicon wafer. The substrate 104a can include various doped regions (e.g., a p-type substrate or an n-type substrate) depending on design requirements. In some embodiments, the doped regions can be doped with p-type dopants or n-type dopants. The doped regions can be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions can be configured as n-type FinFETs and / or p-type FinFETs. In some alternative embodiments, the substrate 104a can be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0042] The interconnect structure 104b can include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect lines embedded in the one or more dielectric layers, where the interconnect lines are electrically connected to semiconductor components (e.g., FinFETs) formed in the substrate 104a. The material of the one or more dielectric layers can include silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N y where x > 0 and y > 0), or other suitable dielectric materials. The interconnect lines can include metal lines. For example, the interconnect lines include copper lines, copper pads, aluminum pads, or combinations thereof.

[0043] The bonding structure 104c can include a bonding dielectric layer 104c1 and a bonding conductor 104c2 embedded in the bonding dielectric layer 104c1. The material of the bonding dielectric layer 104c1 can be silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N ywhere x > 0 and y > 0) or other suitable dielectric material, and the bonding conductor 104c2 can be a via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding structure 104c can be formed by depositing a dielectric material by a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding dielectric layer 104cl including openings or vias; and filling the openings or vias defined by the bonding dielectric layer 104cl with a conductive material to form the bonding conductor 104c2 embedded in the bonding dielectric layer 104cl.

[0044] Referring to Figure 3C , the semiconductor die 104 is picked and placed onto the semiconductor wafer 102 through proper alignment. After the semiconductor die 104 is picked and placed onto the semiconductor wafer 102, the hard plate 230, the cushion layer 240 carried by the hard plate 230, and the edge support 220 disposed on the bottom surface 230a of the hard plate 230 are provided above the semiconductor die 104 and the semiconductor wafer 102 carried by the wafer chuck 210.

[0045] In some embodiments, the edge support 220 is secured to the bottom surface 230a of the hard plate 230, for example, by screws or other suitable securing components, such that the bottom surface 220a of the edge support 220 is vertically spaced apart from the semiconductor wafer 102. In some embodiments, the edge support 220 includes an annular support structure, and the edge support 220 is laterally and vertically spaced apart from the semiconductor die 104. As shown, the edge support 220 includes a feed-in passage 222 and a feed-out passage 224. The cushion layer 240 passes through the feed-in passage 222 and the feed-out passage 224 such that the cushion layer 240 can be fed between the hard plate 230 and the semiconductor die 104. Figure 3C

[0046] ​The material of the hard plate 230 can be or include polyether ether ketone (PEEK), polyimide (PI), or other suitable plastic material. The buffer layer 240 can be or include a release film or other flexible and cushioning film. The buffer layer 240 is provided between the hard plate 230 and the semiconductor dies 104. At this stage, the buffer layer 240 is vertically spaced apart from the hard plate 230 and the semiconductor dies 104. The buffer layer 240 can be applied or supplied by a set of rollers 250 such that the buffer layer 240 can be supplied between the hard plate 230 and the semiconductor dies 104. The buffer layer 240 can reduce the total thickness variation (TTV) problem of the semiconductor dies 104 during a chip-on-wafer (CoW) bonding process performed later. The set of rollers 250 can drive the movement of the buffer layer 240 such that different regions of the buffer layer 240 can be used to minimize the TTV problem of the semiconductor dies 104 during the chip-on-wafer (CoW) bonding process performed later.

[0047] With reference to Figure 1C With Figure 1D After the semiconductor dies 104 are picked up and placed on the semiconductor wafer 102, the hard plate 330 and the edge support 220 are driven to move towards the wafer chuck 210 such that the buffer layer 240 can be moved downwards until the buffer layer 240 contacts the surface (e.g., the back surface) of the semiconductor dies 104 and the bottom surface 220a of the edge support 220 contacts the semiconductor wafer 102. After the buffer layer 240 is pressed onto the surface (e.g., the back surface) of the semiconductor dies 104 and the bottom surface 220a of the edge support 220 contacts the semiconductor wafer 102, the gap between the hard plate 230 and the semiconductor wafer 102 can be maintained by the edge support 220 disposed below the hard plate 230. For example, after the buffer layer 240 is pressed onto the semiconductor dies 104, the gap between the hard plate 230 and the semiconductor wafer 102 is maintained by the edge support 220 disposed on the semiconductor wafer 102. As shown in FIG. 3B, at this stage, the semiconductor dies 104 are laterally surrounded by the edge support 220. Figure 3D

[0048] After the buffer layer 240 is pressed onto the surface (e.g., the back surface) of the semiconductor dies 104, an annealing process is performed such that the bonding structure 104c of the semiconductor dies 104 contacts and bonds with the bonding structure 102d of the semiconductor wafer 102. After the annealing process is completed, the chip-on-wafer (CoW) bonding process of the semiconductor dies 104 and the semiconductor wafer 102 is completed.

[0049] ​After performing the chip-on-wafer (CoW) bonding process described above, a dielectric-to-dielectric bonding interface is formed between the bonding dielectric layer 104c1 and the bonding dielectric layer 102d1, and a metal-to-metal bonding interface is formed between the bonding conductor 104c2 and the bonding conductor 102d2.

[0050] After bonding the semiconductor die 104 to the semiconductor wafer 102, a die probing process can be performed to increase yield.

[0051] Figure 4 schematically illustrates Figures 3A-3D a top view of the relationship between the edge support, the semiconductor wafer, the hard plate, and the wafer chuck.

[0052] Referring to Figure 4 A bonding tool 200 for bonding a semiconductor die 104 to a semiconductor wafer 102 is provided. The bonding tool 200 of the present embodiment includes a hard plate 230, an edge support 220, and a buffer layer 240. The hard plate 230 is movably disposed above the semiconductor die 104. The edge support 220 is disposed on a bottom surface 230a of the hard plate 230, and the edge support 220 includes an infeed channel 222 and an outfeed channel 224. The buffer layer 240 is fed through the infeed channel 222 and the outfeed channel 224 such that the buffer layer 240 is fed between the hard plate 230 and the semiconductor die 104, wherein the buffer layer 240 contacts the semiconductor die 104 and the hard plate 230 when the hard plate 230 and the edge support 220 are moved toward the semiconductor wafer 102. In some embodiments, the bonding tool 200 can further include a wafer chuck 210, wherein the wafer chuck 210 carries the semiconductor wafer 102 and the semiconductor die 104 placed on the semiconductor wafer 102. In some embodiments, the wafer chuck 210 includes a circular chuck, and the hard plate 230 includes a circular hard plate. In some embodiments, the edge support 220 is disposed between the hard plate 230 and the semiconductor wafer 102. In some embodiments, the edge support 220 contacts the semiconductor wafer 102 when the hard plate 230 and the edge support 220 are moved toward the semiconductor wafer 102. In some embodiments, the edge support 220 includes an annular support structure, and the hard plate 230 includes a circular hard plate. In some embodiments, the diameter of the annular support structure 220 is smaller than the diameter of the circular hard plate 230. In some embodiments, the bonding tool 200 can further include a set of rollers 250 for feeding the buffer layer 240 between the hard plate 230 and the semiconductor die 104.

[0053] In the foregoing bonding tool 100 or 200, a bonding force is applied vertically to the semiconductor die 104, and no lateral bonding force is applied to the semiconductor die 104. Thus, a non-bonding issue occurring at a corner region of the semiconductor die 104 can be minimized, and a yield of a chip-on-wafer (CoW) bonding process of the semiconductor die 104 to the semiconductor wafer 102 can be increased.

[0054] According to some embodiments of the present disclosure, a bonding tool is provided for bonding a semiconductor die to a semiconductor wafer. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor die placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor die are laterally surrounded by the edge support, and a top surface of the edge support is substantially flush with a surface of the semiconductor die. The hard plate is movably disposed on the semiconductor die, the edge support, and the wafer chuck. When the hard plate moves toward the edge support, the buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor die. In some embodiments, the wafer chuck includes a circular chuck, and the hard plate includes a circular hard plate. In some embodiments, the edge support includes an annular support structure, and the edge support is laterally spaced apart from the semiconductor wafer. In some embodiments, the wafer chuck includes a circular chuck, and a diameter of the annular support structure is smaller than a diameter of the circular chuck. In some embodiments, the hard plate includes a circular hard plate, and a diameter of the annular support structure is smaller than a diameter of the circular hard plate. In some embodiments, a material of the hard plate includes polyether ether ketone (PEEK) or polyimide (PI). In some embodiments, the buffer layer includes a release film. In some embodiments, the bonding tool further includes a set of rollers for feeding the buffer layer onto the bottom surface of the hard plate.

[0055] According to some alternative embodiments of the present disclosure, a bonding tool is provided for bonding semiconductor dies to a semiconductor wafer. The bonding tool includes a hard plate, an edge support, and a buffer layer. The hard plate is movably configured over a semiconductor die. The edge support is configured on a bottom surface of the hard plate, and the edge support includes an infeed channel and an outfeed channel. The buffer layer is fed through the infeed channel and the outfeed channel such that the buffer layer is fed between the hard plate and the semiconductor die, wherein the buffer layer contacts the semiconductor die and the hard plate when the hard plate and the edge support are moved toward the semiconductor wafer. In some embodiments, the bonding tool further includes a wafer chuck, wherein the wafer chuck carries the semiconductor wafer and the semiconductor die placed on the semiconductor wafer. In some embodiments, the wafer chuck includes a circular chuck, and the hard plate includes a circular hard plate. In some embodiments, the edge support is configured between the hard plate and the semiconductor wafer. In some embodiments, the edge support contacts the semiconductor wafer when the hard plate and the edge support are moved toward the semiconductor wafer. In some embodiments, the edge support includes an annular support structure, and the hard plate includes a circular hard plate. In some embodiments, a diameter of the annular support structure is less than a diameter of the circular hard plate. In some embodiments, the bonding tool further includes a set of rollers for feeding the buffer layer between the hard plate and the semiconductor die.

[0056] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures as the skilled artisan is not limited to the specifically enumerated embodiments. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A bonding tool suitable for bonding a semiconductor die to a semiconductor wafer, characterized in that: The bonding tool comprises: a wafer chuck, wherein the wafer chuck carries the semiconductor wafer and the semiconductor die placed on the semiconductor wafer; an edge support disposed on the wafer chuck, wherein the semiconductor wafer and the semiconductor die are laterally surrounded by the edge support, and a top surface of the edge support is flush with a surface of the semiconductor die; a hard plate movably disposed over the semiconductor die, the edge support, and the wafer chuck; and A buffer layer is disposed on the bottom surface of the rigid board, wherein when the rigid board moves toward the edge support, the buffer layer contacts the top surface of the edge support and the semiconductor die.

2. The bonding tool according to claim 1, wherein The wafer chuck comprises a circular chuck, and the hard plate comprises a circular hard plate.

3. The joining tool according to claim 1, wherein: The edge support includes an annular support structure, and the edge support is laterally spaced apart from the semiconductor wafer.

4. The bonding tool according to claim 1, wherein: The wafer chuck includes a circular chuck, and the diameter of the annular support structure is smaller than the diameter of the circular chuck.

5. The joining tool according to claim 3, wherein: The hard plate includes a circular hard plate, and the diameter of the annular support structure is smaller than the diameter of the circular hard plate.

6. The bonding tool according to claim 1, wherein: The invention further comprises a set of rollers for feeding the buffer layer onto the bottom surface of the hard board.

7. A bonding tool suitable for bonding a semiconductor die to a semiconductor wafer, characterized in that: The bonding tool comprises: a hard plate, movably disposed on the semiconductor die; an edge support, disposed on the bottom surface of the hard board, the edge support including a feed-in channel and a feed-out channel; and A buffer layer passes through the feed-in channel and the feed-out channel so that the buffer layer is fed between the hard plate and the semiconductor die, wherein when the hard plate and the edge support move toward the semiconductor wafer, the buffer layer contacts the semiconductor die and the hard plate.

8. The joining tool according to claim 7, wherein: Also includes: A wafer chuck is provided, wherein the wafer chuck carries the semiconductor wafer and the semiconductor die placed on the semiconductor wafer.

9. The joining tool according to claim 7, wherein: As the hard plate and the edge support move toward the semiconductor wafer, the edge support contacts the semiconductor wafer.

10. The bonding tool according to claim 7, wherein: The invention further comprises a set of rollers for feeding the buffer layer between the hard plate and the semiconductor die.

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