Wiring packaging structure based on chips of 2nm and below 2nm

Abstract

The utility model discloses a routing packaging structure based on a chip of 2nm and below 2nm, and the structure employs an adapter plate for elevating and transition, enables an ultrathin first chip to be disposed on the adapter plate in an inverted manner, and achieves the high integration between the chip and a substrate. And the height is increased, so that the process difficulty of the metal lead is reduced, and subsequent connection to the first metal contact through the metal lead is facilitated. A first metal contact on the back surface of the first chip and a power supply contact on the back surface of the substrate are bonded together through a metal lead, so that the wafer back power supply of the ultrathin chip is realized, the power transmission path is shorter, the resistance is lower, and the requirement of current transmission is met; and the heat can be more effectively dissipated from the substrate through the metal lead, so that the heat dissipation performance is considered. And due to the design of the adapter plate, an additional heat dissipation space is also provided. And a lead bonding mode is adopted, so that manufacturers producing the packaging structure can adopt an existing mature routing process for packaging, and the difficulty and the cost are reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor packaging, specifically relates to a wire bonding packaging structure based on 2nm and below 2nm chip. BACKGROUND

[0002] With the rapid development of semiconductor technology, chip manufacturing process is constantly advancing to a more fine scale, especially in the 2nm and below 2nm process era, the integration and performance of chips have been unprecedentedly improved. However, this technological progress has also brought many challenges, especially in the field of chip packaging. The traditional packaging technology has been difficult to meet the stringent requirements of these high-end chips on power supply efficiency, thermal management and physical size control. For 2nm and below process chips, their power density increases significantly, combined with the explosive growth of the number of transistors inside the chip, making resistance control of the power supply circuit critical.

[0003] Although there are many packaging structures in the prior art that bond chips through leads, but the power supply requirements for 2nm and below 2nm chips are high, and the power supply process needs to meet the demand of low resistance, large current and heat dissipation capacity; and the traditional wire bonding packaging structure directly bonds the chip on the substrate, which is difficult to operate for such thin chips, and it is difficult to achieve high integration. In addition, the traditional wire bonding packaging structure usually bonds the wire on the front surface of the chip, and the power and signal lines need to pass through the front surface of the chip, occupying a large amount of wiring space, which may increase the resistance and heat, and cannot meet the packaging requirements of 2nm and below 2nm chips.

[0004] Therefore, it is particularly important to develop a packaging structure that can realize low resistance, large current power supply and high heat dissipation capacity. INVENTION CONTENTS

[0005] The utility model overcomes the technical insufficiency, provides a wire bonding packaging structure based on 2nm and below 2nm chip.

[0006] To achieve the above purpose, the utility model adopts the following technical scheme:

[0007] A wire bonding packaging structure based on 2nm and below 2nm chip, including the substrate 1, the substrate 1 is connected with the adapter plate 2 on its upper surface, the first chip 3 of 2nm and below 2nm thickness is flip-chip mounted on the upper surface of the adapter plate 2, a plurality of first metal contacts 31 are arranged on the back surface of the first chip 3, a plurality of back power supply contacts 11 are formed in the substrate 1 according to the number of first metal contacts 31, and the first metal contacts 31 and the back power supply contacts 11 are bonded together by a plurality of metal leads 4.

[0008] Preferably, the substrate 1 forms vertical interlayer via holes 12 inside, and is provided with a multilayer vertical intercommunication circuit layer structure 13 in the interlayer via holes 12, the uppermost circuit layer of the circuit layer structure 13 serving as the back surface power supply contact point 11.

[0009] Preferably, the substrate 1 is provided with downwardly recessed openings 14 at the positions of the circuit layer structure 13, and the lowermost circuit layer of the circuit layer structure 13 is exposed through the openings 14.

[0010] Preferably, the substrate 1 is provided with a chip mounting area 110 and a back surface power supply area 120 arranged in a ring shape around the chip mounting area 110, the substrate 1 is provided with a plurality of first solder balls 5 protruding from the upper surface of the chip mounting area 110, and the circuit layer structure 13 is formed inside the corresponding back surface power supply area 120, and the adapter plate 2 is provided with a plurality of first solder joints 21 corresponding to the first solder balls 5 and connected to the first solder balls 5.

[0011] Preferably, the first solder joints 21 protrude from the lower surface of the adapter plate 2.

[0012] Preferably, the first chip 3 is provided with a plurality of second metal contacts 32 on the front surface, and the adapter plate 2 is provided with second solder joints 22 embedded in the top and connected to the second metal contacts 32.

[0013] Preferably, the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 is filled with a filling adhesive layer 6.

[0014] Preferably, the upper surface of the substrate 1 is provided with a plastic sealing layer 7 for encapsulating all components into one body.

[0015] Compared with the prior art, the utility model has the beneficial effects that:

[0016] 1、The case is through the use of adapter plate as a cushion and transition, the ultra-thin first chip is inverted on the adapter plate, on the one hand, the height integration between the chip and the substrate is realized, so as to significantly reduce the packaging height and physical size, improve the overall space utilization; on the other hand, through the height increase, the process difficulty of the metal lead is reduced, so as to be connected to the first metal contact on the back of the first chip through the metal lead subsequently. The arrangement of bonding the first metal contact on the back of the first chip and the back power supply contact point of the substrate together through the metal lead realizes the back power supply of the ultra-thin chip, on the one hand, the power transmission path is shorter, the resistance is lower, so as to improve the power supply efficiency, reduce the power loss, meet the demand of current transmission; on the other hand, the heat can be more effectively dissipated from the substrate through the metal lead, and the heat dissipation performance is taken into account. Moreover, the design of the adapter plate makes the front of the first chip can also be cooled through the adapter plate, providing additional heat dissipation space. In addition, the application adopts the wire bonding mode, so that the manufacturer producing the packaging structure can adopt the existing mature wire bonding process for packaging, reducing the implementation difficulty and cost. Through reasonable design of the layout and number of metal leads, the heat dissipation path can be further optimized, the heat dissipation performance of the whole packaging structure is improved, so that the first chip with nm and nm thickness can also be packaged, breaking the limitation of packaging such chips, which is conducive to improving the competitiveness. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is the cross-sectional structure schematic diagram of the case.

[0018] Figure 2 is the packaging structure top view of the case hiding the plastic sealing layer and the metal lead.

[0019] Figure 3 is the packaging structure top view of the case hiding the plastic sealing layer. DETAILED DESCRIPTION

[0020] The features of the present application and other related features are further described in detail through the following examples, so as to facilitate the understanding of the same industry technical personnel:

[0021] As Figure 1 and Figure 3As shown, a wire bonding packaging structure based on 2nm and below chip includes a substrate 1, a transition plate 2 connected to the upper surface of the substrate 1, a first chip 3 with a thickness of 2nm and below flip-chip mounted on the upper surface of the transition plate 2, and a plurality of first metal contacts 31 provided on the back surface of the first chip 3. The substrate 1 is internally formed with a plurality of back surface power supply contacts 11 according to the number of the first metal contacts 31. The first metal contacts 31 and the back surface power supply contacts 11 are bonded together by a plurality of metal wires 4. In a specific implementation, the diameter and the number of the metal wires 4 can be flexibly designed according to the requirements of overvoltage and heat dissipation. The metal wires 4 can be gold wires, copper wires, palladium copper wires, or other metal or alloy wires.

[0022] As described above, by using the transition plate 2 as a spacer and a transition, the ultra-thin first chip 3 is flip-chip mounted on the transition plate, which on one hand realizes the height integration between the chip and the substrate, so as to significantly reduce the packaging height and physical size and improve the overall space utilization; on the other hand, by increasing the height, the process difficulty of the metal wires is reduced, so as to be connected to the first metal contacts 31 on the back surface of the first chip 3 through the metal wires. By bonding the first metal contacts 31 on the back surface of the first chip and the back surface power supply contacts 11 of the substrate 1 through the metal wires 4, the back surface power supply of the ultra-thin chip is realized, which on one hand makes the power transmission path shorter and the resistance lower, so as to improve the power supply efficiency, reduce the power loss, and meet the current transmission requirements; on the other hand, the heat can be more effectively dissipated from the substrate through the metal wires, which takes into account the heat dissipation performance. Moreover, the design of the transition plate makes the front surface of the first chip also be able to dissipate heat through the transition plate, which provides additional heat dissipation space. In addition, the wire bonding method adopted by the present application makes the manufacturers producing the packaging structure be able to use the existing mature wire bonding process for packaging, which reduces the implementation difficulty and cost. By reasonably designing the layout and number of the metal wires, the heat dissipation path can be further optimized, the heat dissipation performance of the entire packaging structure is improved, the first chip 3 with a thickness of 2nm and below can be packaged therein, which breaks the limitation of packaging such chips, and is conducive to improving the competitiveness.

[0023] As a specific implementation, the substrate 1 is internally formed with vertical interlayer vias 12, and a plurality of vertically connected circuit layer structures 13 are provided in the interlayer vias 12. The uppermost circuit layer of the circuit layer structure 13 serves as the back surface power supply contact 11.

[0024] As described above, by the arrangement of the vertical interlayer via 12 and the multi-layer circuit layer structure 13, the current can be transmitted vertically between different layers, forming a three-dimensional electrical connection path, further enhancing the stability and reliability of the electrical connection, ensuring that the current can be smoothly transmitted between layers. The uppermost layer of the circuit layer structure 13 as the back surface power supply contact point 11 is arranged, so that the power supply network is more compact and efficient, and the first chip can be directly supplied through the back surface power supply contact point, reducing the loss in the process of power transmission and improving the power supply efficiency. In addition, the vertical interlayer via 12 and the multi-layer circuit layer structure 13 not only serve as electrical connections, but also as heat dissipation channels, so that the heat from the chip and the metal lead can be transmitted inside the substrate through these channels and dissipated to the air through the substrate surface, so as to improve the heat dissipation efficiency, help to reduce the working temperature of the chip and prolong its service life. Moreover, by forming a vertical electrical connection path and a circuit layer structure inside the substrate, higher integration can be achieved without increasing the size of the package.

[0025] As a specific embodiment, 3. The lower surface of the substrate 1 is provided with a downward recessed opening 14 at the position of the circuit layer structure 13, and the lowermost layer of the circuit layer structure 13 is exposed through the opening 14. In this way, the lowermost layer of the circuit layer structure can be directly in contact with the external environment through the opening 14, thereby improving the heat dissipation efficiency. The opening 14 can also expose the lowermost layer of the circuit layer structure, which can facilitate electrical performance testing after packaging, and can also serve as an electrical connection interface to connect with external components or packaging structures.

[0026] As shown in Figure 2 or Figure 3 As shown in the specific implementation, the substrate 1 is provided with a chip mounting area 110 and a back surface power supply area 120 arranged in a ring around the chip mounting area 110, and the substrate 1 is provided with a plurality of first solder balls 5 on the upper surface of the chip mounting area 110, and the circuit layer structure 13 is formed inside the corresponding back surface power supply area 120, and the adapter plate 2 is provided with a plurality of first solder joints 21 corresponding to the first solder balls 5 on the lower surface thereof.

[0027] As described above, the substrate divides the chip mounting area 110 and the back supply area 120, which can reasonably layout the packaging structure and facilitate subsequent packaging. The back supply area 120 is arranged in a ring around the chip mounting area 110. Such a ring-shaped power supply structure can more effectively provide power support for the chip, reduce the resistance and inductance in the power transmission path, thereby reducing the voltage drop and electromagnetic interference, and improving the stability and efficiency of power supply. In addition, the ring arrangement allows the metal lead to form a natural heat dissipation channel with the internal multilayer circuit layer structure 13, which helps to uniformly and quickly conduct the heat generated by the chip. The direct connection between the first solder ball 5 and the first solder point 21 provides a short and direct current path, which helps to reduce inductance and resistance, thereby reducing energy loss and electromagnetic interference during signal transmission. Moreover, the contact area between the solder ball and the solder point is relatively large, which helps to conduct and dissipate heat.

[0028] As shown in Figure 1 , in specific implementation, the first solder point 21 is protruded on the lower surface of the adapter plate 2. In this way, the first solder point 21 is protruded on the lower surface of the adapter plate 2, which makes more efficient use of the space on the substrate 1, and helps to improve the integration and density of the package. Moreover, the protruded first solder point 21 facilitates the transfer of heat generated by the first chip to the substrate 1, improving heat dissipation efficiency.

[0029] As shown in Figure 1 , in specific implementation, the first chip 3 has a plurality of second metal contacts 32 on its front surface, and the adapter plate 2 has a second solder point 22 embedded in the top surface and connected to the second metal contacts 32. In this way, the second solder point 22 is embedded in the top of the adapter plate 2 and tightly connected to the second metal contacts 32, which helps to reduce contact resistance and improve the stability and reliability of electrical connection. At the same time, since the second solder point 22 is embedded in the adapter plate, it reduces the influence of the external environment on the electrical connection and does not increase the height of the upper surface of the adapter plate 2, which is beneficial to improve the integration of the packaging structure of the present application.

[0030] As shown in Figure 1 , a filling glue layer 6 is arranged in the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1. In this way, the filling glue layer 6 can firmly bond the adapter plate 2 and the substrate 1 after curing, enhancing the connection strength between them. On the other hand, the filling glue layer 6 can have good thermal conductivity to facilitate the transfer of heat generated by the chip to the substrate 1, further improving heat dissipation efficiency. Moreover, the filling glue layer 6 can fill the small gap between the adapter plate 2 and the substrate 1, reduce thermal resistance, and improve heat conduction efficiency.

[0031] As shown in Figure 1As shown, the upper surface of the substrate 1 is provided with a plastic encapsulation layer 7 for encapsulating all components into one body. In this way, all components are encapsulated into one body, so as to protect the internal components from insulation and moisture, etc. In a specific implementation, the plastic encapsulation layer 7 is usually made of epoxy resin material.

[0032] As described above, the present application protects a wire bonding encapsulation structure based on a 2nm or smaller chip, and all technical solutions identical or similar to the present application shall be shown to fall within the protection scope of the present application.

Claims

1. A wire bonding package structure based on 2nm and below chip, comprising a substrate (1), characterized in that The substrate (1) is connected with an adapter plate (2) on its upper surface, a first chip (3) with a thickness of 2nm or less is flip-chip mounted on the upper surface of the adapter plate (2), a plurality of first metal contacts (31) are arranged on the back surface of the first chip (3), a plurality of back surface power supply contacts (11) are formed in the substrate (1) according to the number of the first metal contacts (31), and the first metal contacts (31) and the back surface power supply contacts (11) are bonded together by a plurality of metal leads (4).

2. The package structure of claim 1, wherein The substrate (1) is formed with vertical interlayer vias (12) in the inside thereof, and a multilayer vertical intercommunication circuit layer structure (13) is arranged in the interlayer vias (12), and the uppermost layer of the circuit layer structure (13) serves as the back surface power supply contact (11).

3. The package structure of claim 2, wherein The lower surface of the substrate (1) is provided with a downward recessed opening (14) at the position of the circuit layer structure (13), and the lowermost layer of the circuit layer structure (13) is exposed through the opening (14).

4. The package structure of claim 2 or 3, wherein The substrate (1) is provided with a chip mounting area (110) and a die back power supply area (120) arranged in a ring shape around the chip mounting area (110), a plurality of first solder balls (5) are arranged on the upper surface of the chip mounting area (110), the circuit layer structure (13) is formed in the inside of the corresponding die back power supply area (120), and a plurality of first solder joints (21) corresponding to the first solder balls (5) are arranged on the lower surface of the adapter plate (2).

5. The package structure of claim 4, wherein, The first solder joint (21) is arranged on the lower surface of the adapter plate (2).

6. The package structure of claim 1, wherein The front surface of the first chip (3) is provided with a plurality of second metal contacts (32), and the upper surface of the adapter plate (2) is provided with second solder joints (22) embedded to the top and connected with the second metal contacts (32).

7. The package structure of claim 1, wherein A filling glue layer (6) is arranged in the gap between the lower surface of the adapter plate (2) and the upper surface of the substrate (1) to fill the gap.

8. The package structure of claim 1, wherein The upper surface of the substrate (1) is provided with a plastic packaging layer (7) for packaging all components into one body.

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