Metal band connection-based packaging structure for chips of 2nm and below
The packaging structure with metal strip connections solves the power supply and heat dissipation problems of chips with process technology of 2nm and below, realizes low resistance conductive network and efficient heat dissipation, simplifies manufacturing process, and improves chip integration and production efficiency.
Patent Information
- Application Number
- CN202422583563.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2034-10-24
AI Technical Summary
Traditional packaging technologies struggle to meet the power efficiency, thermal management, and physical size control requirements of chips manufactured at 2nm and below, especially under high power consumption and high heat conditions, where resistance control and heat dissipation become prominent issues.
The packaging structure, which uses metal strip connections, includes a substrate, an adapter board, and a flip-chip design. The vertical and horizontal extensions of the metal strips form a conductive network, which, combined with a conductive material layer, achieves low-resistance conductivity and efficient heat dissipation, and simplifies the manufacturing process.
It achieves smaller package height and higher integration, reduces resistance and power loss, improves power supply efficiency and heat dissipation, reduces the risk of loose connections, simplifies the manufacturing process, and reduces costs.
Smart Images
Figure CN223462222U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a chip packaging structure, concretely relates to a 2nm and below chip based on the packaging structure of metal band connection. BACKGROUND
[0002] With the rapid development of semiconductor technology, chip manufacturing process is constantly advancing to a more fine scale, especially in the 2nm and below process era, the integration and performance of chips have been unprecedentedly improved. However, this technological progress has also brought many challenges, especially in the field of chip packaging. The traditional packaging technology has been difficult to meet the stringent requirements of these high-end chips on power supply efficiency, thermal management and physical size control.
[0003] For 2nm and below process chips, their power density increases significantly, combined with the explosive growth of transistors inside the chip, making the resistance control of the power supply line a key. High resistance not only leads to energy waste, but also may cause voltage drop, affecting the stability and performance of the chip. At the same time, high power consumption also means more heat, how to effectively dissipate heat and prevent performance degradation or damage caused by overheating of the chip has become a problem to be solved.
[0004] Therefore, it is particularly important to develop a packaging structure that can realize low resistance, large current power supply and has high heat dissipation capacity. SUMMARY
[0005] The utility model overcomes the above technical insufficient, provides a 2nm and below chip based on the packaging structure of metal band connection.
[0006] To achieve the above object, the utility model adopts the following technical scheme:
[0007] A 2nm and below chip based on the packaging structure of metal band connection, including the substrate 1, the substrate 1 is connected with the adapter plate 2 on its upper surface, the first chip 3 of 2nm and below thickness is flip-chip mounted on the upper surface of the adapter plate 2, the first chip 3 back surface is equipped with a plurality of first metal contacts 31, the substrate 1 is formed with a plurality of back wafer power supply metal contacts 11 on its upper surface according to the number of first metal contacts 31, each first metal contact 31 surface is equipped with the first conductive material layer 41, each back wafer power supply metal contact 11 surface is equipped with the second conductive material layer 42, the first conductive material layer 41 and the second conductive material layer 42 are conductively connected together through the metal band 5 of one-piece forming;The metal band 5 includes the vertical extension structure 51 extending from the second conductive material layer 42 to the back surface of the first chip 3, the horizontal extension structure 52 extending from the top end of the vertical extension structure 51 to the first conductive material layer 41.
[0008] Preferably, the vertically extending structure 51 is L-shaped, which is divided into a first extending part 511 covering the second conductive material layer 42 directly and extending to the same level as the lower surface of the adapter plate 2, and a second extending part 512 extending upward from the side of the first extending part 511 close to the first chip 3 to the same level as the back surface of the first chip 3; the first extending part 511 is consistent with the area of the back surface power supply metal contact 11, and the width of the second extending part 512 is less than half of the width of the first extending part 511.
[0009] Preferably, the substrate 1 is provided with a chip mounting area 110 and a back surface power supply area 120 arranged in a ring shape around the chip mounting area 110, the substrate 1 is provided with a plurality of first solder balls 6 on the upper surface of the chip mounting area 110, and the metal strip 5 is connected to the metal strip 5 through the second conductive material layer 42 of the back surface power supply area 120; the lower surface of the adapter plate 2 is provided with a plurality of first solder joints 21 corresponding to the first solder balls 6.
[0010] Preferably, the first solder joint 21 is protruded on the lower surface of the adapter plate 2, and the back surface power supply metal contact 11 is formed on the back surface power supply area 120 and embedded into the top of the substrate 1.
[0011] Preferably, the front surface of the first chip 3 is provided with a plurality of second metal contacts 32, and the upper surface of the adapter plate 2 is provided with a second solder joint 22 embedded into the top and connected with the second metal contact 32.
[0012] Preferably, the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 is provided with a filling glue layer 7 for filling the gap, and the upper surface of the substrate 1 is provided with a plastic sealing layer 8 for packaging all components into one body.
[0013] Preferably, the metal strip 5 is a copper strip.
[0014] Preferably, the first conductive material layer 41 and the second conductive material layer 42 are tin paste layers or conductive glue layers.
[0015] Preferably, the second metal contact 32 and the second solder joint 22 are directly bonded and interconnected in a point-to-point manner.
[0016] Preferably, the substrate 1 is an FCBGA packaging substrate.
[0017] Compared with the prior art, the utility model has the advantages that:
[0018] 1、The application achieves high integration between the chip and the substrate by setting the adapter plate on the substrate and flip-chip the first chip with a thickness of 2nm or less. This can achieve a smaller packaging height and a smaller physical size. At the same time, due to the small thickness of the first chip, the adapter plate can play a certain role in raising the height to facilitate the subsequent connection of the first metal contact on the back of the first chip through the metal strip. Since the first chip is extremely thin, the application forms a conductive network for back-of-chip power supply through the vertical extension structure and the horizontal extension structure of the first conductive material layer, the back-of-chip power supply metal contact and the metal strip, effectively improving the heat conduction and dissipation capacity. Moreover, the vertical metal block / horizontal metal block not only serves as a conductive channel, but also as a heat conduction path, in cooperation with the first conductive material layer and the second conductive material layer and the third conductive material layer, ensuring low resistance and high conductivity of the entire conductive path, which helps to reduce the loss in the process of electric energy transmission and improve energy utilization efficiency. In addition, the first chip is connected to the adapter plate in a flip-chip manner, with the back of the first chip facing up, which can realize back-of-chip power supply in cooperation with the above-mentioned conductive network. Compared with traditional chips, on the one hand, back-of-chip power supply can shorten the power supply path, reduce resistance and improve power supply efficiency. In addition, the use of an integrally formed metal strip design can directly connect the first metal contact and the back-of-chip power supply metal contact during production, without the need for complex stacking processes, reducing the welding and connection steps and the number of components in the assembly process, making the structure relatively simple and easier to manufacture and integrate, thereby improving production efficiency.
[0019] 2、The vertical extension structure of the metal strip is designed in an L shape, which can form a zigzag structure in cooperation with the extension structure, helping to reduce the risk of connection loosening or breaking caused by factors such as vibration or temperature change, making the connection more stable. The first extension part of the vertical extension structure is consistent in size with the back-of-chip power supply metal contact, so as to be able to realize full coverage of the back-of-chip power supply metal contact on the back-of-chip power supply metal contact, ensuring good contact area and conductivity. The second extension part is designed to have a width less than one-half of the first extension part, so as to be able to save metal strip material while ensuring reliable conductive connection with the first conductive material layer, which is beneficial to cost savings and can reduce the weight after packaging. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 is a cross-sectional structure schematic diagram of the application.
[0021] Figure 2 is a top view structure schematic diagram of the application without a plastic encapsulation layer and a metal strip.
[0022] Figure 3 is a top view structure schematic diagram of the application without a plastic encapsulation layer. DETAILED DESCRIPTION
[0023] The features of the present application and other related features are further described in detail by the following examples, so as to facilitate the understanding of the skilled in the art:
[0024] As shown in Figure 1 and Figure 3 , a packaging structure based on metal strip connection for 2nm and below chips includes a substrate 1, an adapter plate 2 is connected to the upper surface of the substrate 1, a first chip 3 with a thickness of 2nm and below is flip-chip mounted on the upper surface of the adapter plate 2, a plurality of first metal contacts 31 are provided on the back surface of the first chip 3, a plurality of back-of-die power supply metal contacts 11 are formed on the upper surface of the substrate 1 corresponding to the number of first metal contacts 31, a first conductive material layer 41 is provided on the surface of each first metal contact 31, a second conductive material layer 42 is provided on the surface of each back-of-die power supply metal contact 11, and the first conductive material layer 41 and the second conductive material layer 42 are conductively connected together by an integrally formed metal strip 5; the metal strip 5 includes a vertical extension structure 51 extending from the second conductive material layer 42 to the same height as the back surface of the first chip 3, and a horizontal extension structure 52 extending from the top end of the vertical extension structure 51 to the first conductive material layer 41.
[0025] As described above, by providing an adapter plate 2 on the substrate 1 and flip-chip mounting a first chip 3 with a thickness of 2nm and below thereon, the present application achieves high integration between the chip and the substrate, and can achieve smaller packaging height and smaller physical size. At the same time, due to the small thickness of the first chip 3, the adapter plate can play a certain height-raising role, so as to facilitate the subsequent connection of the first metal contacts to the back surface of the first chip 3 through the metal strip 5. Since the first chip is extremely thin, the present application forms a conductive network for back-of-die power supply by the first conductive material layer, the back-of-die power supply metal contacts 11, the vertical extension structure 51 and the horizontal extension structure 52 of the metal strip 5, effectively improving the heat conduction and dissipation capacity. Moreover, the vertical metal block / horizontal metal block not only serves as a conductive channel, but also serves as a heat conduction path, and cooperates with the first conductive material layer 41 and the second conductive material layer 42 and the third conductive material layer 43 to ensure low resistance and high conductivity of the entire conductive path, which helps to reduce the loss in the process of electric energy transmission and improve the energy utilization efficiency. In addition, the first chip 3 is connected to the adapter plate in a flip-chip manner, so that the back surface of the first chip 3 faces upward, and the back-of-die power supply can be realized by cooperating with the above-mentioned conductive network, compared with the traditional chip, on the one hand, the back-of-die power supply can shorten the power supply path, reduce the resistance, and improve the power supply efficiency. In addition, the design of the integrally formed metal strip can directly connect the first metal contacts and the back-of-die power supply metal contacts during production, without the need for complex stacking process, reducing the welding and connection steps and the number of components in the assembly process, making the structure relatively simple and easier to manufacture and integrate, thereby improving the production efficiency.
[0026] AsFigure 1 As shown, the vertical extension structure 51 is in L shape, which is divided into a first extension part 511 covering the second conductive material layer 42 directly above and extending to the same level as the lower surface of the adapter plate 2, and a second extension part 512 extending upward from the side of the first extension part 511 close to the first chip 3 to the same level as the back surface of the first chip 3; the first extension part 511 is consistent in size with the area of the back surface power supply metal contact 11, and the width of the second extension part 512 is less than half the width of the first extension part 511; in specific implementation, the second extension part 512 only extends upward from one side of the top end, and the second extension part 512 is only 1 / 3 to 1 / 5 of the width of the first extension part 511.
[0027] As described above, the vertical extension structure 51 of the metal strip is designed in L shape, which can cooperate with the extension structure 52 to form a z-shaped structure, which helps to reduce the risk of loose or broken connection caused by factors such as vibration or temperature change, so that the connection is more stable. The first extension part 511 of the vertical extension structure 51 is consistent in size with the area of the back surface power supply metal contact 11, so as to be able to realize the full coverage of the back surface power supply metal contact 11 on the back surface power supply metal contact 11, and ensure good contact area and conductivity. The width of the second extension part 512 is less than half the width of the first extension part 511, so as to be able to save the material of the metal strip while meeting the reliable conductive connection with the first conductive material layer 41, which is conducive to saving cost, and can also reduce the weight after packaging.
[0028] As Figure 2 shown, in specific implementation, the substrate 1 is provided with a chip mounting area 110 and a back surface power supply area 120 arranged in a ring around the chip mounting area 110, the substrate 1 is provided with a plurality of first solder balls 6 on the upper surface of the chip mounting area 110, and the vertical metal block 5 is connected with the second conductive material layer 42 on the back surface power supply area 120, and the adapter plate 2 is provided with a plurality of first solder joints 21 corresponding to the first solder balls 6 on the lower surface. Each back surface power supply area 120 is provided with a plurality of back surface power supply metal contacts 11.
[0029] As described above, the substrate divides the chip mounting area 110 and the back side power supply area 120, which can reasonably layout the packaging structure and facilitate subsequent packaging. The back side power supply area 120 is arranged in a ring around the chip mounting area 110. Such a ring-shaped power supply structure can more effectively provide power support for the chip, reduce the resistance and inductance in the power transmission path, thereby reducing the voltage drop and electromagnetic interference, and improving the stability and efficiency of power supply. In addition, the ring arrangement allows the conductive network composed of vertical metal blocks and horizontal metal blocks to form a natural heat dissipation channel, which helps to quickly conduct the heat generated by the chip. The direct connection between the first solder ball 6 and the first solder joint 21 provides a short and direct current path, which helps to reduce inductance and resistance, thereby reducing energy loss and electromagnetic interference during signal transmission. Moreover, the contact area between the solder ball and the solder joint is relatively large, which helps to conduct and dissipate heat.
[0030] As shown in Figure 1 , in specific implementation, the first solder joint 21 is protruded on the lower surface of the adapter plate 2, and the back side power supply metal contact 11 is formed on the back side power supply area 120 and embedded in the top of the substrate 1. In this way, the first solder joint 21 is protruded on the lower surface of the adapter plate 2, which makes more efficient use of the space on the substrate 1, and helps to improve the integration and density of the package. Moreover, the protruded first solder joint 21 facilitates the transfer of heat generated by the first chip to the substrate 1, improving heat dissipation efficiency. The back side power supply metal contact 11 is embedded in the top of the substrate 1 without protruding on the top surface of the substrate, which allows the top surface of the substrate to be more compactly arranged with conductive material layers and metal blocks, thereby further improving the integration and density of the entire package. Moreover, the embedded contact design makes the top surface of the substrate more flat, which is conducive to the installation of heat dissipation elements such as heat sinks or heat pipes, improving the heat dissipation efficiency of the package.
[0031] As shown in Figure 1 , in specific implementation, the first chip 3 is provided with a plurality of second metal contacts 32 on the front surface, and the adapter plate 2 is provided with a second solder joint 22 embedded in the top surface and connected with the second metal contacts 32.
[0032] As described above, the second solder joint 22 is embedded in the top of the adapter plate 2 and tightly connected with the second metal contact 32, which helps to reduce contact resistance and improve the stability and reliability of electrical connection. At the same time, since the second solder joint 22 is embedded in the adapter plate, on the one hand, it reduces the influence of the external environment on the electrical connection, and on the other hand, it does not increase the height of the upper surface of the adapter plate 2, which is conducive to improving the integration of the packaging structure of the present application.
[0033] As shown in Figure 1As shown, the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 is filled with a filling adhesive layer 7. In this way, on the one hand, the filling adhesive layer 7 can firmly bond the adapter plate 2 and the substrate 1 after curing, thereby enhancing the connection strength between them; on the other hand, the filling adhesive layer 7 can have good thermal conductivity to facilitate the transfer of heat generated by the chip to the substrate 1, thereby further improving the heat dissipation efficiency. Moreover, the filling adhesive layer 7 can fill the small gap between the adapter plate 2 and the substrate 1, thereby reducing the thermal resistance and improving the thermal conductivity efficiency.
[0034] As shown, the upper surface of the substrate 1 is provided with a plastic encapsulation layer 8 for encapsulating all components into one body. In this way, all components are encapsulated into one body, thereby facilitating insulation protection and moisture-proofing of the internal components. In specific implementation, the plastic encapsulation layer 8 is usually made of epoxy resin material. Figure 1
[0035] As a preferred embodiment, the metal strip 5 is a copper strip. In this way, the copper strip as the metal strip 5 has excellent electrical conductivity, thermal conductivity, good ductility and is easier to process in the packaging structure.
[0036] As a preferred embodiment, the first conductive material layer 41 and the second conductive material layer 42 are tin paste layers or conductive adhesive layers. In this way, the tin paste layer or the conductive adhesive layer is selected as the first conductive material layer 41 and the second conductive material layer 42 to meet the electrical conductivity and heat dissipation requirements, and the tin paste layer and the conductive adhesive layer are both commonly used conductive materials in the packaging process, thereby reducing the complexity and cost of the packaging process.
[0037] As a preferred embodiment, the second metal contact 32 and the second solder point 22 are directly bonded and interconnected in a point-to-point manner, i.e., connected together in a Hybrid Bonding manner. In this way, the first chip and the adapter plate are precisely aligned and directly pressed together to form direct electrical contact, thereby eliminating the need for traditional intermediate materials such as solder.
[0038] As a preferred embodiment, the substrate 1 is an FCBGA packaging substrate. In this way, the adoption of the FCBGA packaging substrate can realize flip-chip technology, i.e., the chip is inverted and attached to the substrate, thereby facilitating the subsequent supply of power to the back of the chip of 2nm and below, eliminating the need for wires to connect the chip and the substrate, and thereby achieving higher integration and higher density packaging.
[0039] As mentioned above, the present case protects a packaging structure based on metal strip connection for 2nm and below chips, and all technical solutions identical or similar to the present case shall be deemed to fall within the protection scope of the present case.
Claims
1. A 2nm and below chip package structure based on metal ribbon connection, comprising a substrate (1), characterized in that The substrate (1) is connected with an adapter plate (2) on its upper surface, a first chip (3) with a thickness of 2nm or below is flip-chip mounted on the upper surface of the adapter plate (2), a plurality of first metal contacts (31) are arranged on the back surface of the first chip (3), a plurality of back surface power supply metal contacts (11) are correspondingly formed on the upper surface of the substrate (1) according to the number of the first metal contacts (31), a first conductive material layer (41) is arranged on the surface of each first metal contact (31), a second conductive material layer (42) is arranged on the surface of each back surface power supply metal contact (11), and the first conductive material layer (41) and the second conductive material layer (42) are conductively connected together through an integrally formed metal strip (5); the metal strip (5) comprises a vertical extension structure (51) extending from the second conductive material layer (42) to the same height as the back surface of the first chip (3), and a horizontal extension structure (52) extending from the top end of the vertical extension structure (51) to the first conductive material layer (41).
2. The package structure of claim 1, wherein The vertical extension structure (51) is in an L shape, which is divided into a first extension part (511) covering directly above the second conductive material layer (42) and extending to the same height as the lower surface of the adapter plate (2), and a second extension part (512) extending upward from one side of the first extension part (511) close to the first chip (3) to the same height as the back surface of the first chip (3); the first extension part (511) is consistent with the area size of the back surface power supply metal contact (11), and the width of the second extension part (512) is less than half of the width of the first extension part (511).
3. The package structure of claim 1, wherein The substrate (1) is provided with a chip mounting area (110) and a back surface power supply area (120) arranged in a ring shape around the chip mounting area (110), a plurality of first solder balls (6) are protrudingly arranged on the upper surface of the substrate (1) in the chip mounting area (110), and the metal strip (5) is connected to the second conductive material layer (42) in the back surface power supply area (120); the lower surface of the adapter plate (2) is provided with a plurality of first solder joints (21) correspondingly connected to the first solder balls (6).
4. The package structure of claim 3, wherein, The first solder joint (21) is protrudingly arranged on the lower surface of the adapter plate (2), and the back surface power supply metal contact (11) is formed in the back surface power supply area (120) and embedded into the top of the substrate (1).
5. The package structure of claim 3, wherein The front surface of the first chip (3) is provided with a plurality of second metal contacts (32), and the upper surface of the adapter plate (2) is provided with second solder joints (22) embedded into the top and connected to the second metal contacts (32) in a fit-together manner.
6. The package structure of any one of claims 1-5, wherein A filling adhesive layer (7) is arranged in the gap between the lower surface of the adapter plate (2) and the upper surface of the substrate (1) to fill the gap, and a plastic packaging layer (8) is arranged on the upper surface of the substrate (1) to package all components into one body.
7. The package structure of claim 1, wherein The metal strip (5) is a copper strip.
8. The package structure of claim 1, wherein The first conductive material layer (41) and the second conductive material layer (42) are tin paste layers or conductive adhesive layers.
9. The package structure of claim 5, wherein The second metal contact (32) and the second solder joint (22) are directly bonded and interconnected together in a point-to-point manner.
10. The package structure of claim 1, wherein The substrate (1) is an FCBGA packaging substrate.