Semiconductor structure, vertical semiconductor device and horizontal semiconductor device

Abstract

The utility model discloses a semiconductor structure, a vertical semiconductor device and a horizontal semiconductor device, and belongs to the technical field of semiconductors. The semiconductor structure at least comprises a substrate; the first buffer layer is arranged on the substrate; the second buffer layer is arranged on the first buffer layer; the porous stress release layer is arranged on the second buffer layer; the first semiconductor layer is arranged on the porous stress release layer, and the first semiconductor layer is free of stress; and the second semiconductor layer is arranged on the first semiconductor layer, and the second semiconductor layer is free of stress. According to the semiconductor structure, the vertical semiconductor device and the horizontal semiconductor device provided by the utility model, the performance of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of semiconductor technology, especially relates to a semiconductor structure, vertical semiconductor device and horizontal semiconductor device. BACKGROUND

[0002] The third generation semiconductor material has very good application prospect and market potential value in solid state light source and power electronics, microwave radio frequency device and other fields due to the superior performance of large band gap, high breakdown field, large thermal conductivity, high electron saturation drift rate and strong anti-radiation capability. However, the current also has the defects of low reverse breakdown voltage and large reverse leakage current, and high cost, complex process and long cycle. UTILITY MODEL CONTENTS

[0003] The utility model discloses a semiconductor structure, vertical semiconductor device and horizontal semiconductor device can effectively alleviate the thermal stress in the interlayer structure of semiconductor structure, improve the performance of the device of application semiconductor structure.

[0004] To solve the above technical problems, the utility model is realized through the following technical schemes:

[0005] The utility model provides a semiconductor structure at least includes:

[0006] Substrate;

[0007] First buffer layer is arranged on the substrate;

[0008] Second buffer layer is arranged on the first buffer layer;

[0009] Porous stress release layer is arranged on the second buffer layer;

[0010] First semiconductor layer is arranged on the porous stress release layer, and the first semiconductor layer is stress-free;And

[0011] Second semiconductor layer is arranged on the first semiconductor layer, and the second semiconductor layer is stress-free.

[0012] In an embodiment of the utility model, the pore size of the porous stress release layer is 20nm-100nm, and the thickness of the porous stress release layer is 200nm-500nm.

[0013] In an embodiment of the utility model, the first semiconductor layer at least contains doped gallium nitride layer.

[0014] In an embodiment of the present application, the second semiconductor layer at least comprises a doped gallium nitride layer, and the doping concentration of the second semiconductor layer is less than the doping concentration of the first semiconductor layer.

[0015] In an embodiment of the present application, the first semiconductor layer at least comprises an undoped gallium nitride layer.

[0016] In an embodiment of the present application, the second semiconductor layer at least comprises an undoped aluminum gallium nitride layer.

[0017] In an embodiment of the present application, the semiconductor structure further comprises a third semiconductor layer, and the third semiconductor layer is arranged on the second semiconductor layer.

[0018] In an embodiment of the present application, the third semiconductor layer at least comprises a gallium nitride layer or a stacked structure of a gallium nitride layer and an aluminum gallium nitride layer.

[0019] The present application provides a vertical semiconductor device, which comprises the semiconductor structure.

[0020] The present application provides a horizontal semiconductor device, which comprises the semiconductor structure.

[0021] In summary, the semiconductor structure, the vertical semiconductor device and the horizontal semiconductor device provided by the present application can form a first buffer layer on a sapphire substrate, reduce the material defect density in a high-voltage semiconductor device, relieve the lattice mismatch problem between different semiconductor layers, avoid device failure caused by device breakdown and leakage under high voltage, and realize low-cost, low-stress and high-uniformity device materials, achieve conventional voltage performance, and reduce the growth cost of materials. Meanwhile, a porous stress release layer is formed on the second buffer layer, effectively relieving the thermal stress of the gallium nitride layer during growth, solving the reliability problem of existing gallium nitride material devices, and realizing a high-quality and high-voltage semiconductor structure.

[0022] Of course, implementing any product of the present application does not necessarily need to achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0024] Figure 1 It is a schematic view of forming the first buffer layer and the second buffer layer on the substrate in an embodiment.

[0025] Figure 2 A schematic view of forming a porous stress release layer in an embodiment.

[0026] Figure 3 A schematic view of forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in an embodiment.

[0027] Figure 4 A schematic view of forming an anode electrode and a cathode electrode in an embodiment.

[0028] Figure 5 A schematic view of peeling off a substrate, a first buffer layer and a second buffer layer in an embodiment.

[0029] Figure 6 A schematic view of forming a first semiconductor layer and a second semiconductor layer in another embodiment.

[0030] Figure 7 A schematic view of forming a Schottky electrode in another embodiment.

[0031] Figure 8 A schematic view of peeling off a substrate, a first buffer layer and a second buffer layer in another embodiment.

[0032] Figure 9 A schematic view of forming an ohmic electrode in another embodiment.

[0033] Label explanation:

[0034] 10, substrate; 21, first buffer layer; 22, second buffer layer; 30, porous stress release layer; 40, first semiconductor layer; 50, second semiconductor layer; 60, third semiconductor layer; 71, anode electrode; 72, cathode electrode; 80, Schottky electrode; 90, ohmic electrode. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work, belong to the protection scope of the present application.

[0036] Please refer to Figure 1 and Figure 2As shown in the embodiment of the present application, the semiconductor structure is, for example, a laminated structure, for example, sequentially comprising a substrate 10, a first buffer layer 21, a second buffer layer 22 and a porous stress release layer 30, etc., to form a horizontal gallium nitride semiconductor structure, i.e., a semiconductor structure based on aluminum gallium nitride / gallium nitride heterojunction, or a vertical gallium nitride semiconductor structure, i.e., a semiconductor structure based on metal-gallium nitride. The material defect density in the device is effectively alleviated, the thermal stress of the nitride layer growth device is alleviated, the performance of the semiconductor device is improved, the manufacturing method is simple, the process cost is low, and the method can also be used for the preparation of other semiconductor structures.

[0037] Referring to Figure 1 As shown in the embodiment of the present application, first, a substrate 10 is provided, and the substrate 10 can be any material suitable for forming a semiconductor structure, for example, one of an insulator substrate, a semiconductor substrate, a metal substrate or a conductive substrate, and the specific material is, for example, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer or other III / V compound semiconductor material, etc., and also includes a laminated structure composed of these semiconductor materials, or silicon on insulator, silicon on insulator, germanium on insulator, etc., and the present application does not limit the material and thickness of the substrate 10. In the embodiment, the substrate 10 is, for example, a sapphire substrate 10, which has, for example, a corundum structure, and improves the heat dissipation, conduction loss, high temperature or high frequency characteristics of the device. The present application does not limit the size and thickness of the substrate 10, and the specific size is determined according to the type and size of the semiconductor device produced.

[0038] Referring to Figure 1In the embodiment of the present application, the first buffer layer 21 is arranged on the substrate 10 to slow down the lattice mismatch between the first semiconductor layer 40 and the substrate 10, and further to cause the defects of dislocation, stacking fault or cavity. In the embodiment, the first buffer layer 21 is, for example, an aluminum nitride layer, and in other embodiments, the first buffer layer 21 is, for example, other materials used for forming gallium nitride devices, and is, for example, gallium nitride or yttrium oxide. The present application does not limit the method for forming the first buffer layer 21, and the method for forming the first buffer layer 21 is, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD) or flame spraying. In the embodiment, the physical vapor deposition is selected, and is, for example, one of ion beam deposition, magnetron sputtering or reactive magnetron sputtering. Specifically, the sapphire substrate 10 is placed in a PVD reaction chamber, nitrogen and argon with a ratio of, for example, 1:8 are introduced into the reaction chamber, the temperature of the substrate 10 is, for example, 550-650 DEG C, and sputtering is performed to obtain an aluminum nitride layer with a thickness of, for example, 20-40 nm. The present application does not limit the annealing process, and is, for example, one of high-temperature annealing process, rapid thermal annealing or spike annealing process. Specifically, the conditions are, for example, that the annealing temperature is, for example, 1600-1700 DEG C, and the annealing gas is, for example, nitrogen. By arranging the aluminum nitride layer on the substrate 10, the lattice defects of the substrate 10 are eliminated, the influence of the piezoelectric effect on the substrate 10 is reduced, and the subsequent formation of the multi-layer semiconductor layer on the first buffer layer 21 is realized, so that the device material with low cost, low stress and high uniformity is realized, the conventional voltage performance is achieved, and the growth cost of the material is reduced.

[0039] Please refer to Figure 1As shown, in an embodiment of the present application, the first buffer layer 21 is provided with a second buffer layer 22, for example, a gallium nitride layer, which can relieve the lattice mismatch between the subsequently deposited semiconductor layer and the substrate 10, and further cause the defects of dislocation, stacking fault or void. The present application does not limit the deposition method of the second buffer layer 22, for example, the second buffer layer 22 is formed by a thin film deposition technique, for example, chemical vapor deposition, hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) or a combination of several methods, wherein the chemical vapor deposition includes metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) and atomic layer chemical vapor deposition (ALCVD). In the embodiment, for example, the physical vapor deposition method is selected to form the second buffer layer 22, and the thickness of the second buffer layer 22 is for example 20nm-2000nm. Specifically, under the conditions that the temperature is for example 500-850℃, for example 500-550℃, the reaction cavity pressure is for example 100Torr-650Torr, for example 200Torr-500Torr, ammonia and trimethyl gallium (TMGa) are introduced into the reaction cavity, and then a layer of gallium nitride layer with a thickness of for example 20nm-2000nm is grown on the first buffer layer 21 to form the second buffer layer 22.

[0040] Please refer to Figures 1 to 2In the embodiment of the utility model, the second buffer layer 22 is provided with a porous stress release layer 30, and the material of the porous stress release layer 30 includes gallium nitride material at least. The porous stress release layer 30 is formed to effectively release the thermal stress of the first semiconductor layer 40 and the second semiconductor layer 50 formed subsequently, and improve the performance of the semiconductor device. In the embodiment, the material of the porous stress release layer 30 is gallium nitride material, the pore size of the porous stress release layer 30 is 20nm-100nm, the thickness of the porous stress release layer 30 is 200nm-1500nm, for example, 200nm-500nm, and the porous stress release layer 30 with different pore size and thickness has different release effects on the thermal stress of the first semiconductor layer 40 and the second semiconductor layer 50, and according to the thickness and doping concentration of the first semiconductor layer 40 and the second semiconductor layer 50, the pore size and thickness of the porous stress release layer 30 are deduced to achieve the effect of no stress in the first semiconductor layer 40 and the second semiconductor layer 50. The utility model does not limit the specific forming method of the porous stress release layer 30, and in the embodiment, for example, one of the epitaxial layer forming methods such as chemical vapor deposition method or physical vapor deposition method is selected to deposit a gallium nitride layer on the second buffer layer 22. After the gallium nitride layer is formed, impurity ions are injected into the gallium nitride layer, and in the embodiment, the injected impurity ions are N-type impurity ions, for example, silicon (Si), phosphorus (P) or arsenic (As) impurity ions, an N-type doped gallium nitride layer is formed, and the doping concentration is set according to specific production requirements, so as to subsequently strip the substrate 10, the first buffer layer 21 and the second buffer layer 22. After the N-type doped gallium nitride layer is formed, the N-type doped gallium nitride layer is etched to obtain the porous stress release layer 30, and the formation of the pores is obtained by selecting physical etching, chemical etching or a combination of the two etching methods. In the embodiment, for example, chemical etching is selected, for example, the N-type doped gallium nitride layer is soaked in a chemical reagent to obtain the porous stress release layer 30. The chemical reagent is selected as oxalic acid solution, the concentration of the chemical reagent is 2mol / L-3mol / L, and the etching time is 1-2 hours. Specifically, for example, the pore size and thickness of the porous stress release layer 30 are controlled by adjusting the etching conditions such as the doping concentration of the porous stress release layer 30, the concentration of the chemical reagent or the etching time, and the subsequent semiconductor layer is matched, so as to effectively release the thermal stress of the semiconductor layer and improve the quality of the epitaxial layer. After the porous stress release layer 30 is formed, the porous stress release layer 30 is used as a growth substrate for the growth of the subsequent functional layer such as the first semiconductor layer 40, and the subsequent vertical semiconductor device or horizontal semiconductor device is formed.

[0041] Please refer to Figures 2 to 3The utility model discloses still provide a horizontal type semiconductor device, horizontal type semiconductor device at least includes porous stress release layer 30, still be provided with first semiconductor layer 40 on porous stress release layer 30. First semiconductor layer 40 is for example non-doped gallium nitride thick layer, through obtaining high resistance first semiconductor layer 40, can improve the withstand voltage of device, thereby improve the quality of semiconductor device. The utility model does not limit the forming method of first semiconductor layer 40, specifically in this embodiment, can be under the condition that temperature is for example 1000 ℃ ~ 1200 ℃, again for example 1000 ℃ ~ 1050 ℃, reaction cavity pressure is for example 100Torr ~ 500Torr, again for example 400Torr ~ 500Torr, ammonia gas and trimethyl gallium (TMGa) are imported into the reaction cavity, and then grow a non-doped gallium nitride thick layer of thickness for example 1000nm ~ 3000nm on porous stress release layer 30, form first semiconductor layer 40. By forming porous stress release layer 30, reduce the stress of first semiconductor layer 40, form non-doped gallium nitride thick layer of no stress or low stress, can overcome the restriction of stress to N-doped concentration and thickness in the subsequent formation of second semiconductor layer 50, greatly reduce the parasitic resistance of second semiconductor layer 50, finally improve the cutoff frequency, power and efficiency of semiconductor device etc.

[0042] Please refer to Figure 3 As shown in the utility model one embodiment, in horizontal type semiconductor device, first semiconductor layer 40 is provided with second semiconductor layer 50. Second semiconductor layer 50 is for example non-doped aluminum gallium nitride layer, to be used as channel layer, and the thickness of second semiconductor layer 50 is for example 20nm ~ 60nm. The utility model does not limit the specific forming method of second semiconductor layer 50, for example selects metal organic compound chemical vapor deposition method to form. Specifically, under the condition that temperature is for example 500 ℃ ~ 900 ℃, again for example 600 ℃ ~ 700 ℃, reaction cavity pressure is for example 100Torr ~ 650Torr, again for example 200 ~ 500Torr, triethyl gallium (TEGa), trimethyl aluminum (TMAL) and ammonia gas (NH3) are imported into the reaction cavity, and then grow a gallium nitride of thickness for example 20nm ~ 40nm or 40nm ~ 60nm on substrate 10, form second semiconductor layer 50. Meanwhile, porous stress release layer 30 releases the thermal stress in second semiconductor layer 50, so that the stress of second semiconductor layer 50 is zero, further improve the performance of semiconductor device.

[0043] Please refer to Figure 3In an embodiment of the present application, a third semiconductor layer 60 is further provided on the second semiconductor layer 50 in the horizontal semiconductor device. The third semiconductor layer 60 is, for example, a non-doped gallium nitride layer, which is used as a barrier layer, and the thickness of the third semiconductor layer 60 is, for example, 600nm-1200nm. The present application does not limit the specific forming method of the third semiconductor layer 60, for example, the same forming method as the second buffer layer 22 is selected. Specifically, under the conditions that the temperature is, for example, 1000-1200℃, and for example, 1050-1200℃, and the reaction cavity pressure is, for example, 100-500Torr, and for example, 200-500Torr, ammonia and trimethyl gallium (TMGa) are introduced into the reaction cavity, and then a gallium nitride layer with a thickness of, for example, 600nm-3000nm or 1000nm-2500nm is grown on the substrate 10 to form the third semiconductor layer 60. By forming the second semiconductor layer 50 and the third semiconductor layer 60, the gallium nitride layer and the aluminum gallium nitride layer have strong spontaneous and piezoelectric polarization effects, so that the formed semiconductor device has good vertical leakage and breakdown characteristics. In other embodiments of the present application, the third semiconductor layer 60 can also be a stacked structure of a gallium nitride layer and an aluminum gallium nitride layer.

[0044] Please refer to Figures 3 to 4 In an embodiment of the present application, an anode electrode 71 and a cathode electrode 72 are provided on the third semiconductor layer 60 in the horizontal semiconductor device. The present application does not limit the forming method of the anode electrode 71 and the cathode electrode 72. In the present embodiment, an oxide layer (not shown in the figure) is formed on the third semiconductor layer 60 after the third semiconductor layer 60, which is used to protect the second semiconductor layer 50 and the third semiconductor layer 60, and at the same time, reduce the leakage caused by the lattice damage of the third semiconductor layer 60. The oxide layers on both sides of the third semiconductor layer 60 are etched until the third semiconductor layer 60 is exposed to form a contact hole (not shown in the figure). Then, a metal material is deposited in the contact hole, and the anode electrode 71 and the cathode electrode 72 are formed on the side of the third semiconductor layer 60 away from the second semiconductor layer 60, thereby forming a horizontal semiconductor device. By providing the porous stress release layer 30, the first semiconductor layer 40, the second semiconductor layer 50 and the third semiconductor layer 60 are formed on the porous stress release layer 30, and the porous stress release layer 30 effectively releases the thermal stress in the first semiconductor layer 40, the second semiconductor layer 50 and the third semiconductor layer 60, thereby significantly reducing the leakage current, increasing the breakdown voltage, and obtaining a horizontal semiconductor structure with high high-voltage resistance.

[0045] Please refer to Figures 4 to 5As shown, in one embodiment of the present invention, in the process of forming a horizontal semiconductor device, after forming the anode electrode 71 and the cathode electrode 72, the substrate 10, the first buffer layer 21 and the second buffer layer 22 are peeled off. The peeling method of the substrate 10, the first buffer layer 21 and the second buffer layer 22 is, for example, selected from chemical peeling, laser peeling or wet etching. In this embodiment, for example, laser peeling is selected. Specifically, the semiconductor structure including the substrate 10, the first buffer layer 21, the second buffer layer 22 and the porous stress release layer 30 is set in a laser emission chamber. The laser beam irradiates the interface between the second buffer layer 22 and the porous stress release layer 30. The interface absorbs the strong energy of the laser beam and instantly generates a temperature of 900°C or higher, causing the N-doped porous stress release layer 30 at the interface to be decomposed by the laser irradiation, so that the porous stress release layer 30 is separated from the second buffer layer 22. The N content in the porous stress release layer 30 is adjusted so that the impact force generated when the porous stress release layer 30 is decomposed is less than or equal to the maximum impact force that the porous stress release layer 30 can withstand, thereby preventing the porous stress release layer 30 from rupturing. In other embodiments, for example, other methods are selected to separate the porous stress release layer 30 from the second buffer layer 22.

[0046] See also Figure 2 and Figure 6 As shown, the present invention further provides a vertical semiconductor device comprising at least a porous stress relief layer 30, on which a first semiconductor layer 40 is disposed. In this embodiment, the first semiconductor layer 40 is, for example, an N-type gallium nitride layer, and the dopant ions in the first semiconductor layer 40 are, for example, germanium or silicon. The present invention is not limited to the method for forming the first semiconductor layer 40, which may be any film deposition method. In this embodiment, physical vapor deposition is selected, for example. Specifically, ammonia, trimethyl gallium (TMGa), and silane (SiH4) can be introduced into the reaction chamber at a temperature of, for example, 1000° C. to 1200° C., or 1050° C. to 1200° C., and a pressure of, for example, 100 Torr to 600 Torr, or 200 Torr to 500 Torr, to grow an N-type gallium nitride layer with a thickness of, for example, 100 nm to 3000 nm, or 500 nm to 2000 nm, on the porous stress relief layer 30. The ion concentration of silicon ions in the first semiconductor layer 40 is, for example, 1×10 18 atoms / cm 3 ~6×10 20 atom / cm 3 , for example 8×10 18 atoms / cm 3 ~5×10 20 atoms / cm 3 .

[0047] See also Figures 6 to 7 As shown, in another embodiment of the present invention, in a vertical semiconductor device, a second semiconductor layer 50 is provided on the first semiconductor layer 40. The second semiconductor layer 50 is, for example, an N-type gallium nitride layer. The doping ions in the second semiconductor layer 50 are, for example, of the same type as the doping ions in the first semiconductor layer 40, and the concentration of N doping in the second semiconductor layer 50 is, for example, less than the concentration of N doping in the first semiconductor layer 40. The present invention does not limit the method for forming the second semiconductor layer 50. For example, the method for forming the second semiconductor layer 50 is the same as the method for forming the first semiconductor layer 40, and the second semiconductor layer 50 with a set N doping concentration is obtained by adjusting reaction conditions such as the concentration of ammonia gas introduced, the reaction temperature, and the reaction pressure. In this embodiment, the ion concentration of silicon ions in the second semiconductor layer 50 is, for example, 1×10 16 atoms / cm 3 ~7×10 18 atoms / cm 3 , for example 8×10 16 atoms / cm 3 ~8×10 17 atoms / cm 3 The thickness of the second semiconductor layer 50 is, for example, 100 nm to 3000 nm, or 500 nm to 2000 nm. By forming the second semiconductor layer 50 with a lower doping concentration, the mismatch and dislocation density between the first semiconductor layer 40 and the second semiconductor layer 50 are reduced, resulting in a semiconductor device with a high critical breakdown electric field and a high Baliga figure of merit.

[0048] See also Figures 7 to 8 As shown, in another embodiment of the present invention, in a vertical semiconductor device, a Schottky electrode 80 is provided on the second semiconductor layer 50. In this embodiment, the material of the Schottky electrode 80 is, for example, nickel nitride, obtained, for example, by plasma-enhanced chemical vapor deposition. Specifically, ammonia gas can be introduced into the reaction chamber at a temperature of, for example, 200°C to 500°C, or 350°C to 400°C, to ammine the Ni for, for example, 3 hours, and grow a nickel nitride layer with a thickness of, for example, 1000nm to 3000nm, or 2000nm to 4000nm, on the second semiconductor layer 50, thereby forming the Schottky electrode 80 on the second semiconductor layer 50.

[0049] See also Figures 8 to 9In another embodiment of the present application, after forming the Schottky electrode 80 in the process of forming the vertical semiconductor device, the substrate 10, the first buffer layer 21 and the second buffer layer 22 are peeled off. The peeling method of the substrate 10, the first buffer layer 21 and the second buffer layer 22 is selected from, for example, chemical peeling, laser peeling or wet etching. In this embodiment, the laser peeling is selected, for example. In other embodiments, the porous stress release layer 30 is separated from the second buffer layer 22 in other ways. The ohmic electrode 90 is formed on one side of the porous stress release layer 30 relative to the Schottky electrode 80. The material of the ohmic electrode 90 is, for example, a mixture of several of titanium, aluminum, nickel or gold. In this embodiment, the multi-layer metal layer is formed by the magnetron sputtering method, for example. Specifically, the titanium / aluminum / titanium / gold multi-layer metal is formed on the porous stress release layer 30 in sequence, and then the ohmic electrode 90 is formed by performing the heat annealing treatment in the nitrogen atmosphere, thereby forming the vertical semiconductor device. In this embodiment, the vertical Schottky diode is obtained, for example. By arranging the porous stress release layer 30 and depositing the semiconductor layer on the porous stress release layer 30, the thermal stress of the first semiconductor layer 40 and the second semiconductor layer 50 is effectively released by the porous stress release layer 30, which greatly reduces the parasitic resistance of the first semiconductor layer 40 and the second semiconductor layer 50, thereby significantly increasing the on-current and improving the performance of the obtained semiconductor structure, such as the cutoff frequency, power and efficiency.

[0050] It is worth noting that in the semiconductor process of the embodiments of the present application, various special gases can be used, such as nitrogen trifluoride, high-purity silane, tetramethylammonium hydroxide, isopropyl alcohol, ammonia, sulfur hexafluoride, phosphine mixed with hydrogen, nitrous oxide. For example, nitrogen trifluoride gas can be used when etching or cleaning. When depositing, high-purity silane gas can be used.

[0051] In different embodiments, the semiconductor device of the present application can be a semiconductor power device or a semiconductor radio frequency device (such as a filter, a power amplifier, a signal amplifier or other radio frequency devices).

[0052] In summary, the utility model provides a kind of semiconductor structure, vertical semiconductor device and horizontal semiconductor device, first buffer layer and second buffer layer are formed in order on substrate, porous stress release layer is formed on second buffer layer, and substrate, first buffer layer and second buffer layer are stripped off. With porous stress release layer as growth substrate, subsequent semiconductor layer is deposited on porous stress release layer, and different types of semiconductor device are formed. By setting the pore size and thickness of porous stress release layer and other characteristics, the semiconductor layer on the porous stress release layer is matched, the thermal stress in the semiconductor layer is released, and the deformation of the semiconductor structure caused by temperature change in subsequent process is avoided. At the same time, the high temperature and high pressure resistance of semiconductor device is significantly improved, the performance of semiconductor device is improved, and the production yield of semiconductor device is improved. The above disclosed embodiments of the utility model are only used to help illustrate the utility model. The embodiments do not describe all the details, nor limit the utility model to the specific implementation described. Obviously, according to the content of the specification, many modifications and changes can be made. The specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the utility model, so that those skilled in the art can well understand and utilize the utility model. The utility model is limited by the claims and the entire scope and equivalents thereof.

Claims

1. A semiconductor structure, characterized by, At least comprising: a substrate; a first buffer layer disposed on the substrate; a second buffer layer disposed on the first buffer layer; a porous stress release layer disposed on the second buffer layer; a first semiconductor layer disposed on the porous stress release layer, and the first semiconductor layer is stress-free; and a second semiconductor layer disposed on the first semiconductor layer, and the second semiconductor layer is stress-free. The pore size of the porous stress release layer is 20nm-100nm, and the thickness of the porous stress release layer is 200nm-500nm.

2. The semiconductor structure of claim 1, wherein, The first semiconductor layer at least contains a doped gallium nitride layer.

3. The semiconductor structure of claim 1, wherein, The second semiconductor layer at least contains a doped gallium nitride layer, and the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer.

4. The semiconductor structure of claim 3, wherein, The first semiconductor layer at least contains an undoped gallium nitride layer.

5. The semiconductor structure of claim 1, wherein, The second semiconductor layer at least contains an undoped aluminum gallium nitride layer.

6. The semiconductor structure of claim 5, wherein, The semiconductor structure further comprises a third semiconductor layer disposed on the second semiconductor layer.

7. The semiconductor structure of claim 5, wherein, The third semiconductor layer at least comprises a gallium nitride layer or a stacked structure of a gallium nitride layer and an aluminum gallium nitride layer.

8. The semiconductor structure of claim 7, wherein, The vertical semiconductor device comprises the semiconductor structure of any one of claims 1-4.

9. A vertical semiconductor device, characterized by comprising: The horizontal semiconductor device comprises the semiconductor structure of any one of claims 1, 5-8.

10. A horizontal type semiconductor device, characterized by comprising: ​

Images