Three-phase intelligent integrated module with low parasitic inductance

Abstract

The utility model aims to solve the problem that the line distance between the grid electrode of an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) chip and a control chip in the existing three-phase power module is too long. The three-phase intelligent integrated module with the low parasitic inductance comprises a power layer, the power layer comprises a bottom plate and a plurality of MOSFET chips, and the MOSFET chips are arranged on the bottom plate in a welded mode; the driving layer is correspondingly arranged above the bottom plate, and the MOSFET chip is located in an area between the bottom plate and the driving layer; a plurality of first lead columns for electric connection are arranged between the driving layer and the bottom plate; one end of the first lead column is welded on the bottom plate and is electrically connected with the MOSFET chip on the bottom plate; the other ends of the first lead columns penetrate through corresponding positioning holes in the driving layers and are welded and fixed between the driving layers; driving chips corresponding to the MOSFET chips in number and position are arranged on the driving layer, and the driving chips are electrically connected with the lead holes; therefore, the distance between the driving chip on the driving layer and the corresponding MOSFET chip is shortest, so that the parasitic inductance of the grid electrode of the MOSFET chip is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of switch control circuits, in particular to a three-phase intelligent integrated module with low parasitic inductance. Background Art

[0002] In the new energy revolution, reducing power device losses is crucial for improving power conversion efficiency and is a critical technology that urgently requires breakthroughs. This is especially true in energy storage applications, where harsh outdoor environments often require core inverters to meet IP68 protection levels. Traditional air cooling is difficult to implement, but low-loss intelligent rectifier modules can dissipate heat naturally, meeting these requirements and broadening their application scenarios.

[0003] With the development of electronic technology, the operating voltage of circuits is getting lower and the current is getting higher. Low voltage operation is beneficial to reducing the overall power consumption of the circuit, but it also poses new challenges to power supply design.

[0004] The losses in a switching power supply primarily consist of three components: power switch losses, high-frequency transformer losses, and output rectifier losses. Under low-voltage, high-current output conditions, the forward voltage drop of the rectifier diode is high, making output rectifier losses particularly significant. The voltage drop of a fast recovery diode (FRD) or ultrafast recovery diode (SRD) can reach 1.0–1.2V. Even with a low-voltage Schottky diode (SBD), a voltage drop of approximately 0.6V occurs, increasing rectification losses and reducing power supply efficiency. Synchronous rectification is a new technology that uses specialized power MOSFETs with extremely low on-state resistance to replace rectifier diodes to reduce rectification losses. It significantly improves DC / DC converter efficiency and eliminates the dead-zone voltage caused by the Schottky barrier voltage; for example, this technology is described in patent publication number CN217935470U. Therefore, synchronous rectification technology significantly reduces rectification losses at the output of a switching power supply, thereby improving conversion efficiency and reducing heat generation.

[0005] However, for MOSFET chips, the lower the switching voltage, the more prominent the parasitic inductance of the gate pin. This parasitic inductance can cause the MOSFET chip to turn on again, leading to a shoot-through burnout. Therefore, the distance from the MOSFET drive signal to the chip's gate pin must be designed to be as short as possible. In existing designs, the driver chip and MOSFET are typically placed on the same horizontal plane, resulting in a long connection line between them. To overcome the difficulties of existing technologies, a three-phase intelligent integrated module with low parasitic inductance is proposed. Summary of the Invention

[0006] The purpose of the utility model is to solve the deficiencies of the prior art and provide a three-phase intelligent integrated module with low parasitic inductance.

[0007] To solve the above problems, the utility model adopts the following scheme:

[0008] A low parasitic inductance three-phase intelligent integrated module, including power layer, power layer includes bottom plate and a plurality of MOSFET chip, MOSFET chip is welded to set up on the bottom plate and is composed of switch control circuit, still include drive layer, drive layer is correspondingly set up above the bottom plate, MOSFET chip is located the area between the bottom plate and drive layer, a plurality of first lead posts for electric connection are arranged between drive layer and bottom plate, one end of first lead post is welded to set up on the bottom plate, and is electrically connected with MOSFET chip on the bottom plate, the other end of first lead post passes through the corresponding positioning hole on drive layer, and is welded and fixed between drive layer, drive layer is provided with the drive chip corresponding with the number and position of MOSFET chip, and the drive chip is electrically connected with lead hole.

[0009] Further, the bottom plate adopts an aluminum-based copper-clad plate, and pads are processed on the aluminum-based copper-clad plate by developing etching. The remaining positions on the aluminum-based copper-clad plate are covered with solder resist films.

[0010] Further, six MOSFET chips are arranged on the bottom plate, three of the six MOSFET chips form a group and are distributed on two sides of the square bottom plate, and the MOSFET chips on the two sides are arranged correspondingly.

[0011] Further, three input power electrodes and two output power electrodes are further arranged on the bottom plate. The input power electrodes are vertically arranged above the bottom plate, the three input power electrodes are arranged correspondingly to the three MOSFET chips on one side of the bottom plate, a cross bridge is arranged between the input power electrode and the MOSFET chip on the other side of the bottom plate, one end of the cross bridge is connected to the input power electrode, and the other end of the cross bridge is connected to the corresponding MOSFET chip. The output power electrodes are vertically arranged on the side edges of the bottom plate, and the output power electrodes and the MOSFET chips are arranged on three edges of the bottom plate, respectively.

[0012] Further, a plurality of red copper blocks are further arranged in series between the input power electrodes and the output power electrodes.

[0013] Further, capacitors for eliminating parasitic inductance are further arranged on the bottom plate. There are three capacitors, and the three capacitors are arranged in the areas between the two groups of MOSFET chips, respectively. The three capacitors correspond to the three MOSFET chips, respectively. The two ends of the capacitors are connected to the gates of the corresponding two MOSFET chips on the two sides of the bottom plate, respectively.

[0014] Further, the first lead post is made of red copper material. A tinning layer, a silver plating layer, or a gold plating layer is arranged on the surface of the first lead post.

[0015] Further, the bottom plate is further provided with sampling resistors, and the sampling resistors are three in total and are correspondingly arranged with the three MOSFET chips on one side of the bottom plate; the sampling resistors are arranged in series with the source or drain of the MOSFET chips; and the sampling resistors are connected with the driving layer through the second lead column.

[0016] Further, the bottom plate is further provided with sampling resistors, and the sampling resistors are three in total and are correspondingly arranged with the three MOSFET chips on one side of the bottom plate; the sampling resistors are arranged in series with the source or drain of the MOSFET chips; and the sampling resistors are connected with the driving layer through the second lead column.

[0017] Further, the bottom plate is further provided with sampling resistors, and the sampling resistors are three in total and are correspondingly arranged with the three MOSFET chips on one side of the bottom plate; the sampling resistors are arranged in series with the source or drain of the MOSFET chips; and the sampling resistors are connected with the driving layer through the second lead column.

[0018] The utility model discloses the beneficial effects are:

[0019] Through setting the power layer and the driving layer of upper and lower layer split, the distance between the driving chip on the driving layer and the respective corresponding MOSFET chip is shortest, so as to reduce the parasitic inductance of MOSFET chip gate, avoids the burning of MOSFET chip because of secondary open problem;

[0020] Through setting the sampling resistor, the working state of MOSFET chip is sampled, and the MOSFET chip that appears abnormally can be found in time;

[0021] Through the series connection of several red copper blocks between the input power electrode and the output power electrode on the bottom plate, the overcurrent capacity of the switching circuit is enhanced, and the line loss is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is the whole structure schematic diagram of embodiment 1;

[0023] Figure 2 It is the whole structure explosion drawing of embodiment 1;

[0024] Figure 3 It is the power layer of embodiment 1 schematic Figure 1 ;

[0025] Figure 4 It is the power layer of embodiment 1 schematic Figure 2 .

[0026] The drawing mark explanation: power layer 1, bottom plate 11, MOSFET chip 12, first lead column 13, input power electrode 14, output power electrode 15, red copper block 16, capacitor 17, sampling resistance 18, second lead column 19, aluminum sleeve 110, connecting bridge 111, copper particle 112, driving layer 2, shell 3. DETAILED DESCRIPTION

[0027] The implementation of the present application will be described below by specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied by different specific embodiments, and the details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0028] It should be noted that the drawings provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the drawings, not the number, shape and size of the components when actually implemented. The shape, number and proportion of each component in actual implementation can be changed arbitrarily, and the component layout pattern can also be more complex.

[0029] Example 1:

[0030] As Figures 1-4As shown, a low parasitic inductance three-phase intelligent integrated module includes a power layer 1, the power layer 1 includes a bottom plate 11 and a plurality of MOSFET chips 12, the MOSFET chips 12 are welded on the bottom plate 11 and constitute a switch control circuit; further includes a driving layer 2, the driving layer 2 is correspondingly arranged above the bottom plate 11, the MOSFET chips 12 are located between the bottom plate 11 and the driving layer 2; a plurality of first lead columns 13 for electrical connection are arranged between the driving layer 2 and the bottom plate 11; one end of the first lead column 13 is welded on the bottom plate 11 and is electrically connected with the MOSFET chip 12 on the bottom plate 11; the other end of the first lead column 13 passes through the corresponding positioning hole on the driving layer 2 and is welded and fixed between the driving layer 2; the driving layer 2 is provided with a driving chip corresponding to the number and position of the MOSFET chip 12, and the driving chip is electrically connected with the lead hole. Wherein the driving layer 2 and the bottom plate 11 are arranged through upper and lower layers, the driving chip on the driving layer 2 is connected with the MOSFET chip 12 through the first lead column 13, so that the distance between the two is extremely short, effectively reducing the parasitic inductance of the gate of the MOSFET chip 12, on the one hand reducing the reactive power loss, on the other hand avoiding the burning of MOSFET due to the secondary opening problem. It should be noted that a plurality of cylindrical copper particles 112 for limiting the height of the driving layer 2 are arranged on the bottom plate 11, so as to avoid the distance between the driving layer 2 and the bottom plate 11 being too small, and in this example, the height of the copper particle 112 is slightly higher than the height of the MOSFET chip 12 on the bottom plate 11.

[0031] The bottom plate 11 adopts an aluminum-based copper-clad plate, and pads are processed on the aluminum-based copper-clad plate by developing etching, and the remaining positions on the aluminum-based copper-clad plate are covered with solder resist film; it should be noted that the developing etching process is a prior method.

[0032] The bottom plate 11 is provided with six MOSFET chips 12, and the six MOSFET chips 12 are three in a group and are distributed on two sides of the square bottom plate 11, and the three MOSFET chips 12 in each group correspond to one phase of three-phase power respectively; the MOSFET chips 12 on the two sides are correspondingly arranged; in this example, the MOSFET chip 12 is located on the longer two side edges of the square bottom plate 11.

[0033] The bottom plate 11 is also provided with three input power electrodes 14 and two output power electrodes 15; wherein the input power electrodes 14 are vertically arranged above the bottom plate 11, the three input power electrodes 14 are respectively arranged corresponding to the three MOSFET chips 12 on one side of the bottom plate 11, a cross-bridge 111 is arranged between the input power electrode 14 and the MOSFET chip 12 on the other side of the bottom plate 11, one end of the cross-bridge 111 is connected with the input power electrode 14, and the other end of the cross-bridge 111 is connected with the corresponding MOSFET chip 12; in this example, the cross-bridge 111 is integrally made with the input power electrode 14; the output power electrode 15 is vertically arranged on the side edge of the bottom plate 11, and the MOSFET chip 12 is arranged on the three edges of the bottom plate 11. A plurality of red copper blocks 16 are also arranged in series between the input power electrode 14 and the output power electrode 15, for enhancing the overcurrent capacity of the switching circuit and reducing the line loss.

[0034] The bottom plate 11 is also provided with a capacitor 17 for eliminating parasitic inductance, and the capacitor 17 is three in total, and the three capacitors 17 are respectively arranged in the region between the two groups of MOSFET chips 12; wherein the three capacitors 17 respectively correspond to the three MOSFET chips 12; the two ends of the capacitor 17 are respectively connected to the gates of the corresponding two MOSFET chips 12 on the two sides of the bottom plate 11, so as to eliminate the parasitic inductance of the gate.

[0035] The first lead column 13 is made of red copper material; the surface of the first lead column 13 is provided with a tin plating layer or a silver plating layer or a gold plating layer, so as to reduce the conduction loss of the first lead column 13 and improve the welding quality.

[0036] The bottom plate 11 is also provided with a sampling resistor 18, and the sampling resistor 18 is three in total, and the three sampling resistors 18 are respectively arranged corresponding to the three MOSFET chips 12 on one side of the bottom plate 11; the sampling resistor 18 is arranged in series with the source or drain of the MOSFET chip 12; the sampling resistor 18 is also connected with the driving layer 2 through the second lead column 19. The sampling resistor 18 is used for collecting the current and voltage in the circuit, so as to facilitate the switching control of the MOSFET chip 12 by the driving chip.

[0037] The side of the bottom plate 11 close to the driving layer 2 is also provided with an aluminum sleeve 110 for helping to position the driving layer 2; the aluminum sleeve 110 is a hollow column in whole, and the bottom plate 11 is provided with a hole position corresponding to the aluminum sleeve 110; one end of the aluminum sleeve 110 is fixedly connected with the bottom plate 11, and the four corners of the driving layer 2 are provided with a circular-arc-shaped notch or a circular hole corresponding to the aluminum sleeve 110; in this example, the driving layer 2 is provided with a circular-arc-shaped notch close to the four corners, which is in close contact with the outside of the aluminum sleeve 110, so that the driving layer 2 can be embedded between the four aluminum sleeves 110 to realize positioning.

[0038] The shell 3 covers the power layer 1 and the driving layer 2, the bottom plate 11 of the power layer 1 is embedded in the lower surface of the shell 3, the shell 3 is filled with two-component silica gel or resin, solidification is achieved, and the packaged device has good dustproof, moistureproof and arc resistance performance. The shell 3 and the aluminum sleeve 110 on the bottom plate 11 are fixedly connected through studs and nuts.

[0039] In the implementation process, the power layer 1 and the driving layer 2 are set to be separated from each other, so that the distance between the driving chip on the driving layer 2 and the corresponding MOSFET chip 12 is the shortest, the parasitic inductance of the MOSFET chip 12 gate is reduced, and the MOSFET chip 12 is prevented from being burned due to secondary opening; the working state of the MOSFET chip 12 is sampled through the sampling resistor 18, the MOSFET chip 12 that appears abnormally can be found in time; a plurality of red copper blocks 16 are connected in series between the input power electrode 14 and the output power electrode 15 on the bottom plate 11, for enhancing the overcurrent capacity of the switching circuit and reducing the line loss.

[0040] The above description is only one specific example of the present application and does not constitute any limitation on the present application. Obviously, for those skilled in the art, after understanding the content and principle of the present application, various modifications and changes in form and details can be made without departing from the principle and structure of the present application, but these modifications and changes based on the idea of the present application are still within the protection scope of the claims of the present application.

Claims

1. A low parasitic inductance three-phase intelligent integrated module, comprising a power layer (1), the power layer (1) comprising a bottom plate (11) and a plurality of MOSFET chips (12), the MOSFET chips (12) being welded on the bottom plate (11) and constituting a switch control circuit; characterized in that, Further comprising a driving layer (2), the driving layer (2) is correspondingly arranged above the bottom plate (11), the MOSFET chip (12) is located in the area between the bottom plate (11) and the driving layer (2); A plurality of first lead columns (13) for electrical connection are arranged between the driving layer (2) and the bottom plate (11); One end of the first lead column (13) is welded on the bottom plate (11) and electrically connected with the MOSFET chip (12) on the bottom plate (11); The other end of the first lead column (13) passes through the corresponding positioning hole of the driving layer (2) and is welded and fixed between the driving layer (2); The driving layer (2) is provided with driving chips corresponding to the number and position of the MOSFET chip (12), and the driving chip is electrically connected with the lead hole.

2. A low parasitic inductance three-phase smart integrated module according to claim 1, characterized in that, The bottom plate (11) is made of aluminum-based copper-clad plate, and the solder pad is processed on the aluminum-based copper-clad plate by developing etching. The rest of the aluminum-based copper-clad plate is covered with a solder resist film.

3. A low parasitic inductance three-phase smart integrated module according to claim 2, characterized in that, Six MOSFET chips (12) are arranged on the bottom plate (11), three of which are a group and are distributed on both sides of the square bottom plate (11); The MOSFET chips (12) on both sides are correspondingly arranged.

4. A low parasitic inductance three-phase smart integrated module according to claim 3, characterized in that, Three input power electrodes (14) and two output power electrodes (15) are further arranged on the bottom plate (11); The input power electrode (14) is vertically arranged above the bottom plate (11), and the three input power electrodes (14) are correspondingly arranged with the three MOSFET chips (12) on one side of the bottom plate (11), respectively. A jumper (111) is arranged between the input power electrode (14) and the MOSFET chip (12) on the other side of the bottom plate (11), one end of the jumper (111) is connected with the input power electrode (14), and the other end of the jumper (111) is connected with the corresponding MOSFET chip (12); The output power electrode (15) is vertically arranged on the side edge of the bottom plate (11), and the output power electrode (15) and the MOSFET chip (12) are arranged on three edges of the bottom plate (11), respectively.

5. A low parasitic inductance three-phase smart integrated module according to claim 4, characterized in that, A plurality of red copper blocks (16) are further arranged in series between the input power electrode (14) and the output power electrode (15).

6. A low parasitic inductance three-phase smart integrated module according to claim 3, characterized in that, A capacitor (17) for eliminating parasitic inductance is further arranged on the bottom plate (11), and there are three capacitors (17), which are arranged in the area between the two groups of MOSFET chips (12), respectively; The three capacitors (17) correspond to the three MOSFET chips (12), respectively; The two ends of the capacitor (17) are respectively connected with the gate electrodes of the corresponding two MOSFET chips (12) on both sides of the bottom plate (11).

7. The low parasitic inductance, three-phase intelligent integrated module of claim 1, wherein, The first lead column (13) is made of red copper material; The surface of the first lead column (13) is provided with a tin plating layer or a silver plating layer or a gold plating layer.

8. The low parasitic inductance, three-phase intelligent integrated module of claim 1, wherein, The bottom plate (11) is further provided with three sampling resistors (18), and the three sampling resistors (18) are respectively arranged in correspondence with the three MOSFET chips (12) on one side of the bottom plate (11); the sampling resistors (18) are arranged in series with the source or drain of the MOSFET chips (12); and the sampling resistors (18) are further connected with the driving layer (2) through the second lead posts (19).

9. The low parasitic inductance, three-phase intelligent integrated module of claim 1, wherein, The bottom plate (11) is further provided with an aluminum sleeve (110) on the side close to the driving layer (2) for positioning the driving layer (2); the aluminum sleeve (110) is in a hollow columnar shape as a whole, and the bottom plate (11) is provided with a hole position corresponding to the aluminum sleeve (110); one end of the aluminum sleeve (110) is fixedly connected with the bottom plate (11), and the four corners of the driving layer (2) are provided with a circular-arc-shaped notch or a circular hole corresponding to the aluminum sleeve (110).

10. A low parasitic inductance three-phase smart integrated module according to claim 9, characterized in that, Further comprising a shell (3) covering the power layer (1) and the driving layer (2) from above; the bottom plate (11) of the power layer (1) is embedded in the lower surface of the shell (3), and the shell (3) is filled with two-component silica gel or resin inside; and the shell (3) and the aluminum sleeve (110) on the bottom plate (11) are fixedly connected through the stud and the nut.

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