Radar information processing system-level chip based on SIP technology

Abstract

The utility model belongs to the technical field of electronics, and particularly relates to a radar information processing system-level chip based on an SIP technology and a substrate. The ZYNQ chip, the DSP chip, the two sets of SPI FLASH chips and the set of DDR3SDRAM chip are located on the front face of the substrate; the two groups of DDR3SDRAM chips are positioned on the back surface of the substrate; wherein the ZYNQ chip is connected with the DSP chip, the group of SPI FLASH chips and the two groups of DDR3SDRAM chips; the DSP chip is further connected with a group of DDR3SDRAM chips and a group of SPI FLASH chips, a plurality of chips are reasonably placed on the high-density circuit substrate, the integration level is high, wiring on the substrate is shorter than wiring on a traditional PCB and fixed in position, such as DDR3, repeated wiring is not needed, and the system stability is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronics, and particularly relates to a radar information processing system-level chip based on SIP technology. BACKGROUND

[0002] With the development of integrated radar technology, airborne radars have been innovatively developed in structure, volume, weight and architecture, and have further advanced in miniaturization and ultra-thin design, which has put forward technical requirements of ultra-thin and small size, high reliability and rapid prototyping for airborne radar information processing units. Traditional radar processing systems are generally based on a chassis backplane, and each functional module is inserted on the chassis backplane, and the backplane completes the signal interconnection and data exchange between modules. The chassis backplane is large in size, which is not conducive to the construction of RF integrated small radars.

[0003] RF integrated small radars put forward new requirements for data acquisition and data processing systems, and the acquisition and processing systems are moved forward in function under the condition that the processing performance is not reduced. Each antenna array unit needs to directly mount a data acquisition and processing system on the back, and the data transmission and processing between arrays are performed after pre-processing and signal processing. The traditional way is to design an integrated comprehensive board, and multiple processors such as CPU, DSP and FPGA are integrated on the single board. Although the form is thin, the PCB size is large, and the space dependence is also high, which is difficult to meet the requirements of RF integrated small radars.

[0004] SiP technology can integrate multiple high-performance processors, memories and other types of dies in a chip package according to different use scenarios, and has the advantages of small size, light weight, high integration, low power consumption and high reliability. Moreover, part of the wiring between processors has been completed inside the SiP, which can greatly reduce the wiring layer requirement of the PCB.

[0005] The radar information processing system-level chip based on the SiP module design is directly placed on the back of the TR component and co-designed with the radio frequency to complete the AD data acquisition function and the down-conversion function, the digital signal processing and data exchange function, the generation function of various intermediate frequency excitation waveforms required by radar transmission, the various timing waveforms required by the radio frequency unit, and the radio frequency control function, which can meet the requirements of multi-array RF integrated C, X, L and S multi-band radars. SUMMARY

[0006] To solve the above problems, the present application provides 1, a radar information processing system-level chip based on SIP technology, comprising:

[0007] a substrate;

[0008] a ZYNQ chip, a DSP chip, two groups of SPI FLASH chips and a group of DDR3 SDRAM chips located on the front of the substrate;

[0009] Two sets of DDR3 SDRAM chips located on the back of the substrate;

[0010] in,

[0011] The ZYNQ chip is connected to a DSP chip, a set of SPI FLASH chips, and two sets of DDR3 SDRAM chips;

[0012] The DSP chip is further connected to a group of DDR3 SDRAM chips and a group of SPI FLASH chips.

[0013] Preferably, the GPIO, reset, EMIF, UART, reset completion flag, and loading completion flag control pins of the DSP chip are all introduced into the ZYNQ chip.

[0014] Preferably, the two groups of SPI FLASH chips include the first SPI FLASH chip and the second SPI FLASH chip, the first SPI FLASH chip includes SPI interface FLASH, capacity 256Mb, and power supply 3.3V; the second SPI FLASH chip includes SPI interface FLASH, capacity 256Mb, and power supply 1.8V.

[0015] Preferably, the three groups of DDR3 chips include a first group of DDR3 SDRAM chips connected to the PS end of the ZYNQ chip, a second group of DDR3 SDRAM chips connected to the PL end of the ZYNQ chip, and a third group of DDR3 SDRAM chips connected to the DSP chip.

[0016] Preferably, the first group of DDR3 SDRAM chips has two chips, with a total memory of not less than 1GB and a speed of not less than 1066Mbps; the second group of DDR3 SDRAM chips has four chips, with a total memory of not less than 4GB and a speed of not less than 1600Mbps; the third group of DDR3 SDRAM chips has four chips, with a total memory of not less than 4GB and a speed of not less than 1333Mbps.

[0017] Preferably, the ZYNQ chip bare DIE and the DSP chip bare DIE are both flip-chip mounted on the surface of the transfer substrate and encapsulated using a plastic encapsulation process.

[0018] Preferably, the first group of DDR3 SDRAM chip bare DIEs are flipped on the surface of the transfer substrate by flip-chip soldering, and the other two groups of DDR3 SDRAM chip bare DIEs are flipped on the surface of the transfer substrate by flip-chip soldering, and rewiring is performed by RDL.

[0019] Preferably, the two groups of SPI FLASH adopt DFN packaging, and the two groups of SPI FLASH are attached to the surface of the substrate in an SMT manner.

[0020] Preferably, the external high-speed interface of the system-level chip comprises 12-channel GTX of ZYNQ, 4X SRIO, 4X PCIE and 1X SGMII of DSP.

[0021] Preferably, the ZYNQ adopts FMQL45T900, and the DSP adopts FT-M6678N.

[0022] Advantages of the present application include:

[0023] Advantages of the present application include:

[0024] (1) In the present application, multiple chips are reasonably placed on a high-density circuit substrate, and the integration degree is high. The wiring on the substrate is shorter than that of a traditional PCB and is fixed in position, for example, DDR3, which does not require repeated wiring, and the system stability is greatly improved.

[0025] (2) In the present application, multiple chips are packaged together in the form of bare DIE, and the system volume is greatly reduced. The computing power is improved by more than 1 times in the same volume, which is convenient for miniaturization and thinning, has a wide range of use scenarios, and is safe and reliable.

[0026] (3) In the present application, various chips used can adopt domestic chips, which is of great significance to the development of domestic components, electronic component technology and the maturity of SIP packaging technology. Moreover, the present application leads out most of the required FPGA and DSP interfaces for user use, so that it has good expansibility and flexibility.

[0027] (4) In the present application, ZYNQ, DSP, DDR3 and SPI FLASH can form a minimum signal processing system, and the functions of the board level are packaged in the micro system to realize the modularization of system functions.

[0028] (5) In the present application, double-sided layout is adopted, and part of the DDR3 and solder balls are packaged on one side, which greatly reduces the packaging size.

[0029] (6) In the present application, there are 10 pieces of DDR3 inside the chip, and the maximum storage capacity can reach 9 GB, which greatly meets the storage requirements.

[0030] (7) The present application is especially suitable for scenarios with urgent demand for miniaturization, such as skin-integrated radar and seeker. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1A system-level chip architecture diagram based on SIP technology is provided for the embodiment of the present application.

[0032] Figure 2 A system-level chip package side structure diagram based on SIP technology is provided for the embodiment of the present application.

[0033] Figure 3 A system-level chip adapter substrate layout diagram based on SIP technology is provided for the embodiment of the present application.

[0034] Figure 4 A system-level chip effect diagram on a certain weather radar is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the technical solutions of the present application and the advantages thereof clearer, the technical solutions of the present application will be further clearly, completely and specifically described below with reference to the drawings. It should be understood that the specific embodiments described herein are only part of the embodiments of the present application, and are only used to explain the present application, but not to limit the present application. It should be noted that, for the purpose of description, only parts related to the present application are shown in the drawings, and other related parts can be referred to the general design. In the case of no conflict, the embodiments in the present application and the technical features in the embodiments can be combined to obtain new embodiments.

[0036] In order to solve the above problems, the present application provides 1, a radar information processing system-level chip based on SIP technology, comprising:

[0037] a substrate;

[0038] a ZYNQ chip, a DSP chip, two groups of SPI FLASH chips and a group of DDR3 SDRAM chips located on the front surface of the substrate;

[0039] two groups of DDR3 SDRAM chips located on the back surface of the substrate;

[0040] The ZYNQ chip is connected with the DSP chip, a group of SPI FLASH chips and two groups of DDR3 SDRAM chips.

[0041] The DSP chip is further connected with a group of DDR3 SDRAM chips and a group of SPI FLASH chips.

[0042] Preferably, the GPIO, reset, EMIF, UART, reset completion identifier and loading completion identifier control pins of the DSP chip are all introduced into the ZYNQ chip.

[0043] Preferably, the two groups of SPI FLASH chips include the first SPI FLASH chip and the second SPI FLASH chip, the first SPI FLASH chip includes a SPI interface FLASH, has a capacity of 256 Mb, and is powered by 3.3 V; and the second SPI FLASH chip includes a SPI interface FLASH, has a capacity of 256 Mb, and is powered by 1.8 V.

[0044] Preferably, the three groups of DDR3 chips include a first group of DDR3 SDRAM chips connected to the PS end of the ZYNQ chip, a second group of DDR3 SDRAM chips connected to the PL end of the ZYNQ chip, and a third group of DDR3 SDRAM chips connected to the DSP chip.

[0045] Preferably, the first group of DDR3 SDRAM chips has 2 pieces, a total memory of not less than 1 GB, and a rate of not less than 1066 Mbps; the second group of DDR3 SDRAM chips has 4 pieces, a total memory of not less than 4 GB, and a rate of not less than 1600 Mbps; and the third group of DDR3 SDRAM chips has 4 pieces, a total memory of not less than 4 GB, and a rate of not less than 1333 Mbps.

[0046] Preferably, the ZYNQ chip bare DIE and the DSP chip bare DIE are both inverted and buckled on the surface of the adapter substrate by flip-chip welding and are packaged by a plastic packaging process.

[0047] Preferably, the first group of DDR3 SDRAM chip bare DIE is inverted and buckled on the surface of the adapter substrate by flip-chip welding, and the bare DIE of the other two groups of DDR3 SDRAM chips is inverted and buckled on the surface of the adapter substrate by flip-chip welding, and is rewired by RDL.

[0048] Preferably, the two groups of SPI FLASH are packaged by DFN, and the two groups of SPI FLASH are attached to the surface of the substrate by SMT.

[0049] Preferably, the external high-speed interface of the system-level chip includes 12-way GTX of the ZYNQ end, 4X SRIO, 4X PCIE, and 1X SGMII of the DSP end.

[0050] Preferably, the ZYNQ adopts FMQL45T900, and the DSP adopts FT-M6678N.

[0051] Preferably, the DSP adopts FT-M6678 of Soochow University, the ZYNQ adopts ZYNQ FMQL45T900 of Fudan Micro, the SPIFLASH adopts JFM25QL256 of Fudan Micro, and the second group of SPI FLASH adopts SM25QU256MX of Guomicro.

[0052] Preferably, the free pins of ZYNQ and DSP are all led out through RDL (Re Distribution Layer) technology to increase the expansibility of the chip.

[0053] Preferably, the system-level chip adopts the ZYNQ+DSP architecture internal processor equivalent to FPGA+ARM+DSP, which can meet the functions of data processing, control, preprocessing, signal processing and the like, and has powerful processing capability.

[0054] In combination with Figure 2 Figure 3 It is illustrated that the system-level chip is packaged: in the embodiment, SIP is used, and the SIP includes TSV, RDL, MCM and other packaging processes. The packaging size of the SIP is 45mmX40mmX4.5mm.

[0055] In combination with Figure 4 It is illustrated that the system-level chip provided by the embodiment has an effect diagram on a certain weather radar, wherein the ZYNQ+DSP part can be directly replaced by the system-level chip, and the size of the processing module is reduced from 120mmX120mm to 60mmX60mm. Data received by the AD9371 is input to the ZYNQ through the JESD204B bus, the ZYNQ module performs preprocessing, and then sends the data to the DSP processor through the SRIO bus for sampling processing, low-pass filtering, FFT transformation, CFAR target detection and tracking, low-altitude obstacle detection and classification and the like. The processing result is returned to the ZYNQ through the SRIO for data recording and uploading. The ZYNQ simultaneously performs task scheduling on the radar subsystem according to the working condition of the current radar, generates a radar subsystem timing signal and a subsystem control signal, controls the working mode of the servo controller through the RS485, and monitors the working state of the radar.

[0056] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A radar information processing system-on-chip based on SIP technology, characterized by, It comprises: a substrate; a ZYNQ chip, a DSP chip, two groups of SPI FLASH chips and a group of DDR3 SDRAM chips on the front of the substrate; two groups of DDR3 SDRAM chips on the back of the substrate; wherein, the ZYNQ chip is connected with the DSP chip, a group of SPI FLASH chips and two groups of DDR3 SDRAM chips; the DSP chip is connected with a group of DDR3 SDRAM chips and a group of SPI FLASH chips.

2. The SIP technology based radar information processing system-on-chip of claim 1, wherein, The GPIO, reset, EMIF, UART, reset completion identifier and loading completion identifier control pins of the DSP chip are introduced into the ZYNQ chip.

3. The SIP technology based radar information processing system-on-chip of claim 1, wherein, The two groups of SPIFLASH chips comprise a first SPI FLASH chip and a second SPI FLASH chip, the first SPI FLASH chip comprises a FLASH with an SPI interface, a capacity of 256Mb and a power supply of 3.3V; the second SPI FLASH chip comprises a FLASH with an SPI interface, a capacity of 256Mb and a power supply of 1.8V.

4. The SIP technology based radar information processing system-on-chip of claim 1, wherein, The three groups of DDR3 chips comprise a first group of DDR3 SDRAM chips connected with the PS end of the ZYNQ chip, a second group of DDR3 SDRAM chips connected with the PL end of the ZYNQ chip and a third group of DDR3 SDRAM chips connected with the DSP chip.

5. The SIP technology based radar information processing system-on-chip of claim 4, wherein, The first group of DDR3 SDRAM chips has 2 pieces, the total memory is not less than 1GB and the rate is not less than 1066Mbps; the second group of DDR3 SDRAM chips has 4 pieces, the total memory is not less than 4GB and the rate is not less than 1600Mbps; the third group of DDR3 SDRAM chips has 4 pieces, the total memory is not less than 4GB and the rate is not less than 1333Mbps.

6. The SIP technology based radar information processing system-on-chip of claim 1, wherein, The ZYNQ chip bare DIE and the DSP chip bare DIE are both inverted and buckled on the surface of the adapter substrate by means of flip-chip soldering and are packaged by using a plastic packaging process.

7. The SIP technology based radar information processing system-on-chip of claim 5, wherein, The first group of DDR3 SDRAM chip bare DIE is inverted and buckled on the surface of the adapter substrate by means of flip-chip soldering, and the bare DIE of the other two groups of DDR3 SDRAM chips is inverted and buckled on the surface of the adapter substrate by means of flip-chip soldering, and is rewired by means of RDL.

8. The SIP technology based radar information processing system-on-chip of claim 1, wherein, The two groups of SPIFLASH are packaged by DFN, and the two groups of SPI FLASH are attached on the surface of the substrate by SMT.

9. The SIP technology based radar information processing system-on-chip of claim 1, wherein, The high-speed interface of the system-level chip to the outside comprises 12 GTX of the ZYNQ end, 4X SRIO, 4X PCIE and 1X SGMII of the DSP end.

10. The SIP technology based radar information processing system-on-chip of claim 1, wherein, The ZYNQ adopts FMQL45T900, and the DSP adopts FT-M6678N.

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