Electrostatic protection circuit and radio frequency front-end chip

Abstract

The utility model provides an electrostatic protection circuit and a radio frequency front-end chip, and the electrostatic protection circuit comprises a plurality of stages of clamping circuits which are sequentially connected and are of a multi-stage stacking structure, and a resistor. Each stage of clamping circuit comprises a first field effect transistor, a second field effect transistor, a capacitor, a driving circuit, a third field effect transistor and a diode; the first end of the resistor is connected to a power supply to be protected, and the second end of the resistor is connected to the second end of the capacitor in the first-stage clamping circuit. The electrostatic protection circuit provided by the utility model can improve the discharge capability of the radio frequency front-end chip, shorten the opening time of the trigger circuit and enhance the effect of electrostatic discharge resistance under the condition of the same layout area of the radio frequency front-end chip.

Description

TECHNICAL FIELD

[0001] The utility model relates to wireless communication technical field especially relates to a static protection circuit and radio frequency front end chip. BACKGROUND

[0002] In the design of radio frequency front end chip, silicon-on-insulator (SOI) technology on insulating substrate has been applied more and more in the field of small power because of its low cost advantage, but because the gate oxide layer of SOI CMOS circuit is thin and the diffusion depth is shallow, it will lead to its natural disadvantage in electro static discharge (ESD) resistance.

[0003] In the prior art, the working voltage end of radio frequency front end chip often adopts multi-stage RC trigger power embedded position circuit to improve its electro static discharge resistance performance, and each stage of embedded position circuit in multi-stage RC trigger power embedded position circuit adopts the design method of capacitor, resistor and diode.

[0004] Although the design method of the above multi-stage RC trigger power embedded position circuit improves the electro static discharge resistance performance of radio frequency front end chip to some extent, its discharge capacity is weak, the opening time of trigger circuit is long, and its electro static discharge resistance performance is still limited, which is not easy to meet the electro static discharge resistance requirement in the design of radio frequency front end chip, and if you want to further improve its electro static discharge resistance effect, you must increase the board area of radio frequency front end chip, which will lead to cost increase. UTILITY MODEL CONTENTS

[0005] In view of the above technical problems of prior art, the utility model provides a static protection circuit and radio frequency front end chip to solve the problem that the design method of embedded position circuit in prior art will lead to weak discharge capacity, long opening time of trigger circuit and poor electro static discharge resistance effect.

[0006] In order to solve the above technical problem, the utility model adopts the following technical scheme:

[0007] Firstly, the utility model provides a static protection circuit, which comprises a plurality of embedded position circuits connected in sequence and a plurality of resistors in a multi-stage stacking structure.

[0008] Each embedded position circuit comprises a first field effect tube, a second field effect tube, a capacitor, a driving circuit, a third field effect tube and a diode.

[0009] The gate of the first field effect tube is connected to the drain of the first field effect tube.

[0010] The source of the second field effect tube is connected to the drain of the first field effect tube, and the gate of the second field effect tube is connected to the drain of the second field effect tube;

[0011] The first end of the capacitor is connected to the drain of the second field effect tube;

[0012] The input end of the driving circuit is connected to the second end of the capacitor, and the first voltage connection end of the driving circuit is connected to the first end of the capacitor;

[0013] The gate of the third field effect tube is connected to the output end of the driving circuit; and the driving circuit is used for controlling the opening or closing of the first field effect tube, the second field effect tube and the third field effect tube;

[0014] The source of the first field effect tube in the first-stage embedding circuit is used for connecting to the power supply to be protected, the second voltage connection end of the driving circuit in the first-stage embedding circuit is used for connecting to the power supply to be protected, the drain of the third field effect tube in the first-stage embedding circuit is used for connecting to the power supply to be protected, and the negative electrode of the diode in the first-stage embedding circuit is used for connecting to the power supply to be protected;

[0015] The source of the first field effect tube in the next-stage embedding circuit is connected to the drain of the second field effect tube in the previous-stage embedding circuit, the second end of the capacitor in the next-stage embedding circuit is connected to the first end of the capacitor in the previous-stage embedding circuit, the second voltage connection end of the driving circuit in the next-stage embedding circuit is connected to the output end of the driving circuit in the previous-stage embedding circuit, the drain of the third field effect tube in the next-stage embedding circuit is connected to the source of the third field effect tube in the previous-stage embedding circuit, and the negative electrode of the diode in the next-stage embedding circuit is connected to the positive electrode of the diode in the previous-stage embedding circuit;

[0016] The drain of the second field effect tube, the source of the third field effect tube and the positive electrode of the diode in the last-stage embedding circuit are all grounded;

[0017] The first end of the resistor is used for connecting to the power supply to be protected, and the second end of the resistor is connected to the second end of the capacitor in the first-stage embedding circuit.

[0018] Preferably, the driving circuit comprises a fourth field effect tube, a fifth field effect tube, a sixth field effect tube, a seventh field effect tube, an eighth field effect tube and a ninth field effect tube;

[0019] The gate of the fourth field effect tube and the gate of the fifth field effect tube are connected and jointly serve as an input end of the driving circuit, and the drain of the fourth field effect tube is connected to the drain of the fifth field effect tube;

[0020] The drain of the fourth field effect tube, the drain of the fifth field effect tube, the gate of the sixth field effect tube and the gate of the seventh field effect tube are connected to each other;

[0021] The drain of the sixth field effect tube is connected to the drain of the seventh field effect tube;

[0022] The drain of the sixth field effect tube, the drain of the seventh field effect tube, the gate of the eighth field effect tube and the gate of the ninth field effect tube are connected to each other;

[0023] The drain of the eighth field effect tube and the drain of the ninth field effect tube are connected and jointly serve as an output end of the driving circuit;

[0024] The source of the fifth field effect tube, the source of the seventh field effect tube and the source of the ninth field effect tube are connected to each other and jointly serve as a first voltage connection end of the driving circuit, and the source of the fourth field effect tube, the source of the sixth field effect tube and the source of the eighth field effect tube are connected to each other and jointly serve as a second voltage connection end of the driving circuit.

[0025] Preferably, the first field effect tube, the second field effect tube, the fourth field effect tube, the sixth field effect tube and the eighth field effect tube are all P-type field effect tubes.

[0026] Preferably, the third field effect tube, the fifth field effect tube, the seventh field effect tube and the ninth field effect tube are all N-type field effect tubes.

[0027] In a second aspect, the utility model provides a radio frequency front-end chip, it includes the electrostatic protection circuit as described above.

[0028] Compared with the prior art, the electrostatic protection circuit in the utility model can improve the discharge capacity of the electrostatic protection circuit, shorten the opening time of the trigger circuit and enhance the anti-static discharge effect by designing the embedding circuit comprising the first field effect tube, the second field effect tube, the capacitor, the driving circuit, the third field effect tube and the diode and additionally arranging the resistor under the condition of the same board area of the radio frequency front-end chip. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other aspects of the utility model will become more apparent and more easily understood by the following detailed description in conjunction with the accompanying drawings. In the drawings:

[0030] Figure 1 A schematic diagram of a module of an electrostatic protection circuit provided in an embodiment of the present utility model;

[0031] Figure 2 This is a circuit schematic diagram of the electrostatic protection circuit provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0033] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] Example 1

[0036] like Figures 1 to 2 As shown, the embodiment of the present invention provides an electrostatic protection circuit 100, which includes multiple levels of clamping circuits and resistors connected in sequence and forming a multi-level stacked structure. Figures 1 to 2 The second FET is marked Q1. Figures 1 to 2 The mark Q2 in the figure has a capacitance of Figures 1 to 2 Mark C in the figure, the driving circuit is Figure 1 Mark 2 in the figure, the third field effect tube is Figures 1 to 2 The diode is marked Q3. Figures 1 to 2 Mark D in the figure, with protection power supply Figures 1 to 2 The mark V in the middle is the ground terminal. Figures 1 to 2GND in the first stage clamping circuit, the fourth field effect transistor is Figure 2 the mark Q4 in the first stage clamping circuit, the fifth field effect transistor is Figure 2 the mark Q5 in the first stage clamping circuit, the sixth field effect transistor is Figure 2 the mark Q6 in the first stage clamping circuit, the seventh field effect transistor is Figure 2 the mark Q7 in the first stage clamping circuit, the eighth field effect transistor is Figure 2 the mark Q8 in the first stage clamping circuit, the ninth field effect transistor is Figure 2 the mark Q9 in the first stage clamping circuit.

[0037] Each stage clamping circuit comprises a first field effect transistor Q1, a second field effect transistor Q2, a capacitor C, a driving circuit 2, a third field effect transistor Q3 and a diode D.

[0038] The gate of the first field effect transistor Q1 is connected to the drain of the first field effect transistor Q1.

[0039] The source of the second field effect transistor Q2 is connected to the drain of the first field effect transistor Q1, and the gate of the second field effect transistor Q2 is connected to the drain of the second field effect transistor Q2.

[0040] The first end of the capacitor C is connected to the drain of the second field effect transistor Q2.

[0041] The input end of the driving circuit 2 is connected to the second end of the capacitor C, and the first voltage connection end of the driving circuit 2 is connected to the first end of the capacitor C.

[0042] The gate of the third field effect transistor Q3 is connected to the output end of the driving circuit 2; the driving circuit 2 is used for controlling the opening or closing of the first field effect transistor Q1, the second field effect transistor Q2 and the third field effect transistor Q3.

[0043] The source of the first field effect transistor Q1 in the first stage clamping circuit is used for being connected to the power supply to be protected, the second voltage connection end of the driving circuit 2 in the first stage clamping circuit is used for being connected to the power supply to be protected, the drain of the third field effect transistor Q3 in the first stage clamping circuit is used for being connected to the power supply to be protected, and the negative electrode of the diode D in the first stage clamping circuit is used for being connected to the power supply to be protected.

[0044] The source of the first field effect transistor Q1 in the next stage clamping circuit is connected to the drain of the second field effect transistor Q2 in the previous stage clamping circuit, the second end of the capacitor C in the next stage clamping circuit is connected to the first end of the capacitor C in the previous stage clamping circuit, the second voltage connection end of the driving circuit 2 in the next stage clamping circuit is connected to the output end of the driving circuit 2 in the previous stage clamping circuit, the drain of the third field effect transistor Q3 in the next stage clamping circuit is connected to the source of the third field effect transistor Q3 in the previous stage clamping circuit, and the negative electrode of the diode D in the next stage clamping circuit is connected to the positive electrode of the diode D in the previous stage clamping circuit.

[0045] The drain of the second FET Q2 , the source of the third FET Q3 , and the anode of the diode D in the last-stage clamping circuit are all grounded to GND.

[0046] A first end of the resistor R is connected to the power supply to be protected, and a second end of the resistor R is connected to a second end of the capacitor C in the first-stage clamping circuit.

[0047] The driving circuit 2 includes a fourth field effect transistor Q4, a fifth field effect transistor Q5, a sixth field effect transistor Q6, a seventh field effect transistor Q7, an eighth field effect transistor Q8 and a ninth field effect transistor Q9;

[0048] The gate of the fourth field effect transistor Q4 and the gate of the fifth field effect transistor Q5 are connected and serve as the input terminal of the driving circuit 2. The drain of the fourth field effect transistor Q4 is connected to the drain of the fifth field effect transistor Q5.

[0049] The drain of the fourth field effect transistor Q4, the drain of the fifth field effect transistor Q5, the gate of the sixth field effect transistor Q6 and the gate of the seventh field effect transistor Q7 are connected to each other;

[0050] The drain of the sixth field effect transistor Q6 is connected to the drain of the seventh field effect transistor Q7;

[0051] The drain of the sixth field effect transistor Q6, the drain of the seventh field effect transistor Q7, the gate of the eighth field effect transistor Q8 and the gate of the ninth field effect transistor Q9 are connected to each other;

[0052] The drain of the eighth field effect transistor Q8 is connected to the drain of the ninth field effect transistor Q9 and serves as the output terminal of the driving circuit 2.

[0053] The source of the fifth field effect transistor Q5, the source of the seventh field effect transistor Q7, and the source of the ninth field effect transistor Q9 are interconnected and collectively serve as the first voltage connection terminal of the drive circuit 2. The source of the fourth field effect transistor Q4, the source of the sixth field effect transistor Q6, and the source of the eighth field effect transistor Q8 are interconnected and collectively serve as the second voltage connection terminal of the drive circuit 2.

[0054] The first FET Q1, the second FET Q2, the fourth FET Q4, the sixth FET Q6 and the eighth FET Q8 are all P-type FETs or PMOS transistors; and the first FET Q1 and the second FET Q2 in each stacked assembly have the same characteristics.

[0055] The third FET Q3 , the fifth FET Q5 , the seventh FET Q7 and the ninth FET Q9 are all N-type FETs or NMOS transistors.

[0056] The above grounding is all connected to the ground terminal GND of the RF front-end chip.

[0057] Please continue to participateFigures 1 to 2 As shown in the figure, the embedding circuit in the embodiment is explained by taking three stages as an example, which are the first stage embedding circuit 11, the second stage embedding circuit 12 and the third stage embedding circuit 13, and which are used to satisfy the anti-static discharge of the power supply to be protected with a working voltage of 3.3-4.3V, which is referred to as power supply for short. Of course, in order to satisfy the anti-static discharge requirement of the power supply with different working voltages, the number of stages of the embedding circuit can also be designed as other numbers.

[0058] The on-resistance of the N-type field effect tube in the embedding circuit is calculated by the following formula:

[0059] Ron=1 / (u*Cox*(W / L)*(Vgs-Vth));

[0060] Wherein, Ron is the on-resistance of the N-type field effect tube, Vgs is the voltage difference between the gate voltage and the source voltage of the N-type field effect tube, Vth is the threshold voltage of the on-resistance, u is the electron mobility, Cox is the unit area gate oxide capacitance, W is the width of the N-type field effect tube, and L is the length of the N-type field effect tube.

[0061] As can be seen from the above calculation formula, the greater the voltage difference between the gate voltage and the source voltage of the N-type field effect tube, the smaller the on-resistance between the drain and the source of the N-type field effect tube.

[0062] It is assumed that the working voltage of the power supply in the first stage embedding circuit 11 is V0, and it is assumed that the voltage of the connection point between the source of the first field effect tube Q1 in the second stage embedding circuit 12 and the drain of the second field effect tube Q2 in the first stage embedding circuit 11 is V1, and it is assumed that the voltage of the connection point between the source of the first field effect tube Q1 in the third stage embedding circuit 13 and the drain of the second field effect tube Q2 in the second stage embedding circuit 12 is V2, then the following conditions are satisfied: Figure 1 Figure 2 Figure 2 Figure 1 Figure 2

[0063] V1=2*V0 / 3; V2=2*V0 / 3.

[0064] The first resistor R, the capacitor C in the first stage embedding circuit 11, the capacitor C in the second stage embedding circuit 12 and the capacitor C in the third stage embedding circuit 13 are connected in series to form a fast response network (impulse circuit).

[0065] It is assumed that the resistance value of the first resistor R is r, the capacitance value of the capacitor C in the first stage embedding circuit 11 is c1, the capacitance value of the capacitor C in the second stage embedding circuit 12 is c2, and the capacitance value of the capacitor C in the third stage embedding circuit 13 is c3. For the convenience of calculation, c1, c2 and c3 satisfy the following conditions:

[0066] ​​​​​c1 = c2 = c3 = c;

[0067] Then, τ = r * c4 = r * c / 3;

[0068] Wherein, τ is discharge constant, c4 is series equivalent capacitance value of c1, c2, c3; if r takes hundreds of K, such as 500K ohm, c takes pF, such as 2pF, τ is 0.33us.

[0069] In the normal working mode of the radio frequency front-end chip, the working voltage of the power supply to be protected is stable, and the capacitors C in the first embedded position circuit 11, the capacitors C in the second embedded position circuit 12 and the capacitors C in the third embedded position circuit 13 are all cut off.

[0070] The voltage of the connection point of the second voltage connection end of the driving circuit 2 in the second embedded position circuit 12 and the output end of the driving circuit 2 in the first embedded position circuit 11 is set as V3, the voltage of the connection point of the second voltage connection end of the driving circuit 2 in the third embedded position circuit 13 and the output end of the driving circuit 2 in the second embedded position circuit 12 is set as V4, and the voltage of the output end of the driving circuit 2 in the third embedded position circuit 13 is set as V5, then the following conditions are met:

[0071] The fourth field effect tube Q4 in the first embedded position circuit 11 is cut off, the fifth field effect tube Q5 is turned on, the sixth field effect tube Q6 is turned on, the seventh field effect tube Q7 is cut off, the eighth field effect tube Q8 is cut off, and the ninth field effect tube Q9 is turned on, and at the same time, V3 = 2 * V0 / 3.

[0072] The fourth field effect tube Q4 in the second embedded position circuit is cut off, the fifth field effect tube Q5 is turned on, the sixth field effect tube Q6 is turned on, the seventh field effect tube Q7 is cut off, the eighth field effect tube Q8 is cut off, and the ninth field effect tube Q9 is turned on, and at the same time, V4 = V3 / 3.

[0073] The fourth field effect tube Q4 in the third embedded position circuit is cut off, the fifth field effect tube Q5 is turned on, the sixth field effect tube Q6 is turned on, the seventh field effect tube Q7 is cut off, the eighth field effect tube Q8 is cut off, and the ninth field effect tube Q9 is turned on, and at the same time, V5 = 0.

[0074] Therefore, in the normal working mode of the radio frequency front-end chip, the third field effect tube Q3 in the first embedded position circuit 11, the third field effect tube Q3 in the second embedded position circuit 12 and the third field effect tube Q3 in the third embedded position circuit 13 are all cut off.

[0075] When the working voltage of the power supply appears electrostatic pulse, because the pulse time of the electrostatic discharge is very short, the frequency spectrum characteristic has very strong high frequency component, and the typical value is several hundred Mhz, so the capacitances C in the first stage clamp circuit 11, the capacitances C in the second stage clamp circuit 12 and the capacitances C in the third stage clamp circuit 13 have low resistance to the electrostatic discharge pulse.

[0076] At this time, the voltage of the connection point of the output terminal of the driving circuit 2 in the first stage clamp circuit 11 and the capacitance C is set as V6, and the following condition is satisfied:

[0077] V6, V1 and V2 are all low level.

[0078] Therefore, the third field effect transistor Q3, the fourth field effect transistor Q4, the seventh field effect transistor Q7 and the eighth field effect transistor Q8 in each stage clamp circuit are all turned on, and the fifth field effect transistor Q5, the sixth field effect transistor Q6 and the ninth field effect transistor Q9 in each stage clamp circuit are all turned off.

[0079] The low resistance loop is formed between the working voltage of the power supply and the ground through the third field effect transistor Q3 in the first stage clamp circuit 11, the third field effect transistor Q3 in the second stage clamp circuit 12 and the third field effect transistor Q3 in the third stage clamp circuit 13.

[0080] The electrostatic positive pulse is discharged to the ground through the third field effect transistor Q3 in the first stage clamp circuit 11, the third field effect transistor Q3 in the second stage clamp circuit 12 and the third field effect transistor Q3 in the third stage clamp circuit 13, so as to achieve the purpose of protecting the circuit.

[0081] When the electrostatic discharge ends, the third field effect transistor Q3 in the first stage clamp circuit 11, the third field effect transistor Q3 in the second stage clamp circuit 12 and the third field effect transistor Q3 in the third stage clamp circuit 13 return to the high resistance state, so that the circuit can work normally.

[0082] When the working voltage of the power supply appears negative pulse, the diode D in the first stage clamp circuit 11, the diode D in the second stage clamp circuit 12 and the diode D in the third stage clamp circuit 13 are turned on, and the electrostatic pulse is discharged to the ground through the diode D in the first stage clamp circuit 11, the diode D in the second stage clamp circuit 12 and the diode D in the third stage clamp circuit 13.

[0083] Compared with the prior art, the electrostatic protection circuit 100 in the embodiment can improve the discharge capacity of the electrostatic protection circuit 100, shorten the opening time of the trigger circuit, and enhance the anti-electrostatic discharge effect, under the condition of the same board area of the radio frequency front-end chip, by designing the embedding circuit containing the first field effect tube Q1, the second field effect tube Q2, the capacitor C, the driving circuit 2, the third field effect tube Q3, and the diode D, and additionally adding the resistor R.

[0084] Embodiment two

[0085] The radio frequency front-end chip in the embodiment contains the electrostatic protection circuit 100 in the embodiment one, and thus can achieve the technical effects achieved by the electrostatic protection circuit 100 in the embodiment one, which will not be repeated here.

[0086] It should be noted that the various embodiments described above with reference to the drawings are only used to illustrate the present application and not to limit the scope of the present application, and those skilled in the art should understand that the modifications or equivalent replacements made to the present application without departing from the spirit and scope of the present application should be covered within the scope of the present application. In addition, unless the context indicates otherwise, the word in singular form includes the word in plural form, and vice versa. In addition, unless specifically stated, all or part of any embodiment can be used in combination with all or part of any other embodiment.

Claims

1. An electrostatic discharge protection circuit, characterized by, The electrostatic protection circuit comprises a plurality of levels of embedding circuits connected in sequence and stacked in a multi-level structure, and a resistor; Each level of the embedding circuit comprises a first field effect transistor, a second field effect transistor, a capacitor, a driving circuit, a third field effect transistor, and a diode; The gate of the first field effect transistor is connected to the drain of the first field effect transistor; The source of the second field effect transistor is connected to the drain of the first field effect transistor, and the gate of the second field effect transistor is connected to the drain of the second field effect transistor; The first end of the capacitor is connected to the drain of the second field effect transistor; The input end of the driving circuit is connected to the second end of the capacitor, and the first voltage connection end of the driving circuit is connected to the first end of the capacitor; The gate of the third field effect transistor is connected to the output end of the driving circuit; The driving circuit is used to control the opening or closing of the first field effect transistor, the second field effect transistor, and the third field effect transistor; The source of the first field effect transistor in the first level of the embedding circuit is used to be connected to a power source to be protected, the second voltage connection end of the driving circuit in the first level of the embedding circuit is used to be connected to the power source to be protected, the drain of the third field effect transistor in the first level of the embedding circuit is used to be connected to the power source to be protected, and the negative electrode of the diode in the first level of the embedding circuit is used to be connected to the power source to be protected; The source of the first field effect transistor in the next level of the embedding circuit is connected to the drain of the second field effect transistor in the previous level of the embedding circuit, the second end of the capacitor in the next level of the embedding circuit is connected to the first end of the capacitor in the previous level of the embedding circuit, the second voltage connection end of the driving circuit in the next level of the embedding circuit is connected to the output end of the driving circuit in the previous level of the embedding circuit, the drain of the third field effect transistor in the next level of the embedding circuit is connected to the source of the third field effect transistor in the previous level of the embedding circuit, and the negative electrode of the diode in the next level of the embedding circuit is connected to the positive electrode of the diode in the previous level of the embedding circuit; The drain of the second field effect transistor, the source of the third field effect transistor, and the positive electrode of the diode in the last level of the embedding circuit are all grounded; The first end of the resistor is connected to the power source to be protected, and the second end of the resistor is connected to the second end of the capacitor in the first level of the embedding circuit.

2. The electrostatic discharge circuit of claim 1, wherein, The driving circuit comprises a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, and a ninth field effect transistor; The gate of the fourth field effect transistor and the gate of the fifth field effect transistor are connected and serve as the input end of the driving circuit, and the drain of the fourth field effect transistor is connected to the drain of the fifth field effect transistor; The drain of the fourth field effect transistor, the drain of the fifth field effect transistor, the gate of the sixth field effect transistor, and the gate of the seventh field effect transistor are connected to each other; The drain of the sixth field effect transistor is connected to the drain of the seventh field effect transistor; a drain of the sixth field effect transistor, a drain of the seventh field effect transistor, a gate of the eighth field effect transistor and a gate of the ninth field effect transistor are connected with each other; a drain of the eighth field effect transistor and a drain of the ninth field effect transistor are connected and serve as an output terminal of the driving circuit; a source of the fifth field effect transistor, a source of the seventh field effect transistor and a source of the ninth field effect transistor are connected with each other and serve as a first voltage connection terminal of the driving circuit, and a source of the fourth field effect transistor, a source of the sixth field effect transistor and a source of the eighth field effect transistor are connected with each other and serve as a second voltage connection terminal of the driving circuit.

3. The electrostatic discharge protection circuit of claim 2, wherein, The first field effect transistor, the second field effect transistor, the fourth field effect transistor, the sixth field effect transistor and the eighth field effect transistor are all P-type field effect transistors.

4. The electrostatic discharge protection circuit of claim 3, wherein, The third field effect transistor, the fifth field effect transistor, the seventh field effect transistor and the ninth field effect transistor are all N-type field effect transistors.

5. A radio frequency front-end chip, characterized by The radio frequency front-end chip comprises the electrostatic protection circuit according to any one of claims 1 to 4.

Images