Charging circuit capable of automatically balancing bus level
By adopting a new bidirectional DC-DC topology in energy storage inverters, off-grid inverters, and grid-connected inverters, and utilizing the design of coupled inductors and transformers, automatic bus voltage balancing is achieved, solving the voltage imbalance problem of traditional interleaved LLC circuits under load changes or no-load conditions, and realizing a simple and low-cost voltage balancing effect.
Patent Information
- Application Number
- CN202422757957.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2034-11-13
AI Technical Summary
Existing technologies struggle to effectively and automatically balance bus voltage when load changes or when there is no load, especially in energy storage inverters, off-grid inverters, and grid-connected inverters. Traditional interleaved LLC circuits are not ideal when there is no load or light load.
A novel bidirectional DC-DC topology is adopted. By designing coupled inductors and transformers and utilizing the synchronous and complementary control of switching transistors, automatic bus voltage balancing is achieved, avoiding the need for additional control circuitry.
Regardless of load size or no-load conditions, it can automatically and effectively balance the bus voltage. The topology is simple, the cost is low, and no additional control circuitry is required.
Smart Images
Figure CN223472061U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a circuit technical field especially relates to a charging circuit of automatic equalization bus level. BACKGROUND
[0002] In the application of energy storage inverter, off-grid inverter and parallel and off-grid inverter, there is usually photovoltaic and battery charging and discharging application. The mains supplies power to the battery or is used for load, and the PFC circuit of the preceding stage usually adopts the structure of three-phase six switches. In this structure, the PFC output needs two capacitors in series to provide a single bus voltage (such as 800V). But sometimes ±400V bus needs to be provided, and the following load will be connected to the positive and negative buses respectively. The usual way is to use the upper and lower interleaved LLC in parallel in the following stage, and the bus capacitor voltage balance is realized by the competition of the two LLC circuits. But this scheme is only effective when there is load, and when there is no load or the load is light, the effect is not ideal.
[0003] Therefore, it is necessary to provide a charging circuit for automatically balancing bus level, which can automatically and effectively balance the bus voltage whether the load is large or even when the output is empty, without the need for additional control circuit. UTILITY MODEL CONTENT
[0004] The utility model discloses a charging circuit of automatic equalization bus level relates to the field of power electronics, and is widely used in the field such as energy storage inverter, off-grid inverter and parallel and off-grid inverter, and it can effectively solve the technical problem involved in the background art.
[0005] To achieve the above object, the technical scheme of the utility model is:
[0006] A charging circuit for automatically balancing the bus level, comprising a port VA, a port VB and a port VC, one end of an inductor L3 is connected to the port VA, the other end of the inductor L3 is connected to the pin 1 of a switch tube Q4 and the pin 2 of a switch tube Q7, one end of an inductor L4 is connected to the port VB, the other end of the inductor L4 is connected to the pin 1 of a switch tube Q5 and the pin 2 of a switch tube Q8, one end of an inductor L5 is connected to the port VC, the other end of the inductor L5 is connected to the pin 1 of a switch tube Q6 and the pin 2 of a switch tube Q9, the pin 2 of the switch tube Q4 is connected to the pin 2 of the switch tube Q5, the pin 2 of the switch tube Q6, a port VBUS+, one end of a capacitor C1 and one end of an inductor L1, the other end of the inductor L1 is connected to the pin 2 of a switch tube Q1 and one end of a capacitor C3, the other end of the capacitor C3 is connected to the pin 1 of a transformer T1, the other end of the capacitor C1 is connected to one end of a capacitor C2, the pin 1 of the switch tube Q1, the pin 2 of a switch tube Q2, the pin 2 of the transformer T1 and the pin 3 of the transformer T1, the pin 1 of the switch tube Q7 is connected to the pin 1 of the switch tube Q8, the pin 1 of the switch tube Q9, the other end of the capacitor C2, a port VBUS- and one end of an inductor L2, the other end of the inductor L2 is connected to the pin 1 of the switch tube Q2 and one end of a capacitor C4, the other end of the capacitor C4 is connected to the pin 4 of the transformer T1, the pin 5 of the transformer T1 is connected to the pin 2 of a switch tube Q3, the pin 1 of the switch tube Q3 is connected to one end of a capacitor C5, the pin 6 of the transformer T1 is connected to the other end of the capacitor C5 and a port VBAT.
[0007] As a preferred improvement of the utility model: the port VA, the port VB and the port VC connect three-phase power supply network.
[0008] As a preferred improvement of the utility model: the switch tube Q1, the switch tube Q2, the switch tube Q3, the switch tube Q4, the switch tube Q5, the switch tube Q6, the switch tube Q7, the switch tube Q8 and the switch tube Q9 are MOS tubes, the pin 1 is the source, and the pin 2 is the drain.
[0009] As a preferred improvement of the utility model: the inductor L1 and the inductor L2 are coupled.
[0010] As a preferred improvement of the utility model: the other end of the capacitor C1 is connected to a port GND.
[0011] As a preferred improvement of the present utility model: the charging circuit also includes load 1 connection port 1, load 1 connection port 2, load 2 connection port 1 and load 2 connection port 2, the load 1 connection port 1 is connected to one end of the inductor L1, the load 1 connection port 2 is connected to port GND, the load 2 connection port 1 is connected to one end of the inductor L2, and the load 2 connection port 2 is connected to port GND.
[0012] As a preferred improvement of the present invention: one end of the capacitor C5 is connected to the port AGND.
[0013] As a preferred improvement of the present invention: the port VBAT is connected to a battery.
[0014] The beneficial effects of the utility model are as follows:
[0015] A new bidirectional DCDC topology is proposed to replace the original interleaved LLC circuit. Regardless of the load size, even when the output is unloaded, it can automatically and effectively balance the bus voltage. No additional control circuit is required, the topology is simple, and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. Among them:
[0017] Figure 1 This is a schematic diagram of a charging circuit for automatically balancing bus levels according to the present invention. DETAILED DESCRIPTION
[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0019] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0020] In addition, the descriptions in the present application such as "first", "second" and the like are merely intended for differentiation rather than indicating or implying their relative importance or implying the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise explicitly and specifically defined.
[0021] In the present application, unless otherwise explicitly defined and limited, the terms "connection", "fixing" and the like should be understood in a broad sense, for example, "fixing" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium; can be internal connection of two elements or interaction relationship between two elements, unless otherwise explicitly defined. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0022] In addition, the technical solutions of various embodiments of the present application can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor is it within the protection scope required by the present application.
[0023] Please refer to Figure 1The utility model provides a kind of charging circuit of automatic equalization bus level, including port VA, port VB and port VC, one end of the inductor L3 is connected to the port VA, the other end of the inductor L3 is connected to the pin 1 of switch tube Q4 and the pin 2 of switch tube Q7, one end of the inductor L4 is connected to the port VB, the other end of the inductor L4 is connected to the pin 1 of switch tube Q5 and the pin 2 of switch tube Q8, one end of the inductor L5 is connected to the port VC, the other end of the inductor L5 is connected to the pin 1 of switch tube Q6 and the pin 2 of switch tube Q9, the pin 2 of the switch tube Q4 is connected to the pin 2 of the switch tube Q5, the pin 2 of the switch tube Q6, port BUSThe pin 2 of switch tube Q7, the pin 1 of capacitor C1 and the pin 1 of inductor L1, the other end of the inductor L1 is connected to the pin 2 of switch tube Q1 and the pin 1 of capacitor C3, the other end of the capacitor C3 is connected to the pin 1 of transformer T1, the other end of the capacitor C1 is connected to the pin 1 of capacitor C2, the pin 1 of switch tube Q1, the pin 2 of switch tube Q2, the pin 2 of the transformer T1 and the pin 3 of the transformer T1, the pin 1 of the switch tube Q7 is connected to the pin 1 of the switch tube Q8, the pin 1 of the switch tube Q9, the other end of the capacitor C2, port BUSThe pin 1 of inductor L2, the other end of the inductor L2 is connected to the pin 1 of the switch tube Q2 and the pin 1 of capacitor C4, the other end of the capacitor C4 is connected to the pin 4 of the transformer T1, the pin 2 of the switch tube Q3 is connected to the pin 5 of the transformer T1, the pin 1 of the switch tube Q3 is connected to the pin 1 of capacitor C5, the pin 6 of the transformer T1 is connected to the other end of the capacitor C5 and port VBAT.The pin 1 of the transformer T1 and the pin 2 of the transformer T1 share a coil, the pin 3 of the transformer T1 and the pin 4 of the transformer T1 share a coil, the pin 5 of the transformer T1 and the pin 6 of the transformer T1 share a coil.The port VA, the port VB and the port VC connect three-phase power supply network, the switch tube Q1, the switch tube Q2, the switch tube Q3, the switch tube Q4, the switch tube Q5, the switch tube Q6, the switch tube Q7, the switch tube Q8 and the switch tube Q9 are MOS tube, pin 1 is source, pin 2 is drain, pin 3 is gate, connect controller.The inductor L1 and the inductor L2 are coupled, equivalent to the two coils of coupled inductor, the other end of the capacitor C1 is connected to port GND.The pin 1 of the capacitor C5 is connected to port AGND, port VBAT is connected to battery positive end, and battery negative end is connected to port AGND.The charging circuit further includes load one connection port one, load one connection port two, load two connection port one and load two connection port two, one end of the inductor L1 is connected to the load one connection port one, port GND is connected to the load one connection port two, one end of the inductor L2 is connected to the load two connection port one, and port GND is connected to the load two connection port two.VBUS is an output port, two, one is positive voltage, one is negative voltage. Output equivalent to 3, one positive, one negative, one ground, load interface positive port, the voltage is Vbus+, interface negative port, is Vbus-, the total output voltage Vbus+ Vbus-, generally two voltage balance, that is 2 times Vbus. Load can be selected in many kinds, DCDC, inverter can. Need to be further explained is that other components are used to achieve the above effects, should be within the inventive concept of the utility model, and should be within the protection scope of the utility model.
[0024] Working principle:
[0025] 1, the left side is a three-phase six-switch rectifier, which converts output three-phase alternating current into direct current. Usually, there are two capacitors in series on the output side, and sometimes positive and negative voltages are obtained, and there are two loads (Load1 / Load2 in the figure) on the capacitors.
[0026] 2, Q1 / Q2 synchronous switch, Q3 and Q1 / Q2 complementary switch.
[0027] When Q1 / Q2 is turned on, Q3 is turned off, and inductor L1 stores energy through Q1 / Q2. Transformer T1 and capacitor C2 / C4 reset.
[0028] 3, when Q1 / Q2 is turned off, Q3 is turned on. The energy of inductor L1 is transmitted to the battery side through capacitors C3 / C4 and transformer.
[0029] Q1 and Q2 are controlled by the same group of drivers. When there is a load on the output, because they are coupled through the same transformer, the secondary side is also connected together. When the voltages of the two capacitors on the bus are not equal, the energy of the upper capacitor will be transmitted to the secondary side first, automatically balancing the bus voltage.
[0030] When there is no load on the output, the traditional LLC circuit cannot balance the bus capacitors. However, in this circuit, Q3 is shared, so even if there is no load on the secondary output, the energy of the capacitor on the high side will be transmitted to the secondary side through the transformer, and then transmitted back to the low side of the bus capacitor on the primary side, completing the voltage balance of the two capacitors on the bus.
[0031] The topology is simple and low in cost, and can replace the traditional interleaved LLC circuit. Regardless of the size of the load, even under no load conditions, it can still effectively balance the capacitor voltage. Even if the upper and lower capacitors on the bus are connected to different loads, the voltage of the two capacitors can still be balanced. The inductors in the figure are coupled inductors, and the inductors can also work normally without coupling. The example power switch in the figure is a MOSFET, and other power switches can also achieve the function of the circuit.
[0032] Although the embodiments of the present application have been disclosed as above, it is not limited to the application listed in the specification and the embodiments, and it can be applied to various fields suitable for the present application. For those skilled in the art, other modifications can be easily realized, and therefore the present application is not limited to specific details and the figures shown and described herein.
Claims
1. A charging circuit for automatically equalizing bus levels, characterized by: The port VA is connected to one end of the inductor L3, the other end of the inductor L3 is connected to the pin 1 of the switch tube Q4 and the pin 2 of the switch tube Q7, the port VB is connected to one end of the inductor L4, the other end of the inductor L4 is connected to the pin 1 of the switch tube Q5 and the pin 2 of the switch tube Q8, the port VC is connected to one end of the inductor L5, the other end of the inductor L5 is connected to the pin 1 of the switch tube Q6 and the pin 2 of the switch tube Q9, the pin 2 of the switch tube Q4 is connected to the pin 2 of the switch tube Q5, the pin 2 of the switch tube Q6, the port VBUS+, one end of the capacitor C1 and one end of the inductor L1, the other end of the inductor L1 is connected to the pin 2 of the switch tube Q1 and one end of the capacitor C3, the other end of the capacitor C3 is connected to the pin 1 of the transformer T1, the other end of the capacitor C1 is connected to one end of the capacitor C2, the pin 1 of the switch tube Q1, the pin 2 of the switch tube Q2, the pin 2 of the transformer T1 and the pin 3 of the transformer T1, the pin 1 of the switch tube Q7 is connected to the pin 1 of the switch tube Q8, the pin 1 of the switch tube Q9, the other end of the capacitor C2, the port VBUS- and one end of the inductor L2, the other end of the inductor L2 is connected to the pin 1 of the switch tube Q2 and one end of the capacitor C4, the other end of the capacitor C4 is connected to the pin 4 of the transformer T1, the pin 5 of the transformer T1 is connected to the pin 2 of the switch tube Q3, the pin 1 of the switch tube Q3 is connected to one end of the capacitor C5, the pin 6 of the transformer T1 is connected to the other end of the capacitor C5 and the port VBAT.
2. A charging circuit for automatically equalizing bus levels as claimed in claim 1, characterized in that: The port VA, the port VB and the port VC are connected to a three-phase power supply network.
3. A charging circuit for automatically equalizing bus levels as recited in claim 1, wherein: The switch tube Q1, the switch tube Q2, the switch tube Q3, the switch tube Q4, the switch tube Q5, the switch tube Q6, the switch tube Q7, the switch tube Q8 and the switch tube Q9 are MOS tubes, the pin 1 is a source electrode and the pin 2 is a drain electrode.
4. The charge circuit for automatically equalizing the bus level according to claim 1, wherein: The inductor L1 and the inductor L2 are coupled.
5. The charge circuit for automatically equalizing the bus level according to claim 1, wherein: The other end of the capacitor C1 is connected to the port GND.
6. A charge circuit for automatically equalizing bus levels as claimed in claim 5, characterized in that: The charging circuit further comprises a load one connection port one, a load one connection port two, a load two connection port one and a load two connection port two, the load one connection port one is connected to one end of the inductor L1, the load one connection port two is connected to the port GND, the load two connection port one is connected to one end of the inductor L2, and the load two connection port two is connected to the port GND.
7. A charge circuit for automatically equalizing bus levels as recited in claim 1, wherein: One end of the capacitor C5 is connected to the port AGND.
8. The charge circuit for automatically equalizing the bus level according to claim 1, wherein: The port VBAT is connected to a battery.