Non-volatile static random access memory circuit
By introducing IGZO-TFT transistors and 2T0C-DRAM into 4T-SRAM and using DRAM for data backup and recovery, the problems of volatility in 6T-SRAM and leakage current in 4T-SRAM are solved, achieving stability and high-density integration of near-nonvolatile memory.
Patent Information
- Application Number
- CN202422691302.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-11-05
AI Technical Summary
Existing 6T-SRAM is volatile, causing data loss when power is off, and 4T-SRAM suffers from leakage current and transistor state switching issues, affecting high-density integration and data stability.
It employs 4T-SRAM, a first 2T0C-DRAM, a second 2T0C-DRAM, a first IGZO-TFT transistor, and a second IGZO-TFT transistor. By utilizing the high threshold voltage and periodic storage mechanism of the IGZO-TFT transistor, it uses DRAM for data backup and recovery, thereby achieving non-volatile storage.
It enables data recovery after power failure, reduces leakage current and static power consumption, and improves the stability and high-density integration capability of storage cells.
Smart Images
Figure CN223486702U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor memory device technology, and in particular to a non-volatile static random access memory circuit. Background Technology
[0002] 6TB SRAM, as the most common static random access memory, is widely used for data storage and backup, improving system performance, capacity, and flexibility. However, the volatility of 6TB SRAM means that stored data will be lost when power is off. Moreover, because each memory cell in 6TB SRAM requires 6 transistors, the layout area is large, making high-density integration impossible, and increasing the difficulty and cost of transistor manufacturing processes.
[0003] 4T-SRAM can reduce the number of transistors used, thereby reducing the layout area of the memory cell, which is more conducive to high-density integration and saves manufacturing process costs. However, due to leakage current and transistor state switching in 4T-SRAM, the memory cell also needs to rely on the parasitic capacitance or capacitance of the transistor to retain data. This data retention is not stable and is prone to destructive reads, resulting in data loss or errors. Utility Model Content
[0004] Based on the above analysis, the present invention aims to provide a non-volatile static random access memory circuit to solve the problem that data in existing SRAM will be lost after power failure.
[0005] The objective of this utility model is mainly achieved through the following technical solutions:
[0006] Includes: 4T-SRAM, a first 2T0C-DRAM, a second 2T0C-DRAM, a first IGZO-TFT transistor, and a second IGZO-TFT transistor; wherein,
[0007] The source of the first IGZO-TFT transistor is connected to the Q point of the 4T-SRAM, the drain is connected to the source of the read transistor in the first 2T0C-DRAM, and the gate is input with a switch control signal.
[0008] The source of the second IGZO-TFT transistor is connected to the 4T-SRAM. The drain is connected to the source of the read transistor in the second 2T0C-DRAM, and the gate is used to input the switch control signal.
[0009] The drain connection of the write transistor in the first 2T0C-DRAM is at point Q; the drain connection of the write transistor in the second 2T0C-DRAM is... Points; the drain of the read transistor in the first 2T0C-DRAM and the drain of the read transistor in the second 2T0C-DRAM are connected to the power supply; the gate of the write transistor in the first 2T0C-DRAM and the gate of the write transistor in the second 2T0C-DRAM are connected to the clock signal.
[0010] Based on a further improvement of the above scheme, the source of the write transistor in the first 2TOC-DRAM is connected to the gate of its read transistor, and the source of the write transistor in the second 2TOC-DRAM is connected to the gate of its read transistor.
[0011] Based on further improvements to the above scheme, the 4T-SRAM includes a third IGZO-TFT transistor and a fourth IGZO-TFT transistor responsible for driving, and a fifth IGZO-TFT transistor and a sixth IGZO-TFT transistor for controlling read and write.
[0012] Based on a further improvement to the above scheme, the drain of the third IGZO-TFT transistor, the gate of the fourth IGZO-TFT transistor, and the source of the fifth IGZO-TFT transistor are connected to point Q; the drain of the fourth IGZO-TFT transistor, the gate of the third IGZO-TFT transistor, and the source of the sixth IGZO-TFT transistor are connected to... Point; the drain of the fifth IGZO-TFT transistor is connected to the bit line BL of the 4T-SRAM; the drain of the sixth IGZO-TFT transistor is connected to the bit line of the 4T-SRAM. The sources of the third and fourth IGZO-TFT transistors are grounded; the gates of the fifth and sixth IGZO-TFT transistors are connected to the word line WL of the 4T-SRAM.
[0013] Based on a further improvement of the above scheme, the switch control signal is at a high level during data recovery, which is used to turn on the first IGZO-TFT transistor and the second IGZO-TFT transistor.
[0014] Based on the further improvement of the above scheme, both the first IGZO-TFT transistor and the second IGZO-TFT transistor are IGZO-TFT transistors with high threshold voltage, and the threshold voltage is above 0.7V.
[0015] Based on a further improvement of the above scheme, the circuit performs data backup when the clock signal is periodically high.
[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0017] 1. A circuit that uses DRAM to periodically store data in SRAM and restores the stored data to SRAM after power-on is implemented to achieve a non-volatile memory-like circuit.
[0018] 2. The 4T-SRAM, the first 2T0C-DRAM, the second 2T0C-DRAM, the first IGZO-TFT transistor and the second IGZO-TFT transistor in the circuit all adopt IGZO-TFT transistors. IGZO-TFT has higher mobility, lower leakage current, lower static power consumption, lower growth temperature, is compatible with BEOL process, and has excellent uniformity when fabricated in large area.
[0019] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages will become apparent from the description or be learned by practicing this invention. The objectives and other advantages of this invention can be realized and obtained from the details specifically pointed out in the text and accompanying drawings. Attached Figure Description
[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0021] Figure 1 This is a circuit diagram of a non-volatile static random access memory circuit according to an embodiment of the present invention.
[0022] Figure 2 This is a circuit diagram of a 2T0C-DRAM according to an embodiment of the present invention. Detailed Implementation
[0023] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0024] A specific embodiment of this utility model discloses a non-volatile static random access memory circuit, such as... Figure 1 As shown, it includes: 4T-SRAM, a first 2T0C-DRAM, a second 2T0C-DRAM, a first IGZO-TFT transistor, and a second IGZO-TFT transistor; wherein,
[0025] The source of the first IGZO-TFT transistor is connected to the Q point of the 4T-SRAM, the drain is connected to the source of the read transistor in the first 2T0C-DRAM, and the gate is input with a switch control signal.
[0026] The source of the second IGZO-TFT transistor is connected to the 4T-SRAM. The drain is connected to the source of the read transistor in the second 2T0C-DRAM, and the gate is used to input the switch control signal.
[0027] The drain connection of the write transistor in the first 2T0C-DRAM is at point Q; the drain connection of the write transistor in the second 2T0C-DRAM is... Points; the drain of the read transistor in the first 2T0C-DRAM and the drain of the read transistor in the second 2T0C-DRAM are connected to the power supply; the gate of the write transistor in the first 2T0C-DRAM and the gate of the write transistor in the second 2T0C-DRAM are connected to the clock signal.
[0028] Among them, the switch control signal Manual-Recover is used to control the on / off state of the first IGZO-TFT transistor and the second IGZO-TFT transistor; V store This is a clock signal.
[0029] It should be noted that, as Figure 2 As shown, the 2T0C-DRAM includes a write transistor and a read transistor, wherein the source of the write transistor controls the on and off states of the read transistor; T W This indicates the write transistor of the 2T0C-DRAM, T R This indicates the read transistor of the 2T0C-DRAM, SN indicates the parasitic capacitance of the 2T0C-DRAM, and WWL indicates the write word line used to control T. W The WBL line is used to transmit the written data signal, and the RWL line is used to control the T bit. R The RBL indicates that the read bit line is used to transmit data signals read from the memory cell. In the first 2TOC-DRAM, the source of the write transistor is connected to the gate of its read transistor, and in the second 2TOC-DRAM, the source of the write transistor is connected to the gate of its read transistor.
[0030] It should be noted that the 4T-SRAM includes a third IGZO-TFT transistor and a fourth IGZO-TFT transistor responsible for driving, and a fifth IGZO-TFT transistor and a sixth IGZO-TFT transistor for controlling read and write.
[0031] Wherein, the drain of the third IGZO-TFT transistor, the gate of the fourth IGZO-TFT transistor, and the source of the fifth IGZO-TFT transistor are connected to point Q; the drain of the fourth IGZO-TFT transistor, the gate of the third IGZO-TFT transistor, and the source of the sixth IGZO-TFT transistor are connected to... Point; the drain of the fifth IGZO-TFT transistor is connected to the bit line BL of the 4T-SRAM; the drain of the sixth IGZO-TFT transistor is connected to the bit line of the 4T-SRAM. The sources of the third and fourth IGZO-TFT transistors are grounded; the gates of the fifth and sixth IGZO-TFT transistors are connected to the word line WL of the 4T-SRAM.
[0032] It should be noted that the switch control signal is high only during data recovery, used to turn on the first IGZO-TFT transistor and the second IGZO-TFT transistor. At this time, the read transistor in the 2T0C-DRAM is connected to the Q point of the 4T-SRAM or... Point; the switch control signal is at a low level when reading, writing, holding, and backing up data, and the read transistor in the 2T0C-DRAM does not participate in the operation at this time.
[0033] It should be noted that both the first IGZO-TFT transistor and the second IGZO-TFT transistor are high threshold voltage IGZO-TFT transistors, with the threshold voltage being above 0.7V; using high threshold voltage IGZO-TFT transistors can reduce leakage current and static power consumption.
[0034] Specifically, the data retention operation of the circuit in this embodiment includes:
[0035] Set the word line WL of the 4T-SRAM to low and the switch signal to low. For example, point Q stores a "1". When the Q-point is stored as "0", the fifth IGZO-TFT transistor in the 4T-SRAM is turned off. The third and fifth IGZO-TFT transistors have leakage power consumption. Therefore, the Q-point is unstable as a dynamic storage node; the data needs to be backed up in DRAM.
[0036] During data backup, the power supply VDD is high, the manual-recover switch signal is low, and the clock signal V... STORE Backup is performed when the level is high; Q point and The data at each point is stored in the parasitic capacitance SN1 of the first 2T0C-DRAM and the parasitic capacitance SN2 of the second 2T0C-DRAM respectively; data backup can be performed regardless of whether the word line WL is high-level write or low-level hold.
[0037] In addition, data recovery includes: setting the word line WL low, setting the switch signal high, and setting the clock signal V... STOREData recovery is performed when the level is low; the data stored in the parasitic capacitance SN1 of the first 2T0C-DRAM and the parasitic capacitance SN2 of the second 2T0C-DRAM are respectively input to point Q and... point.
[0038] It should be noted that when the non-volatile static random access memory experiences a power outage due to human intervention or a power failure, VDD is not powered, and at this time, point Q and Data saved at point Q will be lost when power is lost; before the power outage, point Q and... The data at the last high level of the clock signal will be stored in the first 2T0C-DRAM and the second 2T0C-DRAM respectively. When power is restored, the data will be re-stored in point Q and... Points, so that the data recovery process is not affected by bit line BL or bit line The impact of the data to be written requires setting the word line WL to a low level to turn off the fifth and sixth IGZO-TFT transistors.
[0039] Compared with the prior art, the circuit provided in this embodiment can periodically store data in SRAM using DRAM, and restore the stored data to SRAM after power-on, realizing a circuit with non-volatile storage. The 4T-SRAM, the first 2T0C-DRAM, the second 2T0C-DRAM, the first IGZO-TFT transistor and the second IGZO-TFT transistor in the circuit provided in this embodiment are all IGZO-TFT transistors. IGZO-TFT has the characteristics of higher mobility, lower leakage current, lower static power consumption, lower growth temperature, compatibility with BEOL process, and excellent uniformity when fabricated on a large area.
[0040] This invention does not involve any software improvements. It only requires connecting the various devices with corresponding functions through the connection relationships given in the embodiments of this invention, without involving any program software improvements. The connection methods between the various hardware devices with corresponding functions are all implementable by those skilled in the art using existing technology, and will not be described in detail here.
[0041] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model should be included within the protection scope of the present utility model.
Claims
1. A type of non-volatile static random access memory circuit, comprising: 4T-SRAM, first 2T0C-DRAM, second 2T0C-DRAM, first IGZO-TFT transistor, second IGZO-TFT transistor; wherein, The source of the first IGZO-TFT transistor is connected to the Q point of the 4T-SRAM, the drain is connected to the source of the read transistor in the first 2T0C-DRAM, and the gate is input with a switch control signal. The source of the second IGZO-TFT transistor is connected to the 4T-SRAM. The drain is connected to the source of the read transistor in the second 2T0C-DRAM, and the gate is used to input the switch control signal. The drain connection of the write transistor in the first 2T0C-DRAM is at point Q; the drain connection of the write transistor in the second 2T0C-DRAM is... Points; the drain of the read transistor in the first 2T0C-DRAM and the drain of the read transistor in the second 2T0C-DRAM are connected to the power supply; the gate of the write transistor in the first 2T0C-DRAM and the gate of the write transistor in the second 2T0C-DRAM are connected to the clock signal.
2. The quasi-nonvolatile static random access memory circuit according to claim 1, characterized in that, In the first 2TOC-DRAM, the source of the write transistor is connected to the gate of its read transistor, and in the second 2TOC-DRAM, the source of the write transistor is connected to the gate of its read transistor.
3. The quasi-nonvolatile static random access memory circuit according to claim 2, characterized in that, The 4T-SRAM includes a third and a fourth IGZO-TFT transistor responsible for driving, and a fifth and a sixth IGZO-TFT transistor for controlling read and write operations.
4. The quasi-nonvolatile static random access memory circuit according to claim 3, characterized in that, The drain of the third IGZO-TFT transistor, the gate of the fourth IGZO-TFT transistor, and the source of the fifth IGZO-TFT transistor are connected to point Q; the drain of the fourth IGZO-TFT transistor, the gate of the third IGZO-TFT transistor, and the source of the sixth IGZO-TFT transistor are connected to... Point; the drain of the fifth IGZO-TFT transistor is connected to the bit line BL of the 4T-SRAM; the drain of the sixth IGZO-TFT transistor is connected to the bit line of the 4T-SRAM. The sources of the third and fourth IGZO-TFT transistors are grounded; the gates of the fifth and sixth IGZO-TFT transistors are connected to the word line WL of the 4T-SRAM.
5. The quasi-nonvolatile static random access memory circuit according to claim 4, characterized in that, The switch control signal is high during data recovery, used to turn on the first IGZO-TFT transistor and the second IGZO-TFT transistor.
6. The quasi-nonvolatile static random access memory circuit according to claim 5, characterized in that, Both the first IGZO-TFT transistor and the second IGZO-TFT transistor are high threshold voltage IGZO-TFT transistors, with the threshold voltage being above 0.7V.
7. The quasi-nonvolatile static random access memory circuit according to claim 6, characterized in that, The circuit backs up data when the clock signal is periodically high.