Paster type power hybrid integrated circuit module packaging structure

Abstract

The utility model discloses a surface-mounted power hybrid integrated circuit module packaging structure, and belongs to the technical field of microelectronic device packaging. The packaging structure is packaged by adopting a ceramic shell and a metal assembly; a high-power chip and a low-power chip are integrated in different areas in a packaging cavity of a ceramic shell, the integration areas of the high-power chip and the low-power chip are in a step type, the low-power chip and the high-power chip are sequentially integrated from an upper step to a lower step, and seamless isolation and staggered-layer integration are carried out; the high-power chip is sintered on the heat sink, and the heat sink penetrates through the ceramic shell to realize internal and external electric connection; a TU1 material is used in a key parasitic parameter generation area of the packaging structure and penetrates through the ceramic cavity and the outside, and penetrating type connection is achieved. The surface-mounted high-power chip module packaging structure solves the problems of high parasitic impedance, low heat dissipation efficiency, low product power density, low integration level and large packaging size in the conventional surface-mounted high-power chip module packaging structure. The packaging structure is widely applied to the packaging technology of the power hybrid integrated circuit module.

Description

Technical Field

[0001] This utility model belongs to the field of microelectronic device packaging technology, and more specifically to the field of surface mount hybrid integrated circuit packaging technology. In particular, it relates to a surface mount power hybrid integrated circuit module packaging structure. Background Technology

[0002] With the development of microelectronic device packaging technology, the packaging requirements for integrated circuits are becoming increasingly stringent. In the field of electronic packaging, traditional low-loss, high-power control modules are PCB-level discrete device packages, resulting in large size and low power density. While the technology is currently mature, the development of next-generation power systems, avionics systems, and weapon control systems, especially in the aerospace and defense sectors, necessitates a clear demand for miniaturized, lightweight, low-power, and high-power-density devices. Although individual device packages are small, assembling functional systems still leads to large system size, heavy weight, and low power density. Therefore, to meet the application needs of the industry, there is an urgent need to develop hybrid integrated microcircuit module products.

[0003] Compared to organic plastic packaging, ceramic packaging offers higher mechanical strength, a lower coefficient of thermal expansion, and higher thermal conductivity. These characteristics meet the requirements of high hermeticity and high heat dissipation in chip packaging. Hybrid integrated circuit ceramic packaging is a packaging technology that fixes electronic components onto a ceramic substrate using specific processes and seals them with a ceramic shell. This packaging technology provides higher heat resistance, moisture resistance, corrosion resistance, and electromagnetic interference resistance. It can maintain stable performance at high temperatures without performance degradation due to temperature increases. It has the following characteristics:

[0004] 1. High moisture resistance: It has good waterproof and moisture-proof properties and is suitable for environments with high humidity;

[0005] 2. High corrosion resistance: It has excellent corrosion resistance to chemicals such as acids, alkalis, salts and organic solvents;

[0006] 3. High resistance to electromagnetic interference: It has excellent electromagnetic shielding capabilities and can be used at high frequencies without being affected by electromagnetic interference;

[0007] 4. Excellent electrical performance: Ceramic materials have low resistivity and high insulation performance, which can effectively suppress electromagnetic interference and signal crosstalk;

[0008] 5. Excellent mechanical properties and stability: Ceramic materials have high hardness and impact resistance, which can effectively protect the chip from external physical impacts and damage;

[0009] 6. Good airtightness: Ceramic packaging is an airtight packaging, which can prevent moisture from entering the internal structure and contaminating the chip;

[0010] 7. Low coefficient of thermal expansion: Ceramic materials have a low coefficient of thermal expansion, which is similar to that of chip materials, which helps to improve the reliability of packaging.

[0011] Due to these significant characteristics, ceramic packaging is widely used in various high-performance electronic fields, including aerospace, military equipment, medical devices, high-end communication equipment, and functional electronics. For example, electronic devices operating in extreme temperature and radiation environments require highly reliable and long-term stable communication and navigation systems.

[0012] For ceramic surface-mount packages of high-power driver chips, high reliability and high conversion efficiency are required. Current packaging structures suffer from high parasitic impedance, low heat dissipation efficiency, and low power density, failing to meet the requirements for high integration and miniaturized ceramic packaging.

[0013] In view of the above, this utility model is hereby proposed. Summary of the Invention

[0014] The technical problem to be solved by this utility model is to address the issues of high parasitic impedance, low heat dissipation efficiency, low power density, low integration, and large package size in existing surface-mount high-power chip module packaging structures.

[0015] The inventive concept of this utility model is:

[0016] The packaging structure uses a ceramic shell and metal components for encapsulation. Through precise calculation and design, the ceramic shell and metal components ensure that the entire product is in an optimal state.

[0017] Within the ceramic housing, high-power and low-power chips are integrated in different areas. These integration areas are stepped, with the low-power chip integrated sequentially from the upper step to the lower step. This step-based seamless isolation and staggered integration not only ensures the isolation between chips and reduces parasitic effects, but also significantly improves heat dissipation and integration density.

[0018] High-power integrated circuit chips are directly sintered onto a large heat sink made of tungsten copper. The heat sink material runs through the ceramic shell, achieving internal and external electrical connection, which greatly reduces the parasitic impedance of the product, while maximizing the product's heat dissipation efficiency and increasing the product's power density.

[0019] TU1 material (oxygen-free copper material) is used in the critical parasitic parameter generation areas of the packaging structure, penetrating through the ceramic cavity and the outside to achieve a through-connection, thereby reducing the product's parasitic impedance and inductive reactance and improving product reliability.

[0020] Therefore, a surface-mount power hybrid integrated circuit module packaging structure is provided, such as... Figure 1As shown. Includes:

[0021] 1. Ceramic base body, 2. Inner cavity, 3. Side cavity, 4. Sealing ring, 5. Cover plate, 6. Bottom surface of inner cavity, 7. Metallized layer on bottom surface of inner cavity, 8. Bottom surface of power area of ​​inner cavity, 9. Metallized layer on bottom surface of power area, 10. High-power chip, 11. Plating copper heat sink, 12. Through-type inner electrode, 13. Buried inner electrode, 14. Side electrode, 15. External electrode.

[0022] The ceramic base body 1 is a multi-layer co-fired ceramic.

[0023] The inner cavity 2, the side cavity 3, the bottom surface of the inner cavity 6, the bottom surface of the inner cavity power area 8, the mounting holes of the copper-plated heat sink 11, and the filling holes of the through-type inner electrode 12 are integrally fabricated inside the ceramic base body 1. The bottom surface of the inner cavity 6 is located in the peripheral area of ​​the bottom of the inner cavity of the ceramic base, and the bottom surface of the inner cavity power area 8 is located in the central area of ​​the bottom of the inner cavity of the ceramic base. The bottom surface of the inner cavity 6 is higher than the bottom surface of the inner cavity power area 8.

[0024] The inner cavity bottom surface metallization layer 7 is fabricated on the inner cavity bottom surface 6, and the power region bottom surface metallization layer 9 is fabricated on the inner cavity power region bottom surface 8. The inner cavity bottom surface metallization layer 7 is used for the low-power chip assembly area, bonding area, internal electrode wiring and connection with external electrodes, and the power region bottom surface metallization layer 9 is used for the high-power chip assembly area.

[0025] The copper-plated heat sink 11 is located in the central area of ​​the high-power chip assembly area, penetrating the ceramic base body, and is used for rapid heat dissipation.

[0026] The through-hole of the through-hole inner electrode 12 is located below the metallization layer 7 on the bottom surface of the inner cavity, penetrating the ceramic base body. The through-hole is filled with a metal electrode. The buried inner electrode 13 is located between the ceramic layers of the multilayer co-fired ceramic. The side electrode 14 is located on the side wall of the ceramic base body. The outer electrode 15 is located at the bottom of the ceramic base body. The upper end of the metal through-hole is connected to the metallization layer 7 on the bottom surface of the inner cavity. The inner part of the buried inner electrode 13 is connected to the metallization layer 7 on the bottom surface of the inner cavity, and the outer part is connected to the side electrode 14. The outer electrode 15 is connected to the lower end of the metal through-hole and the lower end of the side electrode 14.

[0027] This invention features excellent insulation performance, high package power density, low parasitic inductance / impedance, ultra-small size, ultra-high integration, ultra-light weight, rapid heat dissipation, high reliability, and wide product coverage. It can be widely used in various products with high reliability requirements, such as semiconductor devices, semiconductor power devices, and hybrid integrated circuits. Compared to existing plastic-packaged products, it offers significant advantages and wider applicability. It has high promotional value for other products with similar form factor requirements. It effectively meets the high reliability and technical requirements of this type of form factor product in scientific research and production, and is widely used in aerospace and other fields. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the ceramic package structure for a multi-channel driver chip.

[0029] Figure 2 A schematic diagram of the planar structure of the metallized region within the ceramic substrate of a seven-channel driver chip package.

[0030] Figure 3 A schematic diagram of the planar structure showing the connection relationship between the inner surface electrodes and the outer electrodes of the ceramic substrate for a seven-channel driver chip.

[0031] Figure 4 This is a top view diagram of the packaged structure of a seven-channel driver chip.

[0032] Figure 5 This is a side view of the package structure of a seven-channel driver chip.

[0033] In the diagram: 1 is the ceramic base body, 2 is the inner cavity, 3 is the side cavity, 4 is the sealing ring, 5 is the cover plate, 6 is the bottom surface of the inner cavity, 7 is the metallization layer on the bottom surface of the inner cavity, 8 is the bottom surface of the power area of ​​the inner cavity, 9 is the metallization layer on the bottom surface of the power area, 10 is the high-power chip, 11 is the copper plating heat sink, 12 is the through-type inner electrode, 13 is the buried inner electrode, 14 is the side electrode, and 15 is the external electrode.

[0034] 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8E, 9M, 7C, 6C, 5C, 4C, 3C, 2C, and 1C are the serial numbers of the inner surface distributed electrodes; B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, and B18 are the serial numbers of the inner surface distributed metallization layers; and P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, and P16 are the serial numbers of the external lead-out electrodes. Detailed Implementation

[0035] like Figure 1-5 As shown, taking a seven-channel driver chip ceramic-metal package as an example, the specific implementation of the surface-mount power hybrid integrated circuit module package structure is as follows:

[0036] The packaging shell base is a square ceramic base. The ceramic body material is more than 95% Al2O3 ceramic (alumina) or AlN ceramic (aluminum nitride).

[0037] The enclosure cover is a square metal cover. The composition is 4J42 or 4J29.

[0038] The outer casing has external dimensions of 10.2mm in length, 6mm in width, and 2.65mm in height (length * width * height), with an internal enclosed cavity volume of 4.5mm. 2 .

[0039] The sealing ring material is 4J42 / 4J29.

[0040] The material for the through-hole copper plating electrode is TU1 (oxygen-free copper).

[0041] The base area layout is as follows: high-power chip area (P area), low-power device (including passive devices) area (K area), and external electrode area (external electrode, B area), such as... Figure 2 As shown.

[0042] The surfaces of the high-power chip area, the low-power device area, and the external electrode area are covered with a metallization layer.

[0043] The inner surface metallization layer distribution is as follows: B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, such as... Figure 2 As shown.

[0044] B17 is the main chip (high-power chip) soldering area, located in the bottom and middle area of ​​the inner cavity (2); B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, and B16 are the low-power chip soldering area and electrode lead or bonding area, located around B17; B18 is the lead transition area that is electrically connected to the soldering area.

[0045] The inner surface metallization layer consists of multiple metal layers. The top layer is a gold layer, the second layer is a nickel, nickel-cobalt, or nickel-phosphorus layer, and the third layer is a tungsten or molybdenum-manganese layer. The top and second layers are electroplated, while the third layer is achieved by first printing a metal paste onto the ceramic and then curing it. The nickel layer thickness ranges from 1.3 to 8.9 μm.

[0046] The inner surface electrode distribution is: 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8E, 9M, 7C, 6C, 5C, 4C, 3C, 2C, 1C, as follows: Figure 3 As shown.

[0047] The outer electrodes on the bottom outer surface are distributed as follows: P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16. The structure of the outer electrodes on the bottom outer surface involves first printing a tungsten layer or a molybdenum-manganese layer in a designated area on the outside, and then welding a metal block onto the tungsten layer or molybdenum-manganese layer, such as... Figure 1 As shown.

[0048] P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, and P16 are used as external leads for user-end soldering, and each lead is 0.5 mm long. The thickness range of each metal layer in the metallization layer on the surface of the external electrode is as follows: the thickness of the top gold layer is 1.3–5.7 μm, with a purity ≥99.9%; the thickness of the second metal layer (nickel, nickel-cobalt, or nickel-phosphorus) is 1.3–8.9 μm; and the thickness of the third metal layer (tungsten or molybdenum-manganese) is 5–30 μm.

[0049] The outer surface of the side electrode is a nickel layer, a nickel-cobalt layer, or a nickel-phosphorus layer, which is plated by electroplating. The thickness of the nickel layer is 1.3 to 8.9 μm, and the bottom layer is a tungsten layer or a molybdenum-manganese layer with a thickness of 5 to 30 μm.

[0050] P1 connects to 1B, P2 connects to 2B, P3 connects to 3B, P4 connects to 4B, P5 connects to 5B, P6 connects to 6B, P7 connects to 7B, P8 connects to 8E, P9 connects to 9M, P10 connects to 7C, P11 connects to 6C, P12 connects to 5C, P13 connects to 4C, P14 connects to 3C, P15 connects to 2C, and P16 connects to 1C. Figure 3 As shown.

[0051] The outer casing sealing ring and the cover plate are connected by parallel seam welding, such as Figure 1 As shown.

[0052] Specifically:

[0053] All chips are silicon-based, with Ag as the back metallization layer, and the maximum chip size is 1mm × 1.2mm × 0.3mm. Furthermore, the structural design achieves at least two layers of staggered packaging, and the chip's heat source is designed separately.

[0054] The bottom of the chip is connected to the inner cavity base using bottom solder, and the solder used for chip sintering is CT285 silver paste.

[0055] The chip mounting requirements are: install the bottom layer solder, install the bottom layer chip on the bottom layer solder, and place a weight block on the bottom layer chip.

[0056] The outer shell sealing ring and the cover plate are connected by parallel seam welding. The outer shell material is ceramic, and the cover plate is a metal cover plate (composition 4J42 or 4J29). The seal between the outer shell and the cover plate is airtight, with an internal moisture content ≤5000ppm and a leakage rate ≤1×10⁻⁶ after sealing. -1 Pa·cm 3 / s.

[0057] The power chip is connected to the inner surface electrode by metal wires. The metal wires are made of gold wire with a diameter of ≥25μm and there are 16 wires in total.

[0058] The application of this invention enables the packaging of high-power-density hybrid integrated microcircuit modules. It significantly improves the power density, application range, and integration of low-loss, high-power controllers. The nano-silver paste and parallel seam welding with multiple temperature gradients provide excellent heat dissipation and highly reliable hermetic sealing, broadening the module's application scenarios.

[0059] The packaging structure of this multi-channel driver chip has advantages such as small size, light weight, high integration, high mechanical strength, stable chemical properties, excellent electrical performance and high reliability, and good space adaptability. It can replace traditional discrete device packaging at the board level, solving key problems such as large size and low integrated power density, significantly saving space and simplifying system circuit layout. In addition, through stacked three-dimensional welding, the space of the volume cavity can be reduced, realizing three-dimensional integrated rectifier array device packaging, greatly improving device production efficiency and saving packaging shells.

[0060] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This utility model includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all implementation methods. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this utility model are within the protection scope of this utility model.

Claims

1. A surface-mount power hybrid integrated circuit module packaging structure, characterized in that: Includes a ceramic base body (1), an inner cavity (2), a side cavity (3), a sealing ring (4), a cover plate (5), a bottom surface of the inner cavity (6), a metallization layer on the bottom surface of the inner cavity (7), a bottom surface of the power area of ​​the inner cavity (8), a metallization layer on the bottom surface of the power area (9), a high-power chip (10), a copper-plated heat sink (11), a through-type inner electrode (12), a buried inner electrode (13), a side electrode (14), and an external electrode (15); The ceramic base body (1) is a multi-layer co-fired ceramic; The inner cavity (2), side cavity (3), bottom surface of the inner cavity (6), bottom surface of the inner cavity power area (8), mounting holes of the copper-plated heat sink (11) and filling holes of the through-type inner electrode (12) are integrally fabricated inside the ceramic base body (1). The bottom surface of the inner cavity (6) is located in the peripheral area of ​​the bottom of the inner cavity of the ceramic base, and the bottom surface of the inner cavity power area (8) is located in the central area of ​​the bottom of the inner cavity of the ceramic base. The bottom surface of the inner cavity (6) is higher than the bottom surface of the inner cavity power area (8). The sealing ring (4) is located above the side cavity (3), and the cover plate (5) is located above the sealing ring (4). The inner cavity bottom surface metallization layer (7) is fabricated on the inner cavity bottom surface (6), and the power region bottom surface metallization layer (9) is fabricated on the inner cavity power region bottom surface (8); the inner cavity bottom surface metallization layer (7) is located in the low power chip assembly area, bonding area, and internal electrode wiring area, and the power region bottom surface metallization layer (9) is located in the high power chip assembly area. The copper-plated heat sink (11) is located in the central area of ​​the high-power chip assembly area and penetrates the ceramic base body; The through hole of the through-hole inner electrode (12) is located below the metallization layer (7) on the bottom surface of the inner cavity, penetrating the ceramic base body. The through hole is filled with a metal electrode. The buried inner electrode (13) is located between the ceramic layers of the multilayer co-fired ceramic. The side electrode (14) is located on the side wall of the ceramic base body. The external electrode (15) is located at the bottom of the ceramic base body. The upper end of the metal through hole is connected to the metallization layer (7) on the bottom surface of the inner cavity. The inside of the buried inner electrode (13) is connected to the metallization layer (7) on the bottom surface of the inner cavity, and the outside is connected to the side electrode (14). The external electrode (15) is connected to the lower end of the metal through hole and the lower end of the side electrode (14).

2. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The base area is laid out as follows: high-power chip area, low-power device area, and external lead-out electrode area; The surfaces of the high-power chip area, the low-power device area, and the external lead electrode area have metallization layers.

3. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The inner surface metallization layer has a gold layer as the first layer, a nickel layer, a nickel-cobalt layer, or a nickel-phosphorus layer as the second layer, and a tungsten layer or a molybdenum-manganese layer as the third layer. The thickness of the nickel layer, nickel-cobalt layer, or nickel-phosphorus layer is 1.3 to 8.9 μm.

4. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The outer surface of the bottom outer electrode is a metal block, and the bottom layer is a tungsten layer or a molybdenum-manganese layer. The metal block is welded to the tungsten layer or the molybdenum-manganese layer.

5. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The thickness range of each metal layer in the metallization layer on the surface of the external electrode is as follows: the thickness of the top gold layer is 1.3 to 5.7 μm, the thickness of the second metal layer (nickel, nickel-cobalt, or nickel-phosphorus) is 1.3 to 8.9 μm, and the thickness of the third metal layer (tungsten or molybdenum-manganese) is 5 to 30 μm; the length of each external lead-out terminal is 0.5 mm.

6. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The outer surface metal of the side electrode is a nickel layer, a nickel-cobalt layer, or a nickel-phosphorus layer, and the bottom layer is a tungsten layer or a molybdenum-manganese layer. The thickness of the nickel layer, nickel-cobalt layer, or nickel-phosphorus layer is 1.3 to 8.9 μm, and the thickness of the tungsten layer or molybdenum-manganese layer is 5 to 30 μm.

7. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The cover plate is located above the sealing ring, and the sealing ring and the cover plate are connected by airtight parallel seam welding.

8. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The inner surface metallization layer is distributed as follows: B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18; B17 is the high-power chip welding area, located in the bottom and middle area of ​​the inner cavity (2); B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, and B16 are the low-power chip soldering area and electrode lead or bonding area, located around B17; B18 is the lead transition area that is electrically connected to the soldering area, and is set according to the lead design. The inner surface electrodes are distributed as follows: 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8E, 9M, 7C, 6C, 5C, 4C, 3C, 2C, 1C, which are integrated with B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16 in sequence; The outer electrodes on the bottom outer surface are distributed as follows: P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16. P1, P2, P3, P4, P5, P6, P7, and P8 are arranged from top to bottom on the left side of the bottom of the ceramic base body (1), and P9, P10, P11, P12, P13, P14, P15, and P16 are arranged from bottom to top on the right side of the bottom of the ceramic base body (1).

9. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 8, characterized in that: P1 is connected to 1B, P2 is connected to 2B, P3 is connected to 3B, P4 is connected to 4B, P5 is connected to 5B, P6 is connected to 6B, P7 is connected to 7B, P8 is connected to 8E, P9 is connected to 9M, P10 is connected to 7C, P11 is connected to 6C, P12 is connected to 5C, P13 is connected to 4C, P14 is connected to 3C, P15 is connected to 2C, and P16 is connected to 1C. The high-power chip is connected to the inner surface electrode by metal wire bonding.

10. The surface-mount power hybrid integrated circuit module packaging structure as described in claim 1, characterized in that: The ceramic base body is a square ceramic base; The cover plate is a square metal cover plate.

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