Chip packaging structure and PCB

Abstract

The utility model provides a chip packaging structure, which comprises a plastic packaging body, a plurality of first leading-out pieces and a groove, each first leading-out piece is led out from the side surface of the plastic packaging body, each first leading-out piece comprises at least two leading-out pieces with specific functions, and the groove extends into the plastic packaging body from the top surface of the plastic packaging body. And the corresponding parts, positioned in the plastic package body, of the leading-out pieces with the specific functions are exposed, so that the two leading-out pieces with the specific functions are interconnected with a component. Therefore, the component is arranged on the top surface of the plastic package body and can be interconnected with the lead-out piece with a specific function through the groove, so that the electrical performance of the chip in an operation state is improved, for example, the capacitor is arranged on the top surface of the plastic package body and can be very close to the chip in the chip package structure, and the power supply stability and the EMC performance of the chip are improved; and the components do not occupy the space of the PCB and do not influence the wiring of each lead-out piece, so that the design is flexible, and the application range is very wide. Correspondingly, the utility model also provides a PCB (Printed Circuit Board).

Description

Technical Field

[0001] This utility model relates to the field of packaging technology, and in particular to a chip packaging structure and PCB board. Background Technology

[0002] To ensure the power supply stability of chips, existing electronic systems typically require reserved capacitor soldering positions between power supplies (e.g., VDD / VBAT / VREF+ / VCAP) and grounds (e.g., VSS) on the printed circuit board (PCB). The closer the capacitor is to the main chip of the electronic system (e.g., a microcontroller unit (MCU) or a system-on-a-chip (SOC), the better the power supply stability and EMC performance. This type of capacitor is also called a decoupling capacitor, which can filter out high-frequency noise, making the voltage stable and clean, and ensuring the normal operation of the main chip of the electronic system. Furthermore, to reduce the influence of parasitic inductance and equivalent resistance, the capacitor should be placed as close as possible to the main chip, thereby improving power supply stability and EMC (Electromagnetic Compatibility) performance.

[0003] However, for large-package main chip structures, the number of leads is large, and too many leads need to be routed as signal lines, making capacitor placement a challenge. In some cases, to place capacitors on a limited PCB board without affecting lead routing, the only options are to remove capacitors, replace them with smaller capacitors to reduce their size, or place them further away from the main chip (even to the back of the PCB). However, this undoubtedly reduces the power supply stability and EMC performance of the main chip. Utility Model Content

[0004] The purpose of this invention is to provide a chip packaging structure and PCB board to solve the problems of difficulty in placing capacitors on the PCB board of existing electronic systems containing chips, and the inability to further improve power stability and EMC performance.

[0005] To achieve the above objectives, this utility model provides a chip packaging structure, comprising:

[0006] Plastic encapsulation;

[0007] A plurality of first leads, each first lead extending from the surface of the encapsulation, each first lead including at least two specific functional leads; and,

[0008] A groove extends from the top surface of the molding compound into the molding compound and exposes the portion of the corresponding functional lead located within the molding compound for interconnection between the two functional leads and a component.

[0009] Optionally, the component has a second lead-out, which is interconnected with a corresponding functional lead-out via a corresponding groove or via a conductive material.

[0010] Optionally, two of the specific function leads are grouped together, and the two specific function leads in the same group are interconnected with the same component.

[0011] Optionally, two of the specific functional leads in the same group are adjacent to each other.

[0012] Optionally, the chip packaging structure further includes:

[0013] A connecting groove extends from the top surface of the molding compound into the molding compound, and the two ends of the connecting groove are respectively connected to the grooves corresponding to the two specific functional leads in the same group to accommodate the components.

[0014] Optionally, the connecting groove is located between two specific function leads in the same group, and is coaxially arranged with the two grooves corresponding to the two specific function leads in the same group.

[0015] Optionally, the depth of the connecting groove is the same as that of the recess.

[0016] Optionally, the distance between two of the specific functional leads in the same group is greater than or equal to 0.6 mm.

[0017] Optionally, the groove fully exposes the portion of the corresponding functional lead located within the molding compound; or, the groove exposes a portion of the portion of the corresponding functional lead located within the molding compound.

[0018] Optionally, the specific functional leads are power leads and ground leads, and the components include capacitors, clamping devices or ESD devices.

[0019] Optionally, this utility model also provides a PCB board, comprising:

[0020] substrate;

[0021] The chip packaging structure is soldered onto the substrate; and...

[0022] The components are located on the top surface of the plastic encapsulation of the chip package structure and are interconnected with the corresponding specific functional leads through the grooves.

[0023] The chip packaging structure provided by this utility model includes a molding compound, multiple first leads, and a recess. Each first lead extends from the surface of the molding compound and includes at least two specific functional leads. The recess extends from the top surface of the molding compound into the molding compound, exposing the portion of the corresponding specific functional lead located within the molding compound, allowing the two specific functional leads to interconnect with a component. Thus, by placing the component on the top surface of the molding compound, the component can interconnect with the specific functional leads through the recess, improving the electrical performance of the chip in operation. For example, placing a capacitor on the top surface of the molding compound allows the capacitor to be very close to the chip within the chip packaging structure, improving the chip's power stability and EMC performance. Furthermore, the component does not occupy PCB board space or affect the routing of the leads, offering flexible design and a wide range of applications. Correspondingly, this utility model also provides a PCB board. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the chip packaging structure provided in an embodiment of the present utility model;

[0025] Figure 2 A schematic diagram illustrating the interconnection between components and specific functional leads provided in this embodiment of the utility model;

[0026] Figure 3 An enlarged schematic diagram of the groove and the connecting groove provided in an embodiment of this utility model;

[0027] The attached figures are labeled as follows:

[0028] 10 - Molded enclosure; 20 - First lead-out; 21 - Specific function lead-out; 30 - Groove; 40 - Connecting groove; 50 - Component; 51 - Second lead-out; VDD1, VDD2, VDD3 - Power supply lead-out; VSS1, VSS2, VSS3 - Grounding lead-out. Detailed Implementation

[0029] The specific embodiments of this utility model will now be described in more detail with reference to the accompanying drawings. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0030] The terminology used in this utility model is for the purpose of describing particular embodiments only and is not intended to limit the utility model. Unless otherwise defined in this application, the technical or scientific terms used in this utility model should be understood in their ordinary meaning by one of ordinary skill in the art to which this utility model pertains. The words "a" or "one" and similar terms used in this utility model do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, the words "above" and / or "below" and similar terms are for ease of description only and are not limited to a location or spatial orientation. The words "comprising" or "including" and similar terms mean that the elements or structures preceding "comprising" or "including" encompass the elements or structures listed following "comprising" or "including" and their equivalents, and do not exclude other elements or structures.

[0031] Figure 1 This is a schematic diagram of the chip packaging structure provided in this embodiment. Figure 1 As shown, the chip packaging structure includes a molding compound 10, multiple first leads 20, and a recess 30.

[0032] Specifically, the encapsulation 10 contains a chip ( Figure 1 (Not shown in the image), the chip can be a bare die obtained by directly dicing a wafer, and the chip is encapsulated by a molding compound 10. The chip includes a substrate, a device structure located within / on the substrate, and multiple pads interconnecting with the device structure, the multiple pads may include functional pads.

[0033] Please continue reading. Figure 1 The molding compound 10 has a top surface and a bottom surface opposite to each other, as well as at least two side surfaces opposite to each other. When the chip package structure is mounted on a PCB board, the bottom surface of the molding compound 10 is usually facing the surface of the PCB substrate, while the top surface of the molding compound 10 is facing away from the surface of the PCB substrate, thus serving as a heat dissipation surface. Each first lead 20 extends from the surface of the molding compound 10. A portion of each first lead 20 is located outside the molding compound 10, and another portion is located inside the molding compound 10, interconnecting with the corresponding pad of the chip (through direct contact or through conductive material). Optionally, the first lead 20 can extend from the bottom surface of the molding compound 10 or from the side surface of the molding compound 10; examples will not be provided here.

[0034] Optionally, the chip package structure can be a through-hole package, where the first lead 20 can be a through-hole lead, extending from the side of the molded body 10 along the direction from the top to the bottom surface of the molded body 10. Alternatively, the chip package structure can be a surface-mount package, where the first lead 20 can be a surface-mount lead, extending from the side of the molded body 10 in a direction perpendicular to the side. On the side of the molded body 10, multiple first leads 20 can be arranged linearly along the centerline of the side, with a certain spacing between adjacent first leads 20 for electrical isolation. Optionally, the first lead 20 can be a pin, a wire, or a solder ball.

[0035] Understandable, Figure 1 The chip packaging structure and the number of first leads 20 shown are merely examples. The chip packaging structure can be, for example, DIP (Dual In-line Package), SOP (Small Outline Package), QFP (Quad Flat Package), BGA (Ball Grid Array Package), QFN (QFN Chip-Level Leadless Package), LGA (Large Outline Package), TSSOP (Thin Small Outline Package), etc. The number and specific structure of the first leads 20 need to be determined based on the specific chip and its packaging method. Therefore, although the first leads 20 in this embodiment only extend from two opposite sides of the molding compound 10, this should not be considered a limitation. In some embodiments, the first leads 20 can also extend from two other opposite sides of the molding compound 10 or from the bottom surface of the molding compound 10.

[0036] Furthermore, the first lead-out 20 includes at least two specific function leads 21, which are interconnected with corresponding specific function pads. A recess 30 extends from the top surface of the molding compound 10 into the molding compound 10, exposing portions of the corresponding specific function leads 21 located within the molding compound 10, for interconnection between the two specific function leads 21 and a component 50. Specifically, Figure 2 This is a schematic diagram illustrating the interconnection between component 50 and specific functional lead-out element 21 provided in this embodiment. (See diagram below.) Figure 2 As shown, component 50 has a second lead 51. The second lead 51 can extend into the groove 30 to directly contact the corresponding specific function lead 21 through the groove 30 (which also requires the use of solder) to achieve interconnection. Alternatively, the second lead 51 can not extend into the groove 30, but can contact the corresponding specific function lead 21 through a conductive material (such as solder) to achieve interconnection.

[0037] As can be seen, interconnecting the appropriate component 50 with the specific functional lead-out 21 in this embodiment can improve the electrical performance of the chip in operation. At this time, the component 50 is interconnected with the portion of the corresponding specific functional lead-out 21 located within the molding compound 10 via the groove 30. The portion of the specific functional lead-out 21 exposed by the groove 30 is the reserved soldering position for the component 50. The component 50 can be soldered onto the portion of the specific functional lead-out 21 exposed by the groove 30 without affecting the routing of each first lead-out 20. It is also easy to modify and replace, eliminating the need to find the corresponding component 50 for the specific functional lead-out 21 on the PCB board. Furthermore, the component 50 can be placed on the top surface of the molding compound 10, without occupying PCB board space, greatly improving PCB board space utilization. The design is flexible and has a very wide range of applications. In particular, the chip packaging structure in this embodiment does not increase packaging costs. It only requires that when forming the molding compound 10, the corresponding position in the groove 30 is not filled with molding compound, thereby exposing a portion of the specific functional lead-out 21 (the area that should originally be located within the molding compound 10).

[0038] It should be noted that when designing the chip package structure, if it is known whether each specific functional lead 21 needs to be interconnected with the component 50, then the corresponding groove 30 can be designed only for the specific functional lead 21 that needs to be interconnected with the component 50. If it is not known whether each specific functional lead 21 needs to be interconnected with the component 50 (or it is just for the convenience of fabrication), the corresponding groove 30 can be designed for all specific functional leads 21.

[0039] In this embodiment, two specific function leads 21 are grouped together. For example, a specific function pad can be a power pad and a ground pad, through which the chip can be powered, and the corresponding power pad and ground pad are grouped together; the specific function lead 21 can be a power lead and a ground lead, and the corresponding power lead and ground lead are grouped together, with the two power leads and ground leads in the same group interconnected with the power pad and ground pad respectively, and used to connect to the positive and negative terminals of the power supply respectively.

[0040] Based on this, such as Figure 2As shown, two specific functional leads 21 in the same group can be interconnected with the same component 50. For example, two power leads and a ground lead in the same group can be interconnected with the two ends of a capacitor, specifically in series. The capacitor is then placed on the top surface of the plastic package 10. The capacitor can be very close to the chip within the chip package structure, storing charge when the voltage is too high and releasing charge when the voltage drops, thereby smoothing voltage fluctuations and improving the chip's power supply stability and EMC performance. Specifically, when the GPIO signal frequently toggles, it generates rapid current changes, causing power supply voltage fluctuations. The capacitor can reduce these fluctuations and maintain a stable voltage by quickly storing and releasing charge, solving the problem of unstable power supply voltage and voltage drops below the standard value after too many GPIO signal toggles. Furthermore, the capacitor does not occupy PCB board space, allowing for the use of large-capacity capacitors, and does not affect the routing of the individual leads.

[0041] It should be noted that the component 50 in this embodiment is not limited to a capacitor, but may also be a clamping device (such as a clamping diode) or an ESD device (such as a diode or a transistor), a resistor or an inductor, etc. The connection relationship between the component 50 and the specific functional lead-out piece 21 may be in series or other connection relationships.

[0042] Figure 1 The example demonstrates three sets of power leads and ground leads (specifically, power pins and ground pins). Power lead VDD1 and ground lead VSS1 form one set, power lead VDD2 and ground lead VSS2 form another set, and power lead VDD3 and ground lead VSS3 form yet another set. The potential difference between any two power leads and ground leads within the same set can be the same or different. Each of the power leads VDD1, ground lead VSS1, power lead VDD2, ground lead VSS2, power lead VDD3, and ground lead VSS3 has a corresponding groove 30, exposing portions of each power lead VDD1, ground lead VSS1, power lead VDD2, ground lead VSS2, power lead VDD3, and ground lead VSS3 within the molding compound 10.

[0043] Furthermore, in this embodiment, the chip packaging structure also includes a connecting groove 40, which extends from the top surface of the molding compound 10 into the molding compound 10. The two ends of the connecting groove 40 are respectively connected to the corresponding grooves 30 of two specific functional leads 21 in the same group, for accommodating components 50. In this embodiment, the connecting groove 40 is located between the two specific functional leads 21 in the same group and is coaxially arranged with the two corresponding grooves 30 of the two specific functional leads 21 in the same group. Thus, some surface-mount components 50 (such as surface-mount capacitors) can be conveniently placed within the connecting groove 40 and surface-mounted (SMT) between the two specific functional leads 21 in the same group using stencil-printed solder paste or other conductive materials.

[0044] For example, in Figure 1 In the middle, there is a connecting groove 40 between the two grooves 30 corresponding to the power lead VDD1 and the ground lead VSS1. This connecting groove 40 communicates with the two grooves 30 corresponding to the power lead VDD1 and the ground lead VSS1 to accommodate the component 50 interconnected with the power lead VDD1 and the ground lead VSS1; there is also a connecting groove 40 between the two grooves 30 corresponding to the power lead VDD2 and the ground lead VSS2. This connecting groove 40 communicates with the two grooves 30 corresponding to the power lead VDD2 and the ground lead VSS2 to accommodate the component 50 interconnected with the power lead VDD1 and the ground lead VSS1. D2 communicates with the two grooves 30 corresponding to the ground lead VSS2 to accommodate the component 50 interconnected with the power lead VDD2 and the ground lead VSS2; there is a connecting groove 40 between the two grooves 30 corresponding to the power lead VDD3 and the ground lead VSS3, and this connecting groove 40 communicates with the two grooves 30 corresponding to the power lead VDD3 and the ground lead VSS3 to accommodate the component 50 interconnected with the power lead VDD3 and the ground lead VSS3. Figure 3 This is an enlarged schematic diagram of the groove 30 and the connecting groove 40 provided in this embodiment. Figure 3 As shown, the connecting groove 40 and the two grooves 30 connected to it can actually be different parts of the same groove. The depth of the connecting groove 40 and the grooves 30 is preferably the same. In this way, the surface mount component 50 is placed more stably in the connecting groove 40, and the corresponding second lead 51 and the first lead 20 can also be in closer contact. However, this should not be a limitation. In some embodiments, the depth of the connecting groove 40 and the grooves 30 can also be different.

[0045] Of course, in some embodiments, the connecting slot 40 can also be omitted, that is, the grooves 30 corresponding to the two specific function leads 21 in the same group are independent of each other. This solution is more suitable for through-hole components 50. The second lead 51 of the through-hole component 50 can extend into the grooves 30 corresponding to the two specific function leads 21 in the same group to achieve interconnection with the specific function leads 21.

[0046] from Figure 1 As can be seen, power lead VDD1 and ground lead VSS1 are adjacent to each other, power lead VDD2 and ground lead VSS2 are adjacent to each other, and power lead VDD3 and ground lead VSS3 are adjacent to each other. That is, in this embodiment, the two specific function leads 21 in the same group are adjacent to each other, which conforms to design habits, but is not limited to this. In some embodiments, the two specific function leads 21 in the same group may not be adjacent to each other.

[0047] Furthermore, in order to accommodate the component 50 within the communicating groove 40, the distance between two specific functional leads 21 in the same group cannot be too small. For example, the distance between two specific functional leads 21 in the same group is preferably greater than or equal to 0.6 mm, but should not be limited thereto. It should be noted that in this embodiment, if the first leads 20 are arranged at equal intervals, the distance between two adjacent first leads 20 cannot be too small. For example, the distance between two adjacent first leads 20 is preferably greater than 0.6 mm, but should not be limited thereto.

[0048] As an optional embodiment, the groove 30 may fully expose the portion of the corresponding specific function lead-out 21 located within the encapsulation body 10, or it may only expose a portion of the portion of the corresponding specific function lead-out 21 located within the encapsulation body 10 (as long as the exposed area meets the welding requirements). This utility model does not impose any limitations.

[0049] Based on this, this embodiment also provides a PCB board. The PCB board includes a substrate, the above-mentioned chip packaging structure, and components 50, wherein the chip packaging structure is soldered onto the substrate, and the components 50 are located on the top surface of the plastic encapsulation 10 of the chip packaging structure and are interconnected with corresponding specific functional lead-outs 21 through grooves 30.

[0050] In summary, the chip packaging structure provided in this embodiment includes a molding compound 10, a plurality of first leads 20, and a recess 30. Each first lead 20 extends from the side of the molding compound 10 and includes at least two specific functional leads 21. The recess 30 extends from the top surface of the molding compound 10 into the molding compound 10, exposing the portion of the corresponding specific functional lead 21 located within the molding compound 10, so that the two specific functional leads 21 can be interconnected with a component 50. Thus, by placing the component 50 on the top surface of the molding compound 10, the component 50 can be interconnected with the specific functional leads 21 through the recess 30, improving the electrical performance of the chip in operation. For example, by placing a capacitor on the top surface of the molding compound 10, the capacitor can be very close to the chip within the chip packaging structure, improving the chip's power supply stability and EMC performance. Furthermore, the component 50 does not occupy PCB board space and does not affect the routing of the leads, offering flexible design and a wide range of applications. Accordingly, this utility model embodiment also provides a PCB board.

[0051] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0052] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention without departing from the scope of the present invention, or equivalent embodiments can be modified based on the disclosed technical content. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

[0053] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0054] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A chip packaging structure, characterized in that, include: Plastic encapsulation; Multiple first leads, each first lead extending from the surface of the encapsulation, each first lead including at least two specific functional leads; as well as, A groove extends from the top surface of the molding compound into the molding compound and exposes the portion of the corresponding functional lead located within the molding compound for interconnection between the two functional leads and a component.

2. The chip packaging structure as described in claim 1, characterized in that, The component has a second lead-out, which is interconnected with the corresponding functional lead-out through a corresponding groove or through a conductive material.

3. The chip packaging structure as described in claim 1, characterized in that, Two of the aforementioned specific function leads form a group, and the two aforementioned specific function leads in the same group are interconnected with the same aforementioned component.

4. The chip packaging structure as described in claim 3, characterized in that, The two specific function leads in the same group are adjacent to each other.

5. The chip packaging structure as described in claim 3 or 4, characterized in that, The chip packaging structure also includes: A connecting groove extends from the top surface of the molding compound into the molding compound, and the two ends of the connecting groove are respectively connected to the grooves corresponding to the two specific functional leads in the same group to accommodate the components.

6. The chip packaging structure as described in claim 5, characterized in that, The connecting groove is located between the two specific function leads in the same group, and is coaxially arranged with the two grooves corresponding to the two specific function leads in the same group.

7. The chip packaging structure as described in claim 5, characterized in that, The depth of the connecting groove is the same as that of the recess.

8. The chip packaging structure as described in claim 3 or 4, characterized in that, The distance between two of the specific functional leads in the same group is greater than or equal to 0.6 mm.

9. The chip packaging structure as described in claim 1, characterized in that, The groove fully exposes the portion of the corresponding functional lead located within the molding compound; or, the groove exposes a portion of the portion of the corresponding functional lead located within the molding compound.

10. The chip packaging structure as described in claim 1, characterized in that, The two specific functional leads are a power lead and a ground lead, and the components include capacitors, clamping devices or ESD devices.

11. A PCB board, characterized in that, include: substrate; The chip packaging structure as described in any one of claims 1 to 10 is soldered onto the substrate; as well as, The components are located on the top surface of the plastic encapsulation of the chip package structure and are interconnected with the corresponding specific functional leads through the grooves.

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