Level shift circuit for switching converter
Through the high and low power rail separation design of the voltage sampling module and the level down-shift module, combined with PMOS tubes, NMOS tubes and buffers, the problems of fast speed, low power consumption and anti-interference of the level down-shift circuit in a high-voltage environment are solved, and efficient level conversion is achieved.
Patent Information
- Application Number
- CN202422830394.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2034-11-20
AI Technical Summary
In the prior art, the level-down shift circuit is poorly designed under high-voltage environments and cannot be fast, low-power, and anti-interference, resulting in low level conversion efficiency and low integration.
It adopts voltage sampling module and level down-shifting module, including sampling input unit, speed-up unit, sampling output unit, level input unit, voltage limiting unit, anti-interference unit and level output unit. Through the separation design of high and low power rails, level shifting is achieved by using PMOS tubes, NMOS tubes, capacitors, resistors and buffers, and the anti-interference ability is improved by combining unidirectional delay reverse circuit.
It realizes fast level conversion from high voltage domain to low voltage domain, with level shift time less than 2ns and quiescent current of only 2μA, low power consumption, high integration and excellent anti-interference ability.
Smart Images
Figure CN223488087U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of switching power supply technology, specifically a level shifting circuit for switching converters. Background Technology
[0002] In switching converters, level shifting circuits are a crucial component. They primarily address signal level conversion between different voltage domains and, as a vital link in the drive logic chain, their operating frequency must be consistent with that of the power transistors. Since the drive logic chain first enters the high power rail and then the low power rail, the level shifting circuit consists of level up and level down circuits. The level up circuit transmits the control signal to the high-voltage side, while the level down circuit transmits the output pulse of the PWM comparator to the low-voltage side.
[0003] To ensure the high-speed and reliable operation of the overall circuit, the level shifting circuit should have the following characteristics:
[0004] (1) Transfer the level to be transmitted to other power rails for circuit control as quickly as possible;
[0005] (2) It should have sufficient anti-interference capability. Each key node should have an active low-impedance path connected to the power rail potential during the dV / dt stage, and a latching structure should be formed during the steady-state stage to prevent circuit erroneous flipping.
[0006] (3) During the state switching phase, there is a large transient current used for charging and discharging when the potential of each node is switched. After the state switching is completed, there should only be static leakage current to reduce circuit power consumption.
[0007] While current technical literature presents various circuit architectures for implementing level shifting, most research and innovation focus on the design and optimization of level-up shifting circuits, with relatively little attention paid to level-down shifting circuits. The design requirements for level-down shifting circuits differ significantly from those for level-up shifting circuits, necessitating targeted optimization design.
[0008] Currently, a common design for level-down shifting circuits is a simple resistor divider network. This approach reduces the signal voltage using only two resistors, but it is often inefficient and may not provide sufficient current drive capability. Alternatively, a dedicated level-shifting chip design can provide more efficient and accurate level shifting, and usually offers better electrical isolation. However, this design results in lower integrated circuit integration density and higher cost. In the field of integrated circuit design, there are various circuit schemes for implementing level-down shifting. For example, a simple level-down shifting circuit can be implemented by combining two inverters with different supply voltages. While this method is extremely simple to operate, it has limitations, such as being unusable at high supply voltages. In conventional high-voltage processes, connecting a high supply voltage to the gate of a MOSFET can damage the high-voltage MOSFET, rendering the level-down shifting circuit inoperable. Another method is to invert the level-up shifting circuit, i.e., swapping the positions of the high and low voltage supply points to achieve level shifting. However, this method suffers from problems such as improved level-up shifting circuits not supporting direct power supply position swapping, and classic level-up shifting circuits being unsuitable for high supply voltages. Therefore, it is particularly important to design a dedicated level downshifting circuit to meet specific design requirements. Utility Model Content
[0009] The purpose of this invention is to provide a level shifting circuit for a switching converter that can operate under high voltage conditions, realize the conversion of the voltage level from the high voltage domain to the low voltage domain, and has the characteristics of high speed, low power consumption and anti-interference.
[0010] To achieve the above objectives, the technical method adopted by this utility model is as follows:
[0011] A level shifting circuit for a switching converter includes a voltage sampling module and a level downshifting module. The voltage sampling module includes a sampling input unit, a speed-up unit, and a sampling output unit. The level downshifting unit includes a level input unit, a voltage limiting unit, an anti-interference unit, and a level output unit. The input terminal of the sampling input unit is connected to the gate of the high-power transistor in the switching converter. The output terminal of the sampling input unit is connected to the input terminals of the speed-up unit and the sampling output unit, respectively. The output terminals of the speed-up unit and the sampling output unit are both connected to the input terminal of the level input unit. The output terminal of the level input unit is connected to the input terminals of the voltage limiting module, the anti-interference module, and the level output unit, respectively. The voltage sampling module and the level input unit operate on the high power rail, while the voltage limiting unit, the anti-interference unit, and the level output unit operate on the low power rail.
[0012] As a limitation: the sampling input unit includes a first PMOS transistor and a first NMOS transistor; the speed-up unit includes a first voltage buffer, a first capacitor, a first resistor, and a second PMOS transistor; the sampling output unit includes a third PMOS transistor, a fourth PMOS transistor, and a second NMOS transistor; the gates of the first PMOS transistor and the first NMOS transistor are both connected to the gate of the high-power transistor in the switching converter; the source of the first PMOS transistor is connected to voltage BST; the drain of the first PMOS transistor is connected to the input terminal of the first voltage buffer, the gate of the third PMOS transistor, the gate of the second NMOS transistor, and the drain of the first NMOS transistor, respectively; the source of the first NMOS transistor... The first PMOS transistor is connected to the source of the second NMOS transistor and the control terminal of the level input unit, respectively. The source of the third PMOS transistor is connected to voltage BST. The drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, the input terminal of the level input unit, and the drain of the second NMOS transistor, respectively. The gate of the fourth PMOS transistor is connected to voltage PBIAS. The output terminal of the first voltage buffer is connected to one end of the first capacitor. The other end of the first capacitor is connected to one end of the first resistor and the gate of the second PMOS transistor, respectively. The other end of the first resistor and the source of the second PMOS transistor are both connected to voltage BST.
[0013] As further defined: the level input unit includes a first high-voltage PMOS transistor, the voltage limiting unit includes a fifth PMOS transistor and a third NMOS transistor, the anti-interference unit includes a unidirectional delay inversion circuit, a fourth NMOS transistor, and a second resistor, and the level output unit includes a second voltage buffer and a third resistor; the output terminal of the sampling input unit is connected to the gate of the first high-voltage PMOS transistor, the output terminals of the speed-up unit and the sampling output unit are both connected to the source of the first high-voltage PMOS transistor, the drain of the first high-voltage PMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the third NMOS transistor, one end of the second resistor, the input terminal of the second voltage buffer, and one end of the third resistor, respectively, the gate and source of the fifth PMOS transistor are both connected to the internal power supply voltage VDD, the gate of the third NMOS transistor is connected to the voltage NBIAS, the source of the third NMOS transistor is grounded, the other end of the second resistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate of the fourth NMOS transistor is connected to the output terminal of the unidirectional delay inversion circuit, the input terminal of the unidirectional delay inversion circuit is connected to the NBIAS voltage, and the output terminal of the second voltage buffer is connected to the other end of the third resistor to output the level signal.
[0014] As a further definition: the unidirectional delayed reverse circuit includes a sixth PMOS transistor, a fifth NMOS transistor, a fourth resistor, and a second capacitor. The gates of the sixth PMOS transistor and the fifth NMOS transistor are connected to the NBIAS voltage. The source of the sixth PMOS transistor is connected to the internal power supply voltage VDD. The drain of the sixth PMOS transistor is connected to one end of the fourth resistor, one end of the second capacitor, and the gate of the fourth NMOS transistor, respectively. The other end of the fourth resistor is connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor and the other end of the second capacitor are both grounded.
[0015] The beneficial effects achieved by this utility model, due to the adoption of the above-mentioned solution, compared with the prior art, are as follows:
[0016] (1) The present invention provides a level shifting circuit for a switching converter, which samples the gate signal of the upper power transistor in the switching converter through a voltage sampling module and outputs it to the level shifting module. This can accurately reflect the state signal of the upper power transistor in the switching converter to the subsequent circuit without affecting the driving capability of the upper power transistor. The level shifting time from the high power rail to the low power rail is less than 2ns, and the level shifting rate is fast. The static current is only 2μA, and the power consumption is low. Due to the special nature of the gate signal of the power transistor, a voltage sampling module is used to avoid affecting the state of the upper power transistor. The area occupied is very small and the integration is high.
[0017] (2) The present invention provides a level shifting circuit for a switching converter, wherein the first voltage buffer, the first capacitor, the first resistor, and the second PMOS transistor cooperate to improve the level shifting rate; the fourth PMOS transistor and its input bias voltage PBIAS together limit the maximum current output of the third PMOS transistor, avoiding the situation where the voltage BST is directly connected to ground; the voltage NBIAS controls the third NMOS transistor to turn on in advance, ensuring that the initial potential at the connection node of the third NMOS transistor, the fifth PMOS transistor, and the first high-voltage PMOS transistor is 0. At the same time, the potential of the voltage NBIAS is relatively low, and the current flowing through the third NMOS transistor is very small, reducing power consumption; the unidirectional delay inverting circuit only outputs a delayed inverted signal when the voltage NBIAS changes from 0 to high, improving the anti-interference capability. When the voltage NBIAS changes from high to low, there is no delay, which improves the level shifting speed when the input voltage changes from high to low; the second voltage buffer and the third resistor play a positive feedback role, improving the level shifting speed.
[0018] This invention is applicable to level conversion from high voltage to low voltage. Attached Figure Description
[0019] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0020] Figure 1 This is a circuit diagram of a level shifting circuit for a switching converter according to an embodiment of the present invention;
[0021] Figure 2 This is a circuit diagram of a unidirectional delayed reverse circuit according to an embodiment of the present invention;
[0022] Figure 3 This is a waveform diagram of one cycle during the Buck switch process in an embodiment of this utility model;
[0023] In the diagram: 1. Sampling input unit; 2. Speed-up unit; 3. Sampling output unit; 4. Level input unit; 5. Voltage limiting unit; 6. Anti-interference unit; 7. Level output unit. Detailed Implementation
[0024] The present invention will be further described below with reference to the embodiments. However, those skilled in the art should understand that the present invention is not limited to the following embodiments. Any improvements and equivalent changes made based on the specific embodiments of the present invention are within the scope of protection of the claims of the present invention.
[0025] Example 1: A level shifting circuit for a switching converter
[0026] A level shifting circuit for a switching converter includes a voltage sampling module and a level shifting module. The voltage sampling module includes a sampling input unit 1, a speed-up unit 2, and a sampling output unit 3. The level shifting unit includes a level input unit 4, a voltage limiting unit 5, an anti-interference unit 6, and a level output unit 7. The sampling input unit 1 includes a first PMOS transistor P1 and a first NMOS transistor N1. The speed-up unit 2 includes a first voltage buffer B1, a first capacitor C1, a first resistor R1, and a second PMOS transistor P2. The sampling output unit 3 includes a third PMOS transistor P3, a fourth PMOS transistor P4, and a second NMOS transistor N2. The level input unit 4 includes a first high-voltage PMOS transistor HP1. The voltage limiting unit 5 includes a fifth PMOS transistor P5 and a third NMOS transistor N3. The anti-interference unit 6 includes a unidirectional delayed inverting circuit, a fourth NMOS transistor N4, and a second resistor R2. The level output unit 7 includes a second voltage buffer B2 and a third resistor R3. The voltage sampling module and the level input unit 4 operate on the high power rail, while the voltage limiting unit 5, the anti-interference unit 6, and the level output unit 7 operate on the low power rail.
[0027] like Figure 1As shown, the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are both connected to the gate of the high-power transistor in the switching converter. The source of the first PMOS transistor P1 is connected to voltage BST. The drain of the first PMOS transistor P1 is connected to the input of the first voltage buffer B1, the gate of the third PMOS transistor P3, the gate of the second NMOS transistor N2, and the drain of the first NMOS transistor N1. The output of the first voltage buffer B1 is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to one end of the first resistor R1 and the gate of the second PMOS transistor P2. The other end of the first resistor R1 and the source of the second PMOS transistor P2 are both connected to voltage BST. The source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and the gate of the first high-voltage PMOS transistor HP1. The source of the third PMOS transistor P3 is connected to voltage BST. The drain of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4. The drain of the first high-voltage PMOS transistor P2 is connected to the drain of the second PMOS transistor P2, the source of the first high-voltage PMOS transistor HP1, and the drain of the second NMOS transistor N2. The gate of the fourth PMOS transistor is connected to the voltage PBIAS. The drain of the first high-voltage PMOS transistor HP1 is connected to the drain of the fifth PMOS transistor P5, the drain of the third NMOS transistor N3, one end of the second resistor R2, the input of the second voltage buffer B2, and one end of the third resistor R3. The gate and source of the fifth PMOS transistor P5 are both connected to the internal power supply voltage VDD. The gate of the third NMOS transistor N3 is connected to the voltage NBIAS. The source of the third NMOS transistor N3 is grounded. The other end of the second resistor R2 is connected to the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 is grounded. The gate of the fourth NMOS transistor N4 is connected to the output of the unidirectional delay inversion circuit. The input of the unidirectional delay inversion circuit is connected to the NBIAS voltage. The output of the second voltage buffer B2 is connected to the other end of the third resistor R3 to output a level signal.
[0028] like Figure 2 As shown, in this embodiment, the unidirectional delayed inverting circuit includes a sixth PMOS transistor P6, a fifth NMOS transistor N5, a fourth resistor R4, and a second capacitor C2. The gates of the sixth PMOS transistor P6 and the fifth NMOS transistor N5 are connected to the NBIAS voltage. The source of the sixth PMOS transistor P6 is connected to the internal power supply voltage VDD. The drain of the sixth PMOS transistor P6 is connected to one end of the fourth resistor R4 and one end of the second capacitor C2, respectively, as the output terminal OUT1 of the unidirectional delayed inverting circuit, outputting a delayed inverted signal to the gate of the fourth NMOS transistor N4 to improve the anti-interference capability of the circuit. The other end of the fourth resistor R4 is connected to the drain of the fifth NMOS transistor N5. The source of the fifth NMOS transistor N5 and the other end of the second capacitor C2 are both grounded.
[0029] The level shifting circuit in this embodiment samples the gate signal IN of the upper power transistor in the switching converter through a voltage sampling module and outputs it to the level down shifting module. This can accurately reflect the state signal of the upper power transistor in the switching converter to the subsequent circuit without affecting the driving capability of the upper power transistor. When the power transistor on the switching converter starts to conduct, the voltage at the SW node is the power supply voltage VIN of the input switching converter; the voltage BST is the power supply voltage VIN of the input switching converter plus an internal power supply voltage VDD, i.e., BST = VIN + VDD. The input voltage IN is close to the voltage BST, which is equivalent to the high level on the high power rail. At this time, the input voltage of the first voltage buffer B1 is low, which pulls down the gate voltage of the second PMOS transistor P2. The second PMOS transistor P2 conducts, providing current for the level shifting circuit, and the voltage at the VH node becomes high. The first voltage buffer B1, the first capacitor C1, the first resistor R1, and the second PMOS transistor P2 play the role of boosting the speed. The gate of the second PMOS transistor P2 is connected to the voltage BST through the first resistor R1 and is usually high. Only when the input voltage IN is high, the first voltage buffer B1 briefly pulls down the voltage of the second PMOS transistor P2 through the first capacitor C1, so that the voltage at the VH node becomes high more quickly, thereby improving the level shifting speed. Subsequently, the gate voltage of the second PMOS transistor P2 increases, turning it off. Simultaneously, the third PMOS transistor P3 turns on, and voltage BST outputs current through PMOS transistors P3 and P4. The voltage at node VH remains high. Therefore, the voltage at node VH is the sampling output of the gate signal IN of the upper power transistor in the switching converter from the voltage sampling module. PMOS transistor P4 and its input bias voltage PBIAS together limit the maximum current output from PMOS transistor P3 to node VH, preventing voltage BST from directly connecting to ground. When the voltage at node VH becomes high, current flows into the level-down shift module through the first high-voltage PMOS transistor HP1. Since the current flowing into HP1 is greater than the current flowing to ground, the voltage at node VL becomes high, and the output signal OUT of level output unit 7 becomes high. The fifth PMOS transistor, P5, limits the maximum voltage at the VL node. Excess current flowing through the second PMOS transistor, P2, flows to VDD through the body diode of the fifth PMOS transistor, P5. Therefore, the maximum voltage at the VL node is approximately VDD + 0.7V, achieving a transition from the high-voltage to the low-voltage domain. The voltage NBIAS slightly leads the input voltage IN. Before the voltage at the VL node rises, the third NMOS transistor, N3, has already turned on, ensuring that the initial potential at the VL node is 0. Simultaneously, the NBIAS potential is relatively low, resulting in a very small current flowing through the third NMOS transistor, N3, thus reducing power consumption.After passing through a unidirectional delayed inverting circuit, the voltage NBIAS is connected to the gate of the fourth NMOS transistor N4. During a certain period when the input voltage IN is high, the fourth NMOS transistor N4 remains on. During the rapid rise of the voltage at node SW from 0 to VDD, the dV / dt ratio between the gate and drain of the first high-voltage PMOS transistor HP1 is very large, causing its parasitic capacitance to discharge. The conduction of the fourth NMOS transistor N4 provides a discharge path, improving anti-interference capability. Once the parasitic capacitance of the first high-voltage PMOS transistor HP1 has discharged completely, the fourth NMOS transistor N4 is turned off, and no current flows, reducing static power consumption. The second resistor R2 limits the magnitude of the DC current flowing through the fourth NMOS transistor N4. The unidirectional delayed inverting circuit only outputs a delayed inverted signal when the voltage NBIAS changes from 0 to high, improving anti-interference capability; when the voltage NBIAS changes from high to low, there is no delay, increasing the speed of level shift when the input voltage IN changes from high to low. The second voltage buffer B2 and the third resistor R3 act as positive feedback, increasing the speed of level shift. When the high-power transistor in the switching converter starts to turn off, the first high-voltage PMOS transistor HP1 turns off. After a very short delay, the voltage NBIAS becomes low, the third NMOS transistor N3 turns off, and the fourth NMOS transistor N4 turns on, instantly pulling the voltage at the VL node low. The output signal OUT of the level output unit 7 is low.
[0030] The level shifting circuit in this embodiment is designed using a 0.18μm BCD process and is integrated into the Buck chip. During the Buck switching process, the gate signal of the high-power transistor continuously switches between high level, low level, high power rail, and low power rail. A waveform of one cycle (1μs) is captured as follows: Figure 3 As shown, when the input voltage IN changes from low to high, the output signal OUT also changes from low to high after approximately 1.5ns. Two voltage spikes appear at the VL node. The first spike is due to the brief conduction of the second PMOS transistor P2, and the second spike is due to the subsequent conduction of the third PMOS transistor P3 and the fourth PMOS transistor P4. Clearly, the first voltage buffer B1, the first capacitor C1, the first resistor R1, and the second PMOS transistor P2 contribute to the speed boost, enabling rapid level shifting even with a limited current in the third PMOS transistor P3. When the input voltage IN changes from high to low, the output signal OUT also changes from high to low after approximately 1ns. At this time, the fourth NMOS transistor N4 rapidly pulls down the voltage at the VL node, thus rapidly pulling down the output signal OUT.
Claims
1. A level shifting circuit for a switching converter, characterized in that, The system includes a voltage sampling module and a level shifting module. The voltage sampling module comprises a sampling input unit, a speed-up unit, and a sampling output unit. The level shifting unit comprises a level input unit, a voltage limiting unit, an anti-interference unit, and a level output unit. The input terminal of the sampling input unit is connected to the gate of the high-power transistor in the switching converter. The output terminal of the sampling input unit is connected to the input terminals of the speed-up unit and the sampling output unit, respectively. The output terminals of the speed-up unit and the sampling output unit are both connected to the input terminal of the level input unit. The output terminal of the level input unit is connected to the input terminals of the voltage limiting module, the anti-interference module, and the level output unit, respectively. The voltage sampling module and the level input unit operate on the high power rail, while the voltage limiting unit, the anti-interference unit, and the level output unit operate on the low power rail.
2. The level shifting circuit for a switching converter according to claim 1, characterized in that, The sampling input unit includes a first PMOS transistor and a first NMOS transistor; the speed-up unit includes a first voltage buffer, a first capacitor, a first resistor, and a second PMOS transistor; the sampling output unit includes a third PMOS transistor, a fourth PMOS transistor, and a second NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are both connected to the gate of the high-power transistor in the switching converter. The source of the first PMOS transistor is connected to voltage BST. The drain of the first PMOS transistor is connected to the input terminal of the first voltage buffer, the gate of the third PMOS transistor, the gate of the second NMOS transistor, and the drain of the first NMOS transistor, respectively. The source of the first NMOS transistor is connected to... The source of the second NMOS transistor is connected to the control terminal of the level input unit. The source of the third PMOS transistor is connected to voltage BST. The drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, the input terminal of the level input unit, and the drain of the second NMOS transistor. The gate of the fourth PMOS transistor is connected to voltage PBIAS. The output terminal of the first voltage buffer is connected to one end of the first capacitor. The other end of the first capacitor is connected to one end of the first resistor and the gate of the second PMOS transistor. The other end of the first resistor and the source of the second PMOS transistor are both connected to voltage BST.
3. A level shifting circuit for a switching converter according to claim 1 or 2, characterized in that, The level input unit includes a first high-voltage PMOS transistor, the voltage limiting unit includes a fifth PMOS transistor and a third NMOS transistor, the anti-interference unit includes a unidirectional delay inversion circuit, a fourth NMOS transistor, and a second resistor, and the level output unit includes a second voltage buffer and a third resistor. The output terminal of the sampling input unit is connected to the gate of the first high-voltage PMOS transistor, and the output terminals of the speed-up unit and the sampling output unit are both connected to the source of the first high-voltage PMOS transistor. The drain of the first high-voltage PMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the third NMOS transistor, one end of the second resistor, the input terminal of the second voltage buffer, and one end of the third resistor, respectively. The gate and source of the fifth PMOS transistor are both connected to the internal power supply voltage VDD. The gate of the third NMOS transistor is connected to the voltage NBIAS, and the source of the third NMOS transistor is grounded. The other end of the second resistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate of the fourth NMOS transistor is connected to the output terminal of the unidirectional delay inversion circuit, the input terminal of the unidirectional delay inversion circuit is connected to the NBIAS voltage, and the output terminal of the second voltage buffer is connected to the other end of the third resistor to output the level signal.
4. A level shifting circuit for a switching converter according to claim 3, characterized in that, The unidirectional delayed inverting circuit includes a sixth PMOS transistor, a fifth NMOS transistor, a fourth resistor, and a second capacitor. The gates of the sixth PMOS transistor and the fifth NMOS transistor are connected to the NBIAS voltage. The source of the sixth PMOS transistor is connected to the internal power supply voltage VDD. The drain of the sixth PMOS transistor is connected to one end of the fourth resistor, one end of the second capacitor, and the gate of the fourth NMOS transistor, respectively. The other end of the fourth resistor is connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor and the other end of the second capacitor are both grounded.