Low-noise amplifier capable of selecting performance parameters

Abstract

The utility model provides a low-noise amplifier capable of selecting performance parameters. The low-noise amplifier mainly comprises four switch modules, an optimal noise input matching module, an optimal gain input matching module, an optimal noise inter-stage matching module, an optimal gain inter-stage matching module, an optimal gain output matching module and a two-stage 0.15-micron GaAs pHEMT stable bias circuit. A plurality of modules capable of independently adjusting noise and gain are designed in the input matching module, the inter-stage matching module and the output matching module, and the noise and gain modules are adjusted through different combinations of the switch modules, so that optimal noise and gain parameters are selected; the optimal gain performance or the optimal noise performance can be selected according to the actual application condition. According to the low-noise amplifier designed by the invention, a noise optimal output signal or a gain optimal output signal can be realized in a working frequency band, and a certain reference is provided for performance optimization of a radio frequency transceiver.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency front-end technology, and particularly relates to a low-noise amplifier with selectable performance parameters. Background Technology

[0002] As low-frequency communication channels become increasingly congested and modern communication continues to evolve towards higher frequencies, the demand for ultra-wideband and high-frequency products will also increase. As the first stage circuit of an RF receiver, the low-noise amplifier (LNA) is required to have the lowest possible noise while simultaneously meeting certain gain requirements. However, in practical designs, it is difficult to maintain optimal noise and gain for both LNAs. To address this issue, this paper presents a low-noise amplifier design based on the gallium arsenide (GaAs) PHEMT 0.15µm process, allowing for the selection of optimal performance parameters.

[0003] Existing patent CN116505895A provides a low-noise amplifier with adjustable current and gain. Impedance adjustment is achieved by adjusting the values ​​of components in the input-output impedance matching circuit, thus enabling gain adjustment. However, this method requires a large number of adjustment devices, significantly increasing the chip size. Furthermore, the control of the switching devices is extremely complex and difficult to implement, and the large number of switching devices also introduces additional losses. For LNAs, noise and gain performance are particularly important, resulting in a large chip area and complex control logic. Utility Model Content

[0004] The purpose of this invention is to solve the problems in the existing technology that cannot keep both the noise and gain of the LNA in the optimal state, as well as the problems in the use of chips in the existing technology.

[0005] To achieve the above objectives, this utility model provides a low-noise amplifier with selectable performance parameters, including input matching, interstage matching, output matching, a first-stage amplifier circuit, and a second-stage amplifier circuit; the first-stage amplifier circuit is provided between the input matching and the interstage matching, and the second-stage amplifier circuit is provided between the interstage matching and the output matching.

[0006] The input matching includes two switching modules, an optimal noise input matching module, and an optimal gain input matching module; the switching module at the input end is connected to the signal input end, and the switching module at the output end is connected to the input end of the first-stage amplifier circuit; the optimal noise input matching module and the optimal gain input matching module are located between the two switching modules.

[0007] Interstage matching includes two switching modules, an optimal noise level interstage matching module, and an optimal gain level interstage matching module; the input switching module is connected to the output of the first-stage amplifier circuit, and the output switching module is connected to the input of the second-stage amplifier circuit; the optimal noise level interstage matching module and the optimal gain level interstage matching module are located between the two switching modules.

[0008] Output matching includes an optimal gain output matching module; one end of the optimal gain output matching module is connected to the output of the second-stage amplifier circuit, and the other end of the optimal gain output matching module is connected to the signal output.

[0009] Furthermore, the first-stage amplifier circuit and the second-stage amplifier circuit are composed of L1, L2 and L3. L1 and L2 serve as gate bias inductors and drain bias inductors, respectively, and L3 is a feedback inductor. L1 and L2 are connected to the gate voltage VG and the drain bias voltage VD, respectively, and the source of L3 is grounded.

[0010] Furthermore, the switch module includes SP1, SP2, SP3, and SP4, with SP1 and SP3 connected to SP2 and SP4 respectively, and the sources of SP2 and SP4 grounded; SP1, SP2, SP3, and SP4 are single-pole double-throw switches, and Port1, Port2, and Port3 can correspond to the three ports of the single-pole double-throw switch respectively.

[0011] Furthermore, the optimal noise input matching module consists of capacitors CI1 and CI2. In the input matching, the Port3 terminal of the input switching module is connected to capacitors CI1 and CI2. Capacitor CI1 is connected to the Port3 terminal of the output switching module in the input matching; the source of capacitor CI2 is grounded.

[0012] Furthermore, the optimal gain input matching module consists of an inductor L1 and a capacitor CI3. In the input matching, the Port2 terminal of the input switching module is connected to the capacitor CI3 and the inductor L1, and the other end of the capacitor CI3 is connected to the Port2 terminal of the output switching module in the input matching; the source of L1 is grounded.

[0013] Furthermore, the optimal noise level matching module is a T-shaped structure consisting of capacitors CM1 and CM2 and an inductor LM1. The Port3 terminal of the switching module at the inter-level matching input is connected to capacitor CM1. Capacitor CM1 is connected to the parallel connection point of capacitor CM2 and inductor LM1. The source of capacitor CM2 is grounded. Inductor LM1 is connected to the Port3 terminal of the switching module at the inter-level matching output.

[0014] Furthermore, the optimal gain interstage matching module adopts a die-shaped structure consisting of capacitors CM3 and CM4 and an inductor LM2. The Port2 terminal of the input switching module of the interstage matching is connected to the inductor LM2 and capacitor CM3. The inductor LM2 and capacitor CM3 are connected in parallel, and the capacitors CM3 and CM4 are connected in series. The sources of the inductor LM2 and capacitor CM4 are grounded. The parallel connection point of capacitors CM3 and CM4 is connected to the Port2 terminal of the output switching module of the interstage matching.

[0015] Furthermore, the optimal gain output matching module consists of capacitor CO and inductor LO. The output of the second-stage amplifier circuit is connected to capacitor CO and inductor LO. Capacitor CO is connected to the signal output terminal, and the source of inductor LO is grounded.

[0016] Beneficial effects:

[0017] This application designs multiple modules in the input matching module, inter-stage matching module, and output matching module that can independently adjust noise and gain. By using different combinations of switches for each noise and gain adjustment module, the noise and gain parameters of the low-noise amplifier can be flexibly adjusted, thereby achieving the selection of optimal noise and gain parameters and solving the problem that the noise and gain parameters of low-noise amplifiers in the prior art cannot be selected. Attached Figure Description

[0018] Figure 1 This is an overall structural diagram of the low-noise amplifier with selectable optimal performance parameters according to this utility model;

[0019] Figure 2 This is a circuit diagram of the first and second stage pHEMT stabilization and bias circuits of this utility model;

[0020] Figure 3 This is a schematic diagram of the switch structure of this utility model;

[0021] Figure 4 This is a diagram of the optimal noise input matching module of this utility model;

[0022] Figure 5 This is a diagram of the optimal gain input matching module of this utility model;

[0023] Figure 6 This is a diagram of the optimal noise level matching module of this utility model;

[0024] Figure 7 This is a diagram of the optimal gain stage matching module of this utility model;

[0025] Figure 8 This is the optimal gain output matching module diagram of this utility model;

[0026] Figure 9 This is a detailed circuit diagram showing the connections between the various modules of this utility model.

[0027] Note: Figures 4 to 8 The impedance matching circuit is a specific matching circuit designed based on the 0.15um pHEMT in this utility model. Different structures should be selected for the matching circuit for different application scenarios.

[0028] Reference numerals: 1-Input matching, 101-Optimal noise input matching module, 102-Optimal gain input matching module, 2-Interstage matching, 201-Optimal noise interstage matching module, 202-Optimal gain interstage matching module, 3-Output matching, 301-Optimal gain output matching module, 4-Switch module, 5-First stage amplifier circuit, 6-Second stage amplifier circuit.

[0029] Note: RFin is the signal input terminal, RFout is the signal output terminal, G is the gate, S is the source, and D is the drain. Detailed Implementation

[0030] To further understand the invention content, features and effects of this utility model, the following embodiments are provided, and detailed descriptions are given in conjunction with the accompanying drawings.

[0031] The structure of this utility model will now be described in detail with reference to the accompanying drawings.

[0032] Please see Figure 1 A low-noise amplifier with selectable performance parameters includes an input matching circuit 1, an interstage matching circuit 2, an output matching circuit 3, a first-stage amplifier circuit 5, and a second-stage amplifier circuit 6. The first-stage amplifier circuit 5 is connected between the input matching circuit 1 and the interstage matching circuit 2, and the second-stage amplifier circuit 6 is connected between the interstage matching circuit 2 and the output matching circuit 3. Both the first-stage amplifier circuit 5 and the second-stage amplifier circuit 6 are 0.15µm GaAs pHEMT stable bias circuits.

[0033] Input matching 1 includes two switching modules 4, an optimal noise input matching module 101, and an optimal gain input matching module 102. The switching module 4 at the input end is connected to the signal input end, and the switching module 4 at the output end is connected to the input end of the first-stage amplifier circuit 5; the optimal noise input matching module 101 and the optimal gain input matching module 102 are located between the two switching modules 4 and are connected in parallel.

[0034] Interstage matching 2 includes two switching modules 4, an optimal noise interstage matching module 201, and an optimal gain interstage matching module 202. The input switching module 4 is connected to the output of the first-stage amplifier circuit 5, and the output switching module 4 is connected to the input of the second-stage amplifier circuit 6. The optimal noise interstage matching module 201 and the optimal gain interstage matching module 202 are located between the two switching modules 4 and are connected in parallel.

[0035] Output matching 3 includes an optimal gain output matching module 301. One end of the optimal gain output matching module 301 is connected to the output terminal of the second-stage amplifier circuit 6, and the other end is connected to the signal output terminal. Output matching 3 has almost no impact on noise performance, so only gain matching needs to be considered for the output.

[0036] The specific structures of the first-stage amplifier circuit 5 and the second-stage amplifier circuit 6 are as follows: Figure 2 As shown, L1 and L2 are connected to the gate and drain bias voltages respectively, serving as gate and drain bias inductors to block RF signals from reaching the DC path; VG and VD are the gate and drain bias voltages respectively; L3 is a feedback inductor to stabilize the circuit, and L3 is an inductor connected from the source to ground.

[0037] The specific structure of the switch module is as follows: Figure 3 As shown, SP1, SP2, SP3, and SP4 are single-pole double-throw (SPD) switches using a series-parallel structure. Port1, Port2, and Port3 correspond to the three ports of the SPD switch, respectively. SP1 and SP3 are connected to SP2 and SP4, respectively, and the sources of SP2 and SP4 are grounded. The specific principle is as follows: to achieve conduction from Port1 to Port2 and deactivation from Port1 to Port3, the control signal at the gate terminal turns on SP1 and SP4, and turns off SP2 and SP3; conversely, to achieve conduction from Port1 to Port3 and deactivation from Port1 to Port2, SP2 and SP3 turn on, and SP1 and SP4 turn off. Port1, Port2, and Port3 correspond to the RF input / output port, noise matching terminal, and gain matching terminal, respectively. The structure and principle of SP5, SP6, SP7, and SP8 in the switch module are the same as described above.

[0038] Optimal noise input matching module 101 Figure 4 As shown, the input terminal is connected to the first-stage amplifier circuit to achieve optimal noise input impedance matching. The optimal noise-enhancing input matching module 101 consists of two capacitors, CI1 and CI2, connected in parallel. The Port3 terminal of the switch module 4 at the input terminal of input matching 1 is connected to capacitors CI1 and CI2. The other end of capacitor CI1 is connected to the Port3 terminal of the switch module 4 at the output terminal of input matching 1. Connecting capacitor CI1 also serves to isolate DC signals from the RF output path. The source of capacitor CI2 is grounded.

[0039] Optimal gain input matching module 102, as shown Figure 5 As shown, the input terminal is connected to the first-stage amplifier circuit, achieving optimal gain input impedance matching. The optimal gain input matching module 102 consists of an inductor L1 and a capacitor CI3, which are connected in parallel. The Port2 terminal of the switch module 4 at the input terminal of input matching 1 is connected to the capacitor CI3 and the inductor L1. The other end of the capacitor CI3 is connected to the Port2 terminal of the switch module 4 at the output terminal of input matching 1. The capacitor CI3 also serves to isolate the DC signal from the RF output path. The source of L1 is grounded.

[0040] Optimal noise level matching module 201 Figure 6 As shown, the first-stage amplifier circuit 5 is connected to the second-stage amplifier circuit 6 to achieve optimal noise level impedance matching. The optimal noise level matching module 201 adopts a T-shaped structure consisting of two capacitors CM1 and CM2 and an inductor LM1. Capacitor CM1 also serves to isolate DC signals from the RF output path. The Port3 terminal of the switching module 4 at the input of the inter-stage matching 2 is connected to capacitor CM1. Capacitor CM1 is connected to the parallel connection point of capacitor CM2 and inductor LM1. The source of capacitor CM2 is grounded, and inductor LM1 is connected to the Port3 terminal of the switching module at the output of the inter-stage matching.

[0041] Optimal gain stage matching module 202 Figure 7 As shown, the first-stage amplifier circuit 5 is connected to the second-stage amplifier circuit 6, achieving optimal inter-stage impedance matching for gain. The optimal gain inter-stage matching module 202 adopts a U-shaped structure consisting of capacitors CM3 and CM4 and an inductor LM2. Capacitor CM3 also serves to isolate DC signals from the RF output path. The Port2 terminal of the switch module 4 at the input of inter-stage matching 2 is connected to inductor LM2 and capacitor CM3. Inductor LM2 and capacitor CM3 are connected in parallel, and capacitor CM3 and capacitor CM4 are connected in series. The sources of inductor LM2 and capacitor CM4 are grounded. The parallel connection point of capacitors CM3 and CM4 is connected to the Port2 terminal of the switch module 4 at the output of inter-stage matching 2.

[0042] Optimal gain output matching module 301, such as Figure 8 As shown, connect the second-stage amplifier circuit 6 to the output terminal, refer to the following for details. Figure 9 The optimal gain output matching module 301 consists of capacitor CO and inductor LO. Capacitor CO also serves to isolate the DC signal from the RF output path. The output terminal of the second-stage amplifier circuit 6 is connected to capacitor CO and inductor LO. Capacitor CO is connected to the signal output terminal, and the source of inductor LO is grounded.

[0043] The working principle of this utility model:

[0044] Reference Figure 9The specific working principle of the circuit is as follows: When the system receives an RF signal and requires optimal noise performance output, an external control signal turns on four GaAs switches (SP3, SP7, SP2, SP6) and turns off four GaAs switches (SP1, SP5, SP4, SP8). This allows the input signal to pass through the optimal noise input matching module 101 to the first-stage amplifier circuit 5, then through the optimal noise inter-stage matching module 201 to the second-stage amplifier circuit 6, and finally through the optimal gain output matching module 301 before being output, thus achieving optimal noise output. When the system receives an RF signal and requires optimal gain performance output, an external control signal turns off four GaAs switches (SP3, SP7, SP2, SP6) and turns on four GaAs switches (SP1, SP5, SP4, SP8). This allows the input signal to pass through the optimal gain input matching module 102 to the first-stage amplifier circuit 5, then through the optimal gain inter-stage matching module 202 to the second-stage amplifier circuit 6, and finally through the optimal gain output matching module 301 before being output, thus achieving optimal gain output.

[0045] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model shall fall within the scope of the technical solution of the present utility model.

Claims

1. A low-noise amplifier with selectable performance parameters, characterized in that, It includes input matching, inter-stage matching, output matching, a first-stage amplifier circuit, and a second-stage amplifier circuit; a first-stage amplifier circuit is provided between the input matching and the inter-stage matching, and a second-stage amplifier circuit is provided between the inter-stage matching and the output matching; The input matching includes two switching modules, an optimal noise input matching module, and an optimal gain input matching module; the switching module at the input end is connected to the signal input end, and the switching module at the output end is connected to the input end of the first-stage amplifier circuit; the optimal noise input matching module and the optimal gain input matching module are located between the two switching modules. Interstage matching includes two switching modules, an optimal noise level interstage matching module, and an optimal gain level interstage matching module; the input switching module is connected to the output of the first-stage amplifier circuit, and the output switching module is connected to the input of the second-stage amplifier circuit; the optimal noise level interstage matching module and the optimal gain level interstage matching module are located between the two switching modules. Output matching includes an optimal gain output matching module; One end of the optimal gain output matching module is connected to the output of the second-stage amplifier circuit, and the other end of the optimal gain output matching module is connected to the signal output.

2. The low-noise amplifier with selectable performance parameters according to claim 1, characterized in that, The first-stage amplifier circuit and the second-stage amplifier circuit are composed of L1, L2 and L3. L1 and L2 are used as gate bias inductors and drain bias inductors, respectively, and L3 is a feedback inductor. L1 and L2 are connected to the gate voltage VG and the drain bias voltage VD, respectively, and the source of L3 is grounded.

3. The low-noise amplifier with selectable performance parameters according to claim 1, characterized in that, The switch module includes SP1, SP2, SP3, and SP4. SP1 and SP3 are connected to SP2 and SP4 respectively, and the sources of SP2 and SP4 are grounded. SP1, SP2, SP3, and SP4 are single-pole double-throw switches, and Port1, Port2, and Port3 can correspond to the three ports of the single-pole double-throw switch respectively.

4. The low-noise amplifier with selectable performance parameters according to claim 1, characterized in that, The optimal noise input matching module consists of capacitors CI1 and CI2. In the input matching, the Port3 terminal of the input switching module is connected to capacitors CI1 and CI2. Capacitor CI1 is connected to the Port3 terminal of the output switching module in the input matching. The source of capacitor CI2 is grounded.

5. The low-noise amplifier with selectable performance parameters according to claim 1, characterized in that, The optimal gain input matching module consists of an inductor L1 and a capacitor CI3. In the input matching, the Port2 terminal of the input switching module is connected to the capacitor CI3 and the inductor L1. The other end of the capacitor CI3 is connected to the Port2 terminal of the output switching module in the input matching; the source of L1 is grounded.

6. The low-noise amplifier with selectable performance parameters according to claim 1, characterized in that, The optimal noise level matching module is a T-shaped structure consisting of capacitors CM1 and CM2 and an inductor LM1. The Port3 terminal of the switching module at the inter-level matching input is connected to capacitor CM1. Capacitor CM1 is connected to the parallel connection point of capacitor CM2 and inductor LM1. The source of capacitor CM2 is grounded. Inductor LM1 is connected to the Port3 terminal of the switching module at the inter-level matching output.

7. The low-noise amplifier with selectable performance parameters according to claim 1, characterized in that, The optimal gain interstage matching module adopts a die-shaped structure consisting of capacitors CM3 and CM4 and an inductor LM2. The Port2 terminal of the input switching module of the interstage matching is connected to the inductor LM2 and capacitor CM3. The inductor LM2 and capacitor CM3 are connected in parallel, and the capacitors CM3 and CM4 are connected in series. The sources of the inductor LM2 and capacitor CM4 are grounded. The parallel connection point of capacitors CM3 and CM4 is connected to the Port2 terminal of the output switching module of the interstage matching.

8. The low-noise amplifier with selectable performance parameters according to claim 1, characterized in that, The optimal gain output matching module consists of capacitor CO and inductor LO. The output of the second-stage amplifier circuit is connected to capacitor CO and inductor LO. Capacitor CO is connected to the signal output terminal, and the source of inductor LO is grounded.

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