Self-locking holding circuit and driving circuit

Abstract

The utility model provides a self-locking holding circuit and a driving circuit. According to the connection relation of the second triode, the potential of the control end of the first triode is equal to the low level under the condition that the second triode is turned on by the level of the enable signal, and the potential of the control end of the second triode is still equal to the low level under the condition that the second triode is turned off by the level of the enable signal. Therefore, under the condition that the enable signal is at different levels, the potential of the control end of the first triode is equal to the low level; the first triodes are PNP type transistors, so that the first triodes are all conducted, and the possibility of keeping the potential of the output signal of the gate driver unchanged is improved; and the output end of the gate driver is usually connected to the control end of the switching tube in the power controllable unit, so that the self-locking holding circuit can improve the possibility of keeping the switching state of the switching tube in the power controllable unit unchanged, and the control reliability of the power controllable unit can be improved.

Description

Technical Field

[0001] This utility model relates to the field of circuit protection technology, and in particular to a self-locking holding circuit and a driving circuit. Background Art

[0002] Currently, the power controllable unit supplies power to the devices it is connected to under the control of the MCU (Micro Control Unit).

[0003] However, if the MCU's program malfunctions, the control signal of the switching transistor in the power controllable unit may change, causing the switching transistor in the power controllable unit to turn off, thus causing the power controllable unit to stop outputting, and consequently causing the devices connected to the power controllable unit to malfunction.

[0004] Therefore, improving the reliability of power controllable units is a technical problem that urgently needs to be solved. Utility Model Content

[0005] In view of this, the present invention provides a self-locking holding circuit and a drive circuit to improve the reliability of the control of the power controllable unit.

[0006] To achieve the above objectives, the present invention provides the following technical solutions:

[0007] This application provides a self-locking circuit, comprising: two transistors and two resistor branches; wherein:

[0008] The first transistor is a PNP type transistor;

[0009] The input terminal of the first transistor receives the supply voltage;

[0010] The output terminal of the first transistor is connected to one end of the first resistor branch, and the connection point serves as the output terminal of the self-locking circuit, which is connected to the input terminal of the gate driver; the other end of the first resistor branch is grounded.

[0011] The control terminal of the first transistor is connected to the input terminal of the second transistor;

[0012] The output terminal of the second transistor is connected to one end of the second resistor branch, and the other end of the second resistor branch is grounded.

[0013] The control terminal of the second transistor serves as the enable terminal of the self-locking circuit, and is used to receive the enable signal.

[0014] Optionally, it also includes: a third transistor; wherein:

[0015] The input terminal of the third transistor is connected to the input terminal of the first transistor;

[0016] The output terminal of the third transistor is connected to the control terminal of the first transistor;

[0017] The control terminal of the third transistor serves as the unlocking terminal of the self-locking circuit, and is used to receive the unlocking reset signal.

[0018] Optionally, it also includes: three resistor branches; wherein:

[0019] The control terminal of the second transistor is connected to the first terminal of the third resistor branch, and the second terminal of the third resistor branch serves as the enable terminal of the self-locking circuit.

[0020] One end of the fourth resistor branch is connected to the output terminal of the first transistor;

[0021] The other end of the fourth resistor branch is connected to one end of the fifth resistor branch, and the connection point is connected to the enable terminal of the self-locking circuit.

[0022] The other end of the fifth resistor branch is grounded.

[0023] Another aspect of this application provides a driving circuit, including: a gate driver, a first signal readout module, and a self-locking circuit as described in any of the preceding aspects of this application; wherein:

[0024] The enable terminal of the self-locking holding circuit is connected to the output terminal of the first signal reading module;

[0025] The input terminal of the first signal reading module is connected to the output terminal of the controller as the enable terminal of the drive circuit;

[0026] The output terminal of the self-locking holding circuit is connected to the input terminal of the gate driver;

[0027] The output terminal of the gate driver serves as the output terminal of the drive circuit and is connected to the control terminal of the switching transistor in the power controllable unit.

[0028] Optionally, it also includes: an overcurrent protection module; wherein:

[0029] The acquisition terminal of the overcurrent protection module receives the actual current value of the switching transistor from the power controllable unit;

[0030] The output terminal of the overcurrent protection module outputs a control signal to the gate driver. The control signal is equal to the turn-off level when the actual current value is greater than a preset value. The turn-off level is a level that can turn off the switching transistor.

[0031] Optionally, the overcurrent protection module includes: a first comparator, a first AND gate, and a preset logic circuit; wherein:

[0032] The non-inverting input of the first comparator serves as the acquisition terminal of the overcurrent protection module, the inverting input of the first comparator receives the first reference voltage, and the output of the first comparator is connected to the input of the preset logic circuit.

[0033] The output terminal of the preset logic circuit is connected to one input terminal of the first AND gate; the potential of the output terminal of the preset logic circuit is opposite to the potential of its own input terminal;

[0034] The other input terminal of the first AND gate is connected to the output terminal of the self-locking circuit, and the output terminal of the first AND gate serves as the output terminal of the overcurrent protection module.

[0035] Optionally, the preset logic circuit includes: a second comparator and a NOR gate; wherein:

[0036] The non-inverting input of the second comparator serves as the input of the preset logic circuit, the inverting input of the second comparator receives the second reference voltage, and the output of the second comparator is connected to one input of the NOR gate.

[0037] The other input terminal of the NOR gate is connected to the non-inverting input terminal of the second comparator, and the output terminal of the NOR gate serves as the output terminal of the preset logic circuit.

[0038] Optionally, the preset logic circuit further includes: a third comparator and a first capacitor branch; wherein:

[0039] The non-inverting input of the third comparator is connected to one end of the first capacitor branch, and the other end of the first capacitor branch is grounded.

[0040] The inverting input of the third comparator receives a third reference voltage.

[0041] The non-inverting input of the third comparator is connected to the output of the second comparator, and the output of the third comparator is connected to one input of the NOR gate.

[0042] or,

[0043] The non-inverting input of the third comparator serves as the input of the preset logic circuit, and the output of the third comparator is connected to the non-inverting input of the second comparator.

[0044] Optionally, the overcurrent protection module further includes: a fourth comparator and a second capacitor branch; wherein:

[0045] The non-inverting input of the fourth comparator is connected to one end of the second capacitor branch, and the other end of the second capacitor branch is grounded.

[0046] The inverting input of the fourth comparator receives the fourth reference voltage;

[0047] The non-inverting input of the fourth comparator is connected to the output of the first comparator, and the output of the fourth comparator is connected to the input of the preset logic circuit.

[0048] or,

[0049] The non-inverting input of the fourth comparator serves as the acquisition terminal of the overcurrent protection module, and the output of the fourth comparator is connected to the non-inverting input of the first comparator.

[0050] Optionally, it may also include: a second signal reading module; wherein:

[0051] The unlocking terminal of the self-locking circuit is connected to the output terminal of the second signal reading module, and the input terminal of the second signal reading module serves as the unlocking terminal of the drive circuit.

[0052] As can be seen from the above technical solution, this utility model provides a self-locking circuit. From the connection relationship of the second transistor, it can be seen that when the enable signal level turns on the second transistor, the potential of the control terminal of the first transistor is low; when the enable signal level turns off the second transistor, the potential of the control terminal of the second transistor is still low. Therefore, when the enable signal is at different levels, the potential of the control terminal of the first transistor is always low. Furthermore, since the first transistor is a PNP type, it is always conducting, thus increasing the probability that the potential of the first transistor's output terminal remains constant, and consequently increasing the probability that the potential of the gate driver's output signal remains constant. Since the output terminal of the gate driver is usually connected to the control terminal of the switching transistor in the power controllable unit, this self-locking circuit increases the probability that the switching state of the switching transistor in the power controllable unit remains constant, thereby improving the reliability of the power controllable unit's control. Attached Figure Description

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0054] Figures 1-3 These are schematic diagrams illustrating three implementations of the self-locking holding circuit provided in this application.

[0055] Figures 4-12These are schematic diagrams illustrating nine different implementations of the driving circuit provided in the embodiments of this application. DETAILED DESCRIPTION

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0057] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] To improve the reliability of the power controllable unit, this application provides a self-locking circuit, the specific structure of which is as follows: Figure 1 As shown, it specifically includes: two transistors and two resistor branches; the connection relationships between the components are described below:

[0059] The input terminal of the first transistor Q1 receives the supply voltage VCC; the output terminal of the first transistor Q1 is connected to one end of the first resistor branch 110, and the connection point serves as the output terminal of the self-locking circuit, which is connected to the input terminal of the gate driver 10; the other end of the first resistor branch 110 is grounded to GND.

[0060] Among them, the first transistor Q1 is a PNP type transistor.

[0061] Additionally, the first resistor branch 110 includes at least one resistor; if the number of resistors is greater than one, all resistors are connected in series and parallel, and the two ends of the branch formed serve as the two ends of the first resistor branch 110; if the number of resistors is equal to one, the two ends of the resistor serve as the two ends of the first resistor branch 110, for example, as... Figure 1 As shown in R1.

[0062] The control terminal of the first transistor Q1 is connected to the input terminal of the second transistor Q2. The output terminal of the second transistor Q2 is connected to one end of the second resistor branch 120, and the other end of the second resistor branch 120 is grounded to GND. The control terminal of the second transistor Q2 serves as the enable terminal of the self-locking circuit and is used to receive the enable signal.

[0063] The second resistor branch 120 includes at least one resistor. If the number of resistors is greater than one, all resistors are connected in series and parallel, and the two ends of the resulting branch serve as the two ends of the second resistor branch 120. If the number of resistors is equal to one, the two ends of the resistor serve as the two ends of the second resistor branch 120. For example, ... Figure 1 As shown in R2 in the diagram.

[0064] Optionally, the second transistor Q2 can be an NPN type transistor or a PNP type transistor. No specific limitation is made here, and it can be determined according to the specific situation. Both are within the protection scope of this application.

[0065] Taking the second transistor Q2 as an NPN type as an example, the working principle of this self-locking circuit is explained in detail below:

[0066] When the enable signal is high, the second transistor Q2 is turned on. When the second transistor Q2 is turned on, the potential at the output terminal of the second transistor Q2 is equal to zero, that is, the potential at the control terminal of the first transistor Q1 is equal to zero, that is, the potential at the control terminal of the first transistor Q1 is low.

[0067] When the enable signal is low, the second transistor Q2 is turned off. When the second transistor Q2 is turned off, the potential at the output terminal of the second transistor Q2 is equal to zero, that is, the potential at the control terminal of the first transistor Q1 is equal to zero, that is, the potential at the control terminal of the first transistor Q1 is low.

[0068] Since the first transistor Q1 is a PNP type transistor, when the potential of the control terminal of the first transistor Q1 is low, the first transistor Q1 is turned on, and a current flows through the first resistor branch 110. As a result, the potential of the output terminal of the first transistor Q1 is equal to the voltage division of the first resistor branch 110. Therefore, as long as the resistance value of the first resistor branch 110 is set properly, the potential of the output terminal of the first transistor Q1 can be made to be high, which means that the potential of the output terminal of the self-locking circuit is also high.

[0069] It should be noted that when the second transistor Q2 is a PNP type transistor, the working principle of this self-locking circuit is similar to that described above and can be derived, so it will not be repeated here.

[0070] As can be seen from the connection relationship of the second transistor Q2, when the enable signal level turns on the second transistor Q2, the potential of the control terminal of the first transistor Q1 is low. When the enable signal level turns off the second transistor Q2, the potential of the control terminal of the second transistor Q2 is still low. Therefore, the potential of the control terminal of the first transistor Q1 is always low regardless of the enable signal level. Since the first transistor Q1 is a PNP transistor, it is always on, which increases the probability that the potential of the output terminal of the first transistor Q1 remains unchanged, thus increasing the probability that the potential of the output signal of the gate driver 10 remains unchanged. Since the output terminal of the gate driver 10 is usually connected to the control terminal of the switching transistor in the power controllable unit, this self-locking circuit can increase the probability that the switching state of the switching transistor in the power controllable unit remains unchanged, thereby improving the reliability of the control of the power controllable unit.

[0071] Another embodiment of this application also provides another implementation of the self-locking holding circuit, the specific structure of which is as follows: Figure 2 As shown, this embodiment, based on the above embodiment, further includes: a third transistor Q3; the connection relationship between this device and other devices is specifically described below:

[0072] The input terminal of the third transistor Q3 is connected to the input terminal of the first transistor Q1; the output terminal of the third transistor Q3 is connected to the control terminal of the first transistor Q1; the control terminal of the third transistor Q3 serves as the unlocking terminal of the self-locking circuit, used to receive the unlocking reset signal.

[0073] Optionally, the third transistor Q3 can be an NPN type transistor or a PNP type transistor. No specific limitation is made here, and it can be determined according to the specific situation. Both are within the protection scope of this application.

[0074] Taking the third transistor Q3 as a PNP type as an example, the working principle of this implementation method will be explained in detail as follows:

[0075] When the unlock reset signal is high, the third transistor Q3 is turned off. When the third transistor Q3 is turned off, the working principle of this embodiment is the same as that of the above embodiment, and will not be repeated here.

[0076] When the unlock reset signal is low, the third transistor Q3 is turned on. When the third transistor Q3 is turned on, if the second transistor Q2 is turned on, then the third transistor Q3, the second transistor Q2, and the branch containing the second resistor branch 120 form a circuit, meaning that current flows through the second resistor branch 120. As a result, the potential of the control terminal of the first transistor Q1 is equal to the voltage division of the second resistor branch 120, that is, the potential of the control terminal of the first transistor Q1 is high. When the third transistor Q3 is turned on, if the second transistor Q2 is turned off, then the potential of the control terminal of the first transistor Q1 is equal to the supply voltage, that is, the potential of the control terminal of the first transistor Q1 is high.

[0077] When the potential at the control terminal of the first transistor Q1 is high, the first transistor Q1 is turned off, and thus the potential at the output terminal of the first transistor Q1 is zero, that is, the potential at the output terminal of the first transistor Q1 is low. In other words, the potential at the output terminal of the self-locking circuit is low, and the self-locking circuit is then reset.

[0078] It should be noted that when the third transistor Q3 is an NPN type transistor, the working principle of this implementation is similar to that described above and can be derived, so it will not be repeated here.

[0079] In this embodiment, by adding a third transistor Q3, the self-locking circuit can be controlled to reset, thereby enabling the self-locking circuit to be reset in a timely manner.

[0080] Another embodiment of this application provides another implementation of the self-locking holding circuit, the specific structure of which is as follows: Figure 3 As shown, this embodiment, based on the above embodiment, further includes: three resistor branches; the connection relationships between the components are as follows:

[0081] The control terminal of the second transistor Q2 is connected to the first terminal of the third resistor branch 130, and the second terminal of the third resistor branch 130 serves as the enable terminal of the self-locking circuit.

[0082] One end of the fourth resistor branch 140 is connected to the output terminal of the first transistor Q1; the other end of the fourth resistor branch 140 is connected to one end of the fifth resistor branch 150, and the connection point is connected to the enable terminal of the self-locking circuit; the other end of the fifth resistor branch 150 is grounded to GND.

[0083] The third resistor branch 130 includes at least one resistor. If the number of resistors is greater than one, all resistors are connected in series and parallel, and the two ends of the resulting branch serve as the two ends of the third resistor branch 130. If the number of resistors is equal to one, the two ends of the resistor serve as the two ends of the third resistor branch 130. For example, ... Figure 3 As shown in R3 in the diagram.

[0084] Additionally, the fourth resistor branch 140 includes at least one resistor; if the number of resistors is greater than one, all resistors are connected in series and parallel, and the two ends of the resulting branch serve as the two ends of the fourth resistor branch 140; if the number of resistors is equal to one, the two ends of the resistor serve as the two ends of the fourth resistor branch 140, for example, as... Figure 3 As shown in R4.

[0085] Furthermore, the fifth resistor branch 150 includes at least one resistor; if the number of resistors is greater than one, all resistors are connected in series and parallel, and the two ends of the resulting branch serve as the two ends of the fifth resistor branch 150; if the number of resistors is equal to one, the two ends of the resistor serve as the two ends of the fifth resistor branch 150, for example, as... Figure 3 As shown in R5.

[0086] Taking the second transistor Q2 as an NPN type transistor as an example, the difference between the working principle of this embodiment and the working principle of the above embodiment is as follows:

[0087] When the first transistor Q1 is turned on, current flows through the first resistor branch 110, and also through the fourth resistor branch 140 and the fifth resistor branch 150. As a result, the potential at the output terminal of the first transistor Q1 is equal to the voltage division of the equivalent resistances of the first resistor branch 110, the fourth resistor branch 140, and the fifth resistor branch 150. Therefore, by properly setting the resistance values ​​of the equivalent resistances of the first resistor branch 110, the fourth resistor branch 140, and the fifth resistor branch 150, the potential at the output terminal of the first transistor Q1 can be made to be high, which also means that the potential at the output terminal of the self-locking circuit is high.

[0088] It should be noted that when the second transistor Q2 is a PNP type transistor, the working principle of this self-locking circuit is similar to that described above and can be derived, so it will not be repeated here.

[0089] Another embodiment of this application provides a driving circuit, the specific structure of which is as follows: Figure 4 As shown, it specifically includes: a gate driver 10, a first signal reading module 20, and a self-locking holding circuit 30 as provided in the above embodiment; the connection relationship between each device is as follows:

[0090] The enable terminal of the self-locking circuit 30 is connected to the output terminal of the first signal reading module 20; the input terminal of the first signal reading module 20 is connected to the output terminal of the controller as the enable terminal of the drive circuit, and is used to receive the enable signal EN; wherein, the first signal reading module 20 is used to read the signal received by the enable terminal of the self-locking circuit 30.

[0091] The output of the self-locking circuit 30 is connected to the input of the gate driver 10; the output of the gate driver 10 serves as the output of the drive circuit and is connected to the control terminal of the switching transistor 02 in the power controllable unit 01.

[0092] In a specific example, such as Figure 4 As shown, the first signal reading module 20 includes: a second AND gate and two comparators; the non-inverting input of the fifth comparator is connected to the non-inverting input of the sixth comparator, and the connection point serves as the input of the first signal reading module 20; the inverting input of the fifth comparator receives a fifth reference voltage, and the inverting input of the sixth comparator receives a sixth reference voltage; the outputs of the fifth and sixth comparators are respectively connected to the two inputs of the second AND gate; the output of the second AND gate serves as the output of the first signal reading module 20.

[0093] When the signal received at the input terminal of the first signal reading module 20 is high, the potential at the non-inverting input terminal of the fifth comparator is greater than the fifth reference voltage, and the potential at the non-inverting input terminal of the sixth comparator is greater than the sixth reference voltage. As a result, the potentials at the output terminals of the fifth and sixth comparators are both high, and consequently, the potential at the output terminal of the second AND gate is high.

[0094] When the signal received at the input terminal of the first signal reading module 20 is low, the potential at the non-inverting input terminal of the fifth comparator is less than the fifth reference voltage, and the potential at the non-inverting input terminal of the sixth comparator is less than the sixth reference voltage. As a result, the potentials at the output terminals of the fifth and sixth comparators are both low, and consequently, the potential at the output terminal of the second AND gate is low.

[0095] It should be noted that in practical applications, the fifth reference voltage and the sixth reference voltage are both set according to the actual situation of the signal received by the input terminal of the first signal reading module 20, and no specific limitation is made here.

[0096] The above is only one implementation of the first signal reading module 20. In practical applications, there are other implementations, including but not limited to this one. No specific limitation is made here. The implementation can be determined according to the specific circumstances, and all of them are within the protection scope of this application.

[0097] Another embodiment of this application provides another implementation of the drive circuit, which is applicable to the case where the self-locking circuit 30 includes a third transistor Q3; the specific structure of this implementation is as follows: Figure 5 As shown, this embodiment, based on the above embodiment, further includes: a second signal reading module 40; the connection relationship between this device and other devices is specifically described as follows:

[0098] The unlocking terminal of the self-locking circuit 30 is connected to the output terminal of the second signal reading module 40. The input terminal of the second signal reading module 40 serves as the unlocking terminal of the drive circuit and is used to receive the unlock reset signal UNLOCK. The second signal reading module 40 is used to read the signal received by the unlocking terminal of the self-locking circuit 30.

[0099] It should be noted that the second signal reading module 40 has the same structure as the first signal reading module 20, and will not be described again here.

[0100] Another embodiment of this application provides another implementation of the driving circuit, the specific structure of which is as follows: Figure 6 As shown, this embodiment, based on the above embodiment, also includes: an overcurrent protection module 50.

[0101] The acquisition terminal of the overcurrent protection module 50 receives the actual current value of the switching transistor 02 from the power controllable unit 01; the output terminal of the overcurrent protection module 50 outputs a control signal to the gate driver 10.

[0102] Specifically, when the actual current value is greater than the preset value, the control signal is equal to the off level, which is the level that can turn off the switch 02; conversely, when the actual current value is less than or equal to the preset value, the control signal is equal to the on level, which is the level that can turn on the switch 02.

[0103] In other words, when the actual current value is greater than the preset value, the output terminal of the overcurrent protection module 50 outputs a control signal at the off level to the gate driver 10, causing the switch 02 to turn off. Conversely, when the actual current value is less than or equal to the preset value, the output terminal of the overcurrent protection module 50 outputs a control signal at the on level to the gate driver 10, causing the switch 02 to turn on.

[0104] The above-mentioned actual current value is greater than the preset value, indicating that the above-mentioned actual current value is large, and vice versa, indicating that the actual current value is small. In practical applications, the above-mentioned actual current value is set according to the actual situation, and no specific limitation is made here.

[0105] In this embodiment, by adding an overcurrent protection module 50, the drive circuit can turn off the switch 02 when the actual current value is large, that is, when the switch 02 has an overcurrent or short-ground GND fault, so that the power controllable unit 01 stops outputting. This reduces the possibility that the power controllable unit 01 will withstand large power and heat up for a long time, thereby reducing the risk of the power controllable unit 01 being burned out.

[0106] Another embodiment of this application provides a specific implementation of an overcurrent protection module 50, which is applicable to the above-mentioned case where the conduction level is high; the specific structure of this implementation is as follows: Figure 6 As shown, it specifically includes: a first comparator 51, a first AND gate 52, and a preset logic circuit 53; the connection relationship of each device is as follows:

[0107] The non-inverting input of the first comparator 51 serves as the acquisition terminal of the overcurrent protection module 50. The inverting input of the first comparator 51 receives the first reference voltage Vref1. The output of the first comparator 51 is connected to the input of the preset logic circuit 53. The output of the preset logic circuit 53 is connected to one input of the first AND gate 52.

[0108] In this circuit, the potential at the output terminal of the preset logic circuit 53 is opposite to the potential at its own input terminal.

[0109] The other input terminal of the first AND gate 52 is connected to the output terminal of the self-locking circuit 30. The output terminal of the first AND gate 52 serves as the output terminal of the overcurrent protection module 50 and is connected to the input terminal of the gate driver 10.

[0110] The working principle of this implementation method is described in detail below:

[0111] When the actual current value is greater than the preset value, the potential of the non-inverting input of the first comparator 51 is greater than the first reference voltage, so the potential of the output of the first comparator 51 is equal to a high level, and then the potential of the output of the preset logic circuit 53 is equal to a low level, that is, the potential of one input of the first AND gate 52 is equal to a low level; since the potential of one input of the first AND gate 52 is equal to a low level, the potential of the output of the first AND gate 52 is equal to a low level, that is, the potential of the output of the overcurrent protection module 50 is equal to a low level, thereby turning off the aforementioned switch 02.

[0112] When the actual current value is less than or equal to the preset value, the potential of the non-inverting input of the first comparator 51 is less than or equal to the first reference voltage, and thus the potential of the output of the first comparator 51 is low. Consequently, the potential of the output of the preset logic circuit 53 is high, that is, the potential of one input of the first AND gate 52 is high. Since the potential of one input of the first AND gate 52 is high, the potential of the output of the first AND gate 52 depends on the potential of the other input of the first AND gate 52. That is, the potential of the output of the overcurrent protection module 50 depends on the potential of the output of the self-locking circuit 30. In other words, if the potential of the output of the self-locking circuit 30 is high, then the potential of the output of the overcurrent protection module 50 is high, thus turning on the switch 02. If the potential of the output of the self-locking circuit 30 is low, then the potential of the output of the overcurrent protection module 50 is low, thus turning off the switch 02.

[0113] In summary, when the actual current value is large, that is, when the switch 02 experiences an overcurrent or short-to-ground fault, the switch 02 can be turned off; when the actual current value is small, that is, when the switch 02 returns to normal, the switch 02 can be re-controlled by the signal output from the output terminal of the self-locking circuit 30.

[0114] It should be noted that the first reference voltage is set according to the actual situation of the signal received by the acquisition terminal of the overcurrent protection module 50, and no specific limitation is made here.

[0115] Another embodiment of this application provides an implementation of the preset logic circuit 53, the specific structure of which is as follows: Figure 7 As shown, it specifically includes: a second comparator 531 and a NOR gate 532; the connection relationship of each device is as follows:

[0116] The non-inverting input of the second comparator 531 serves as the input of the preset logic circuit 53, the inverting input of the second comparator 531 receives the second reference voltage Vref2, and the output of the second comparator 531 is connected to one input of the NOR gate 532.

[0117] The other input of the NOR gate 532 is connected to the non-inverting input of the second comparator 531, and the output of the NOR gate 532 serves as the output of the preset logic circuit 53.

[0118] The working principle of this implementation method is described in detail below:

[0119] When the signal received at the input terminal of the preset logic circuit 53 is high, the potential at the non-inverting input terminal of the second comparator 531 is greater than the second reference voltage, so the output terminal of the second comparator 531 is equal to the high level, and consequently the potential at the output terminal of the NOR gate 532 is equal to the low level.

[0120] When the signal received at the input terminal of the preset logic circuit 53 is low, the potential at the non-inverting input terminal of the second comparator 531 is less than the second reference voltage, so the output terminal of the second comparator 531 is equal to the low level, and consequently the potential at the output terminal of the NOR gate 532 is equal to the high level.

[0121] It should be noted that the second reference voltage is set according to the actual situation of the signal received at the input terminal of the preset logic circuit 53, and no specific limitation is made here.

[0122] The above is only one implementation of the preset logic circuit 53. In practical applications, it includes, but is not limited to, this. It is not specifically limited here, but depends on the specific situation, and all are within the protection scope of this application.

[0123] This embodiment also provides another implementation of the preset logic circuit 53, the specific structure of which is as follows: Figure 8 As shown, this embodiment, based on the above embodiment, further includes: a third comparator 533 and a first capacitor branch 534; the connection relationship between the devices is specifically described below:

[0124] The non-inverting input of the third comparator 533 is connected to one end of the first capacitor branch 534, and the other end of the first capacitor branch 534 is grounded to GND; the inverting input of the third comparator 533 receives the third reference voltage.

[0125] The first capacitor branch 534 includes at least one capacitor. If the number of capacitors is greater than one, all capacitors are connected in series and parallel, and the two ends of the branch are respectively used as the two ends of the first capacitor branch 534. If the number of capacitors is equal to one, the two ends of the capacitor are respectively used as the two ends of the first capacitor branch 534. For example, ... Figure 8 As shown in C1.

[0126] In a specific example, such as Figure 8 As shown, the non-inverting input of the third comparator 533 is connected to the output of the second comparator 531, and the output of the third comparator 533 is connected to one input of the NOR gate 532.

[0127] In this example, when the output of the second comparator 531 is at a high level, the first capacitor branch 534 charges. When the voltage across the first capacitor branch 534 is greater than the third reference voltage, the output of the third comparator 533 is at a high level, and thus the output of the NOR gate 532 is at a high level. When the output of the second comparator 531 is at a low level, the first capacitor branch 534 discharges. When the voltage across the first capacitor branch 534 is less than the third reference voltage, the output of the third comparator 533 is at a low level, and thus the output of the NOR gate 532 is at a low level.

[0128] In another specific example, such as Figure 9 As shown, the non-inverting input of the third comparator 533 serves as the input of the preset logic circuit 53, and the output of the third comparator 533 is connected to the non-inverting input of the second comparator 531.

[0129] In this example, when the potential of the input terminal of the preset logic circuit 53 is high, the first capacitor branch 534 charges. When the voltage across the first capacitor branch 534 is greater than the third reference voltage, the potential of the output terminal of the third comparator 533 is high, that is, the potential of the non-inverting input terminal of the second comparator 531 is high, and thus the potential of the output terminal of the second comparator 531 is high, and consequently the potential of the output terminal of the NOR gate 532 is high. When the potential of the input terminal of the preset logic circuit 53 is low, the first capacitor branch 534 discharges. When the voltage across the first capacitor branch 534 is less than the third reference voltage, the potential of the output terminal of the third comparator 533 is low, that is, the potential of the non-inverting input terminal of the second comparator 531 is low, and consequently the potential of the output terminal of the second comparator 531 is low, and consequently the potential of the output terminal of the NOR gate 532 is low.

[0130] The two examples above illustrate two connection methods for the third comparator 533. No specific limitation is made here, and the method can be determined according to the specific situation. All of them are within the protection scope of this application.

[0131] It should be noted that by adjusting the capacitance value of the first capacitor branch 534, the time difference between the potential change at the non-inverting input terminal of the third comparator 533 and the potential change at the output terminal of the third comparator 533 can be adjusted. In other words, the time difference between the potential change at the input terminal of the preset logic circuit 53 and the potential change at the output terminal of the preset logic circuit 53 can be adjusted, thereby adjusting the delay time of the potential change at the output terminal of the preset logic circuit 53.

[0132] It should also be noted that the third reference voltage is set according to the actual situation of the signal received at the input terminal of the preset logic circuit 53, and no specific limitation is made here.

[0133] In this embodiment, through the third comparator 533 and the first capacitor branch 534, the potential of the output terminal of the preset logic circuit 53 can change after a delay when the potential of its own input terminal changes. This enables the driving circuit to have a delay control function, that is, the aforementioned switch 02 can be turned off after a delay when it experiences an overcurrent or short-ground fault, and when the aforementioned switch 02 returns to normal, it can be controlled by the signal output from the output terminal of the self-locking circuit 30 after a delay, that is, delayed conduction or turn-off.

[0134] Another embodiment of this application provides another implementation of the overcurrent protection module 50, which is applicable when the preset logic circuit 53 does not include a third comparator; the specific structure of this implementation is as follows: Figure 10 As shown, this embodiment, based on the above embodiment, further includes: a fourth comparator 54 and a second capacitor branch 55; the connection relationships between the devices are specifically described below:

[0135] The non-inverting input of the fourth comparator 54 is connected to one end of the second capacitor branch 55, and the other end of the second capacitor branch 55 is grounded to GND; the inverting input of the fourth comparator 54 receives the fourth reference voltage Vref4.

[0136] The second capacitor branch 55 includes at least one capacitor. If the number of capacitors is greater than one, all capacitors are connected in series and parallel, and the two ends of the branch formed serve as the two ends of the second capacitor branch 55. If the number of capacitors is equal to one, the two ends of the capacitor serve as the two ends of the second capacitor branch 55. For example, ... Figure 10 As shown in C2.

[0137] In a specific example, such as Figure 10 As shown, the non-inverting input of the fourth comparator 54 is connected to the output of the first comparator 51, and the output of the fourth comparator 54 is connected to the input of the preset logic circuit 53.

[0138] In another specific example, such as Figure 10 As shown, the non-inverting input of the fourth comparator 54 serves as the acquisition terminal of the overcurrent protection module 50, and the output of the fourth comparator 54 is connected to the non-inverting input of the first comparator 51.

[0139] It should be noted that the working principle of the fourth comparator 54 and the second capacitor branch 55 is the same as that of the third comparator 533 and the first capacitor branch 534, and will not be repeated here.

[0140] The two examples above illustrate two connection methods for the fourth comparator 54. No specific limitations are made here, and the method can be determined according to the specific situation. All of them are within the protection scope of this application.

[0141] Another embodiment of this application provides another implementation of the driving circuit, the specific structure of which is as follows: Figure 12 ( Figure 12 Only Figure 8 As shown in the example (based on the above embodiment), this embodiment further includes a power supply module 56 and a thermal protection module 57. The power supply module 56 is used to draw power from the input terminal of the power controllable unit 01 to provide a power supply voltage to the self-locking circuit 30; the output terminal of the thermal protection module 57 is connected to the input terminal of the gate driver 10, and is used to output the above-mentioned turn-off level when the temperature of the above-mentioned switching transistor 02 is greater than the threshold, so as to turn off the above-mentioned switching transistor 02.

[0142] It should be noted that the above-mentioned shutdown level has been described in detail above and will not be repeated here; the threshold can be set according to the actual situation and is not specifically limited here; the power supply module 56 and the thermal protection module 57 are both very mature technical features in the prior art and will not be described here.

[0143] The features described above in the disclosed embodiments can be substituted or combined with each other, enabling those skilled in the art to implement or use this application. The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to preferred embodiments, it is not intended to limit the present utility model. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present utility model using the disclosed methods and techniques, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present utility model. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall still fall within the protection scope of the technical solution of the present utility model.

Claims

1. A self-locking holding circuit, characterized in that, include: Two transistors and two resistor branches; where: The first transistor is a PNP type transistor; The input terminal of the first transistor receives the supply voltage; The output terminal of the first transistor is connected to one end of the first resistor branch, and the connection point serves as the output terminal of the self-locking circuit, which is connected to the input terminal of the gate driver; the other end of the first resistor branch is grounded. The control terminal of the first transistor is connected to the input terminal of the second transistor; The output terminal of the second transistor is connected to one end of the second resistor branch, and the other end of the second resistor branch is grounded. The control terminal of the second transistor serves as the enable terminal of the self-locking circuit, and is used to receive the enable signal.

2. The self-locking holding circuit according to claim 1, characterized in that, Also includes: Third transistor; where: The input terminal of the third transistor is connected to the input terminal of the first transistor; The output terminal of the third transistor is connected to the control terminal of the first transistor; The control terminal of the third transistor serves as the unlocking terminal of the self-locking circuit, and is used to receive the unlocking reset signal.

3. The self-locking holding circuit according to claim 1 or 2, characterized in that, Also includes: Three resistor branches; among which: The control terminal of the second transistor is connected to the first terminal of the third resistor branch, and the second terminal of the third resistor branch serves as the enable terminal of the self-locking circuit. One end of the fourth resistor branch is connected to the output terminal of the first transistor; The other end of the fourth resistor branch is connected to one end of the fifth resistor branch, and the connection point is connected to the enable terminal of the self-locking circuit. The other end of the fifth resistor branch is grounded.

4. A driving circuit, characterized in that, include: The gate driver, the first signal readout module, and the self-locking holding circuit as described in any one of claims 1 to 3; wherein: The enable terminal of the self-locking holding circuit is connected to the output terminal of the first signal reading module; The input terminal of the first signal reading module is connected to the output terminal of the controller as the enable terminal of the drive circuit; The output terminal of the self-locking holding circuit is connected to the input terminal of the gate driver; The output terminal of the gate driver serves as the output terminal of the drive circuit and is connected to the control terminal of the switching transistor in the power controllable unit.

5. The driving circuit according to claim 4, characterized in that, Also includes: Overcurrent protection module; wherein: The acquisition terminal of the overcurrent protection module receives the actual current value of the switching transistor from the power controllable unit; The output terminal of the overcurrent protection module outputs a control signal to the gate driver. The control signal is equal to the turn-off level when the actual current value is greater than a preset value. The turn-off level is a level that can turn off the switching transistor.

6. The driving circuit according to claim 5, characterized in that, The overcurrent protection module includes: a first comparator, a first AND gate, and a preset logic circuit; wherein: The non-inverting input of the first comparator serves as the acquisition terminal of the overcurrent protection module, the inverting input of the first comparator receives the first reference voltage, and the output of the first comparator is connected to the input of the preset logic circuit. The output terminal of the preset logic circuit is connected to one input terminal of the first AND gate; the potential of the output terminal of the preset logic circuit is opposite to the potential of its own input terminal; The other input terminal of the first AND gate is connected to the output terminal of the self-locking circuit, and the output terminal of the first AND gate serves as the output terminal of the overcurrent protection module.

7. The driving circuit according to claim 6, characterized in that, The preset logic circuit includes: a second comparator and a NOR gate; wherein: The non-inverting input of the second comparator serves as the input of the preset logic circuit, the inverting input of the second comparator receives the second reference voltage, and the output of the second comparator is connected to one input of the NOR gate. The other input terminal of the NOR gate is connected to the non-inverting input terminal of the second comparator, and the output terminal of the NOR gate serves as the output terminal of the preset logic circuit.

8. The driving circuit according to claim 7, characterized in that, The preset logic circuit further includes: a third comparator and a first capacitor branch; wherein: The non-inverting input of the third comparator is connected to one end of the first capacitor branch, and the other end of the first capacitor branch is grounded. The inverting input of the third comparator receives a third reference voltage. The non-inverting input of the third comparator is connected to the output of the second comparator, and the output of the third comparator is connected to one input of the NOR gate. or, The non-inverting input of the third comparator serves as the input of the preset logic circuit, and the output of the third comparator is connected to the non-inverting input of the second comparator.

9. The driving circuit according to claim 6, characterized in that, The overcurrent protection module further includes: a fourth comparator and a second capacitor branch; wherein: The non-inverting input of the fourth comparator is connected to one end of the second capacitor branch, and the other end of the second capacitor branch is grounded. The inverting input of the fourth comparator receives the fourth reference voltage; The non-inverting input of the fourth comparator is connected to the output of the first comparator, and the output of the fourth comparator is connected to the input of the preset logic circuit. or, The non-inverting input of the fourth comparator serves as the acquisition terminal of the overcurrent protection module, and the output of the fourth comparator is connected to the non-inverting input of the first comparator.

10. The driving circuit according to any one of claims 5 to 9, characterized in that, Also includes: Second signal reading module; wherein: The unlocking terminal of the self-locking circuit is connected to the output terminal of the second signal reading module, and the input terminal of the second signal reading module serves as the unlocking terminal of the drive circuit.

Images