Integrated circuit platform

Abstract

The utility model relates to an integrated circuit platform. Methods, systems, and apparatus are provided for normally open GaN high electron mobility transistor (HEMT) integration on a monolithic p-GaN integrated circuit (IC) platform. In particular, the integrated circuit platform may include both enhanced and depletion mode HEMT power devices in a monolithic integrated p-GaN power IC. An exemplary method may include treating at least one of the plurality of p-GaN gates with an in-situ plasma treatment to deactivate Mg in the treated p-GaN gate and deplete Mg of the p-GaN gate. The depleted p-GaN gate may be a gate of a normally-on HEMT in the IC. At least one of the p-GaN gates that is not exposed to the in-situ plasma pretreatment may be a gate of a normally off HEMT in the IC.

Description

Technical Field

[0001] The exemplary embodiments of this disclosure generally relate to high electron mobility transistors (HEMTs), including normally-on gallium nitride (GaN) HEMT integration on a monolithic p-GaN integrated circuit. Background Technology

[0002] GaN is a normally-on technology. p-GaN gates are used to implement normally-off power devices. GaN HEMTs are typically depletion-type transistors, which can be referred to as normally-on HEMTs. However, for some applications, integrated circuits (ICs), sometimes called normally-off enhancement-type transistors, are required for safe operation and circuit simplification. ICs can use p-doped GaN to form the p-GaN gate for normally-off HEMTs (although undoped p-GaN is not necessary, as p-GaN can also be etched), and normally-on HEMTs are obtained on the same platform by etching the p-GaN. However, fabricating an IC with both normally-on and normally-off HEMTs can involve many operations, including the need for p-GaN etching to first define the gate structure. This p-GaN etching can increase the sheet resistance (RsH) of the completed power device.

[0003] The inventors have pointed out several improvements in the prior art and processes, which are the subject of the embodiments described herein. Many of these shortcomings, challenges, and problems have been addressed through the application of effort, ingenuity, and innovation by developing solutions included in the embodiments of this disclosure, some examples of which are described in detail herein. Utility Model Content

[0004] The various embodiments described herein relate to high electron mobility transistors (HEMTs), including normally-on gallium nitride (GaN) HEMT integration on a monolithic normally-off p-GaN integrated circuit.

[0005] According to some embodiments of this disclosure, example methods for manufacturing an integrated circuit platform are provided. The method for manufacturing an integrated circuit platform may include: providing a wafer including an AlGaN layer having a first surface and a p-GaN layer on the AlGaN layer; etching the p-GaN layer to form at least a first p-GaN gate and a second p-GaN gate; depositing a first silicon-based dielectric layer on the first p-GaN gate, the second p-GaN gate, and the AlGaN layer; etching the first silicon-based dielectric layer to expose the second p-GaN gate and a first portion of the AlGaN layer; processing the second p-GaN gate and the first portion of the AlGaN layer with in-situ plasma processing, wherein the in-situ plasma processing deactivates magnesium in the second p-GaN gate to form a depleted p-GaN gate; and forming at least a first normally-off HEMT and at least a first normally-on HEMT, wherein the gate of the normally-off HEMT is the first p-GaN gate, and wherein the gate of the normally-on HEMT is a depleted p-GaN gate.

[0006] In some embodiments, forming a first normally-off HEMT includes forming a plurality of alumina layers; and forming a first normally-on HEMT includes a single alumina layer.

[0007] In some embodiments, the first silicon-based dielectric layer has a thickness of 70 nm.

[0008] In some embodiments, in-situ plasma processing includes diffusing hydrogen into the second p-GaN gate and the AlGaN layer.

[0009] In some embodiments, in-situ plasma treatment deactivates magnesium in a first portion of the AlGaN layer.

[0010] In some embodiments, forming a first normally off HEMT further includes depositing a metallization layer associated with the first normally off HEMT gate, the first normally off HEMT source, and the first normally off HEMT drain; and forming a first normally open HEMT further includes depositing a metallization layer associated with the first normally open HEMT gate, the first normally open HEMT source, and the first normally open HEMT drain.

[0011] In some embodiments, forming a first normally-off HEMT further includes depositing at least a first metal shielding layer; and forming a first normally-on HEMT further includes depositing at least a second metal shielding layer.

[0012] In some embodiments, the depleted p-GaN gate of the first normally open HEMT has a gradual capacitance trend as voltage increases.

[0013] In some embodiments, the p-GaN gate of the first normally off HEMT has a Schottky capacitance trend that increases with voltage.

[0014] In some embodiments, the wafer further includes a TiN layer covering the p-GaN layer; and a first p-GaN gate of the first normally off HEMT is covered by a first portion of the TiN layer; and wherein the depleted p-GaN gate of the first normally on HEMT is covered by a second TiN layer.

[0015] According to some embodiments of this disclosure, an example integrated circuit platform is provided. This integrated circuit platform may include normally-off HEMTs and normally-on HEMTs; wherein the normally-off HEMT includes a p-doped GaN gate on an AlGaN layer; and wherein the normally-on HEMT includes a depleted p-GaN gate on the AlGaN layer that has been depleted by in-situ plasma treatment.

[0016] In some embodiments, a normally closed HEMT further includes a plurality of alumina layers; and a normally open HEMT further includes a single alumina layer.

[0017] In some embodiments, the first silicon-based dielectric layer has a thickness of 70 nm.

[0018] In some embodiments, the depleted p-GaN gate comprises Mg-H formed by diffusing hydrogen into a second p-GaN gate.

[0019] In some embodiments, the first part of the AlGaN exposure to in-situ plasma treatment includes deactivated magnesium.

[0020] In some embodiments, a normally-off HEMT further includes a metallization layer associated with a normally-off HEMT gate, a normally-off HEMT source, and a normally-off HEMT drain; and a normally-on HEMT further includes a metallization layer associated with a normally-on HEMT gate, a normally-on HEMT source, and a normally-on HEMT drain.

[0021] In some embodiments, a normally-off HEMT further includes at least a first metal shielding layer; and a normally-open HEMT further includes at least a second metal shielding layer.

[0022] In some embodiments, the depleted p-GaN gate of a normally open HEMT has a gradual capacitance trend as voltage increases.

[0023] In some embodiments, the p-GaN gate of a normally-off HEMT exhibits a Schottky capacitance trend that increases with voltage.

[0024] In some embodiments, the first p-GaN gate is covered by a first TiN layer; and the depleted p-GaN gate is covered by a second TiN layer.

[0025] According to some embodiments of this disclosure, a method for manufacturing an integrated circuit platform is provided, comprising:

[0026] A wafer is provided, the wafer comprising an AlGaN layer having a first surface and a p-GaN layer on a first surface of the AlGaN layer;

[0027] The p-GaN layer is etched to form at least a first p-GaN gate and a second p-GaN gate;

[0028] A first silicon-based dielectric layer is deposited on the first p-GaN gate, the second p-GaN gate, and the AlGaN layer;

[0029] The first silicon-based dielectric layer is etched to expose a first portion of the AlGaN layer and the second p-GaN gate;

[0030] The second p-GaN gate and the first portion of the AlGaN layer are treated with in-situ plasma processing, wherein the in-situ plasma processing deactivates magnesium in the second p-GaN gate to form a depleted p-GaN gate; and

[0031] At least a first normally off HEMT and at least a first normally on HEMT are formed, wherein the gate of the first normally off HEMT is the first p-GaN gate, and wherein the gate of the first normally on HEMT is the depleted p-GaN gate.

[0032] In some embodiments, forming the first normally closed HEMT includes forming a plurality of alumina layers; and

[0033] The formation of the first normally open HEMT comprises a single alumina layer.

[0034] In some embodiments, the first silicon-based dielectric layer has a thickness of 70 nm.

[0035] In some embodiments, the in-situ plasma processing includes diffusing hydrogen into the second p-GaN gate and the AlGaN layer.

[0036] In some embodiments, the in-situ plasma treatment deactivates magnesium in the first portion of the AlGaN layer.

[0037] In some embodiments, forming the first normally-off HEMT further includes depositing a metallization layer, the metallization layer being associated with the first normally-off HEMT gate, the first normally-off HEMT source, and the first normally-off HEMT drain; and

[0038] The formation of the first normally open HEMT also includes depositing a metallization layer, which is associated with the first normally open HEMT gate, the first normally open HEMT source, and the first normally open HEMT drain.

[0039] In some embodiments, forming the first normally-off HEMT further includes depositing at least a first metal shielding layer; and

[0040] The formation of the first normally open HEMT also includes depositing at least a second metal shielding layer.

[0041] In some embodiments, the depleted p-GaN gate of the first normally open HEMT has a gradual capacitance trend as voltage increases.

[0042] In some embodiments, the p-GaN gate of the first normally off HEMT has a Schottky capacitance trend that increases with voltage.

[0043] In some embodiments, providing the wafer further includes providing a TiN layer covering the p-GaN layer; and

[0044] The first p-GaN gate of the first normally off HEMT is covered by a first portion of the TiN layer; and the depleted p-GaN gate of the first normally on HEMT is covered by a second TiN layer.

[0045] According to some embodiments of this disclosure, an integrated circuit platform is provided, including:

[0046] Normally closed HEMTs and normally open HEMTs;

[0047] The normally-off HEMT includes a p-doped GaN gate on an AlGaN layer; and

[0048] The normally open HEMT includes a depleted p-GaN gate on the AlGaN layer, which is deactivated by in-situ plasma treatment.

[0049] In some embodiments, the normally closed HEMT further includes a plurality of alumina layers; and

[0050] The normally open HEMT further includes a single alumina layer.

[0051] In some embodiments, the integrated circuit platform further includes a first silicon-based dielectric layer, wherein the first silicon-based dielectric layer has a thickness of 70 nm.

[0052] In some embodiments, the depleted p-GaN gate comprises Mg-H, which is formed by diffusing hydrogen into the depleted p-GaN gate.

[0053] In some embodiments, the integrated circuit platform further includes a first portion of the AlGaN layer, wherein the first portion of the AlGaN layer includes deactivated magnesium derived from exposure to the in-situ plasma processing.

[0054] In some embodiments, the normally-off HEMT further includes a metallization layer associated with the normally-off HEMT gate, normally-off HEMT source, and normally-off HEMT drain; and

[0055] The normally open HEMT further includes a metallization layer, which is associated with the normally open HEMT gate, normally open HEMT source, and normally open HEMT drain.

[0056] In some embodiments, the normally-off HEMT further includes at least a first metal shielding layer; and

[0057] The normally open HEMT further includes at least a second metal shielding layer.

[0058] In some embodiments, the depleted p-GaN gate of the normally open HEMT has a gradual capacitance trend as voltage increases.

[0059] In some embodiments, the p-doped GaN gate of the normally off HEMT exhibits a Schottky capacitance trend with increasing voltage.

[0060] In some embodiments, the p-doped GaN gate is covered by a first TiN layer; and the depleted p-GaN gate is covered by a second TiN layer.

[0061] The above summary is provided only for the purpose of summarizing some exemplary embodiments to provide a basic understanding of some aspects of this disclosure. Therefore, it will be understood that the above embodiments are merely examples and should not be construed as narrowing the scope or spirit of this disclosure in any way. It will also be understood that, in addition to those summarized herein, the scope of this disclosure covers many potential embodiments, some of which will be further described below. Attached Figure Description

[0062] Therefore, certain exemplary embodiments of this disclosure have been generally described, and reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0063] Figure 1 The illustration shows a first cross-sectional view of a block diagram of a first exemplary power device according to one or more embodiments of the present disclosure;

[0064] Figure 2 An example flowchart illustrating an operation for manufacturing a power device according to one or more embodiments of the present disclosure is shown;

[0065] Figures 3A-3F The illustration shows an example block diagram associated with operations for manufacturing power devices according to one or more embodiments of the present disclosure;

[0066] Figure 4 The figure illustrates a voltage diagram of the first capacitance associated with an undoped p-GaN gate;

[0067] Figure 5 The illustration shows a first capacitor versus voltage diagram associated with one or more embodiments of this disclosure; and

[0068] Figures 6A-6B The illustration shows a current versus voltage diagram associated with one or more embodiments of this disclosure. Detailed Implementation

[0069] Some embodiments of this disclosure will now be described more fully herein with reference to the accompanying drawings, which illustrate some, but not all, of the embodiments of this disclosure. In fact, various embodiments of this disclosure may be implemented in many different forms and should not be considered as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The same reference numerals always refer to the same elements.

[0070] As used herein, the term “comprising” means including but not limited to, and should be interpreted in the manner commonly used in the patent context. The use of broader terms such as including, comprising, and having should be understood to be supported by narrower terms such as consisting of, substantially consisting of, and substantially constituted by.

[0071] The phrases “in various embodiments,” “in one embodiment,” “according to one embodiment,” “in some embodiments,” etc., generally mean that the specific feature, structure, or characteristic following the phrase may be included in at least one embodiment of this disclosure, and may be included in more than one embodiment of this disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0072] The terms “example” or “exemplary” are used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” should not necessarily be construed as preferred or superior to other implementations.

[0073] If the specification states that a component or feature "may," "can," "is able to," "should," "will," "preferably," "possibly," "typically," "optionally," "for example," "often," "may" (or other such language) include or have a feature, then the specific component or feature is not required to include or have that feature. Such a component or feature may be optionally included in some embodiments or may be excluded.

[0074] Overview

[0075] Various embodiments of this disclosure relate to integrating normally-on GaN HEMTs into normally-off p-GaN. Specifically, this disclosure includes obtaining both enhancement-mode (E-type) HEMT power devices and depletion-mode (D-type) HEMT power devices in a monolithic integrated p-GaN power IC.

[0076] For GaN HEMT devices, undoped GaN devices are normally on because GaN inherently sets the device to normally on. To achieve normally off devices, a magnesium (Mg) doped GaN layer can be formed to create a p-GaN layer. The p-doped gate allows for electron depletion, resulting in a normally off device. Normally off HEMT power devices require a voltage applied to the gate to switch the HEMT power device to the on state and the on-state current.

[0077] The structure of an IC with a GaN HEMT includes a silicon substrate under a GaN buffer, which is located beneath an AlGaN layer. This AlGaN layer allows conduction between the source and gate of the HEMT.

[0078] This conduction originates from the electron concentration beneath the AlGaN layer. When a voltage is applied to the drain, conduction occurs between the gate and the drain.

[0079] Integrating depletion-mode (D-type) HEMTs co-integrated on a p-GaN-based GaN-on-silicon integrated circuit (IC) platform enables IC designs with enhanced functionality and performance. However, with p-GaN, the entire surface of the AlGaN in a D-type HEMT is destroyed due to p-GaN etching. Furthermore, the gate metal used for D-type HEMTs is the same as that used for E-type HEMTs, thus limiting the adjustability of the threshold voltage of D-type devices.

[0080] One advantage of this disclosure is that it integrates the D-type structure into a monolithic IC, avoiding p-GaN etching that could cause surface damage to the AlGaN layer and also result in unstable voltage threshold (Vth). Embodiments of this disclosure allow for adjustments to Vth by modifying certain operations described herein. Additionally or alternatively, normally-on power devices can be manufactured together with normally-off power devices on a single production line, unlike conventional methods that require different manufacturing operations and production lines.

[0081] The power devices disclosed herein can be used in a wide range of applications. For example, various embodiments of this disclosure can be used in DC-DC converter applications.

[0082] Example methods, systems, and devices

[0083] Figure 1The illustration shows a first cross-sectional view of a block diagram of a first exemplary power device according to one or more embodiments of the present disclosure. Figure 1 The exemplary power device illustrated in the figure is manufactured after the exemplary method has been completed, and is further described herein.

[0084] like Figure 1 As illustrated, power device 100 may include two p-GaN HEMTs. A normally off p-GaN HEMT 102 is shown on the left side of the figure, while a normally on depleted p-GaN HEMT 104 is shown on the right side. The normally off p-GaN HEMT 102 and the normally on depleted p-GaN HEMT 104 may be on top of a silicon substrate layer 110, which is located below a GaN layer 112, which is located below an AlGaN layer 114. Above the AlGaN layer are a p-GaN gate 120 and a depleted p-GaN gate 122. The p-GaN gate 120 and the depleted p-GaN gate 122 may initially be portions of a p-GaN layer, which is etched to leave these two regions. As further described herein, the depleted p-GaN gate 122 is plasma-treated to form the depleted p-GaN gate 122 from the associated portion remaining after the etching of the p-GaN layer. Plasma treatment is optional, and the p-GaN can be depleted by diffusing hydrogen into the region during plasma treatment to deplete the Mg in the region. Hydrogen diffusion can also extend into the AlGaN layer 114 near the depleted p-GaN gate 122. The depleted p-GaN gate 122, as part of the depleted p-GaN gate, allows for normally-off functionality.

[0085] The normally-off p-GaN HEMT102 includes a gate, a source, and a drain. The metal contact of the gate of the normally-off p-GaN HEMT102 is illustrated as metallization layer 150A. The metal contact of the source of the normally-off p-GaN HEMT102 is illustrated as metallization layer 152A. The metal contact of the drain of the normally-off p-GaN HEMT102 is illustrated as metallization layer 154A. The normally-off p-GaN HEMT102 may also include one or more other metal shields 156 (e.g., 156A) for controlling the electric field generated when the power device is operating.

[0086] The normally-on depleted p-GaN HEMT104 includes a gate, a source, and a drain. The metal contact of the gate of the normally-on depleted p-GaN HEMT104 is illustrated as metallization layer 150B. The metal contact of the source of the normally-on depleted p-GaN HEMT104 is illustrated as metallization layer 152B. The metal contact of the drain of the normally-on depleted p-GaN HEMT104 is illustrated as metallization layer 154B. The normally-on depleted p-GaN HEMT104 may also include one or more other metal shields 156 (e.g., 156B) for controlling the electric field generated when the power device is operating.

[0087] Power devices may also include multiple aluminum oxide (Al2O3) layers (e.g., 130A, 130B, 130C) and multiple silicon-based dielectric layers (e.g., silicon oxide, silicon nitride, etc.) (e.g., 140A, 140B, 140C, 140D, 140E, 142A, 142B, 142C). The aforementioned aluminum oxide and silicon-based dielectric layers may be deposited one layer at a time and etched to allow one or more surfaces to be exposed, thus allowing more layers to be deposited within one or more portions of the layers removed by etching.

[0088] Figure 2 An example flowchart illustrating an operation for manufacturing a power device according to one or more embodiments of the present disclosure is shown.

[0089] At operation 200, a wafer with an AlGaN layer covered by a p-GaN layer is provided. The wafer may also include a GaN layer 112 beneath the AlGaN 114, and a silicon substrate layer 110 beneath the GaN layer 112. The p-GaN layer may be used to form a p-GaN gate 120 and a region of a p-GaN gate 122 that will become depleted.

[0090] At operation 202, the p-GaN layer is etched to form a gate. Multiple gates can be etched from the p-GaN layer. In various embodiments, a first gate can be etched as p-GaN gate 120, and a second gate can be etched as a gate to become a depleted p-GaN gate 122. The p-GaN layer can be etched in Cl2 / O2. In various embodiments, a TiN layer may also be present above the p-GaN layer (e.g., a self-aligned gate method). The TiN layer can be etched with BCl3. In various embodiments, performing the etching may include wet etching of the TiN side recesses using SiN HM, removal of photoresist in O2 / N2 plasma, and removal of polymer in an EKC265.

[0091] At operation 204, the exposed surfaces are cleaned. This cleaning operation cleans the exposed surfaces of the first and second gates and the AlGaN layer 114. In various embodiments, cleaning may utilize hot HCl and / or HF.

[0092] At operation 206, a first alumina layer is deposited. The first alumina layer 130 may be deposited over the first gate 120, the second gate 122A, and the AlGaN layer 114. In various embodiments, the alumina layer may be Al2O3 with a thickness of up to 5 nm, heated to 300°C via heat treatment or plasma treatment. This thickness can be varied. Other examples may include 2.5 nm to 7.5 nm.

[0093] At operation 208, a first silicon-based dielectric layer is deposited. In various embodiments, the first silicon-based dielectric layer 140 may be a PECVD SiH4-based SiO2 with a thickness of 260 nm.

[0094] The illustration of the wafer after operation 208 is shown in... Figure 3A middle.

[0095] In operation 210, the first silicon-based dielectric layer and the first aluminum oxide layer are etched to expose the second gate contact 122A. Etching of the first silicon-based dielectric layer 140 and the first aluminum oxide layer 130 can remove these layers on the first portion 310 of the wafer to expose the AlGaN layer 114 and the second gate 122A within this first portion 310. This etching can be performed using CF4 EP on the AlGaN layer 114, removal of photoresist using O2 / N2 plasma, and / or removal of polymer in an EKC265.

[0096] At operation 212, in-situ plasma treatment is performed. In-situ plasma treatment can be applied to the first exposed portion 310 of the second gate 122A and the AlGaN layer 114. In-situ plasma treatment can utilize NH3 plasma treatment. In-situ plasma treatment accelerates Mg deactivation by introducing hydrogen (H) to form Mg-H complexes, and this deactivates the doped Mg in the exposed p-GaN layer of the second gate 122A to form a depleted p-GaN gate 122, which reduces the sheet resistance (RsH) of the AlGaN layer 114. In-situ plasma treatment also deactivates some of the Mg in the AlGaN layer 114. The deactivation of Mg in the p-GaN enables the realization of an intrinsic GaN layer.

[0097] In various embodiments, in-situ plasma processing is performed on the wafer, for example, in a direct plasma chamber with an NH3 / N2 flow and a power range between 150 and 300 W. Additionally or alternatively, temperatures in the range of 300°C can accelerate the deactivation of Mg by introducing hydrogen. Vth can then be further reduced by modifying the conditions of operation 212 to diffuse additional hydrogen and / or deactivate a greater amount of Mg.

[0098] The illustration of the wafer after operation 212 is shown in... Figure 3B middle.

[0099] At operation 214, a second aluminum oxide layer is deposited. The second aluminum oxide layer 132 (Al2O3) is deposited. For the first portion 310 of the wafer, the second aluminum oxide layer 132 will cover the AlGaN layer 114 and the depleted p-GaN gate 122. Outside the first portion 310 of the wafer, the second aluminum oxide layer 132 is deposited on the first silicon-based dielectric layer 140.

[0100] In various embodiments, the second alumina layer 132 may have a different thickness than the preceding alumina layer 130. This could be a second alumina layer 132 with a second alumina layer thickness, while the first alumina layer 130 has a first alumina layer thickness. The second alumina layer thickness could be, for example, 3 nm, 5 nm, 7 nm, etc. Variations in the thickness of the second alumina layer 132 may be associated with different gate leakage rates. Gate leakage will also depend on other aspects of the power device, including the shape of the p-GaN gate (e.g., 120). In various embodiments, the second alumina layer 132 may be an ALD Al2O3 deposition.

[0101] At operation 216, a second silicon-based dielectric layer is deposited. The second silicon-based dielectric layer 142 can be deposited. The second silicon-based dielectric layer 142 can be used to seal the depleted p-GaN gate 122. In various embodiments, the second silicon-based dielectric layer can be PECVD-deposited SiH4-based SiO2 with a thickness of 70 nm.

[0102] The illustration of the wafer after operation 216 is shown in... Figure 3C middle.

[0103] At operation 218, one or more silicon-based dielectric layers and one or more aluminum oxide layers are etched to expose the second gate. Etching may be performed at a second portion 320 of the wafer, which is etched to remove the second silicon-based dielectric layer 142 and the second aluminum oxide layer 132 to expose the depleted p-GaN gate 122. This etching may utilize CF4 EP on the aluminum oxide layer 132, removal of photoresist with O2 / N2 plasma, and / or removal of polymer in an EKC265.

[0104] The illustration of the wafer after operation 218 is shown in... Figure 3D middle.

[0105] At operation 220, one or more silicon-based dielectric layers and one or more aluminum oxide layers are etched to expose the first gate. Etching may be performed at a third portion 330 of the wafer, which is etched to remove the first silicon-based dielectric layer 140 and the second silicon-based dielectric layer 142, as well as the first aluminum oxide layer 130 and the second aluminum oxide layer 132, to expose the p-GaN gate 120. This etching may utilize CF4 EP, photoresist removal with O2 / N2 plasma, polymer removal in EKC265, and / or pre-metal cleaning in HCl.

[0106] The illustration of the wafer after operation 220 is shown in... Figure 3E middle.

[0107] At operation 222, a metallization layer is deposited to form a gate contact. One or more metallization layers may be deposited to form a gate contact 150A for the p-GaN gate 120 and a gate contact 150B for the depleted p-GaN contact 122. This metallization layer deposition may utilize TiN / AlCu / TiN metallization and / or tapered etching. Gate contacts 150A and 150B may be self-aligned.

[0108] The illustration of the wafer after operation 222 is shown in... Figure 3F middle.

[0109] At operation 224, a third silicon-based dielectric layer is deposited. In various embodiments, the third silicon-based dielectric layer 144 may be deposited. In various embodiments, the third silicon-based dielectric layer may be PECVD SiH4-based SiO2.

[0110] At operation 226, etching is performed for the ohmic contact. Etching for the ohmic contact may include etching the silicon-based dielectric layer and / or aluminum oxide layer to expose the AlGaN layer 114 for fabricating the source contact 152 and drain contact 154 of the power device. This etching may utilize CF4 EP, BCl3 recesses on the AlGaN, removal of photoresist with O2 / N2 plasma, removal of polymer in an EKC265, and / or pre-metal cleaning with HCl.

[0111] At operation 228, one or more metallization layers are deposited for ohmic contacts (and shielding). This metallization layer can be deposited to form source contacts 152A and drain contacts 154A of normally off p-GaN HEMT102, and source contacts 152B and drain contacts 154B of normally on depleted p-GaN HEMT104. In various embodiments, this metallization layer may also include one or more deposited shielding metal portions. This metallization layer deposition can utilize TiN / AlCu / TiN metallization and / or taper etching.

[0112] At operation 230, annealing is performed. Annealing can be ohmic annealing. In various embodiments, ohmic annealing can be performed at 560°C.

[0113] The illustration of the wafer after operation 230 is shown in... Figure 1 middle.

[0114] In various embodiments, the operations following in-situ plasma treatment can be referred to as forming the gate, source, and drain of the HEMT, because each of these operations forms one or more structures required for forming the HEMT power device 100.

[0115] It will be understood that the above operations can be repeated, omitted, or modified. For example, the deposition of one or more alumina layers may be omitted in various embodiments.

[0116] Figures 3A-3F The illustration shows a block diagram associated with operations for manufacturing power devices according to one or more embodiments of the present disclosure.

[0117] Figure 3A The illustration shows the chip after operation 208 is performed.

[0118] Figure 3B The illustration shows the chip after operation 212.

[0119] Figure 3C The illustration shows the chip after operation 216 is performed.

[0120] Figure 3D The illustration shows the chip after operation 218 is performed.

[0121] Figure 3E The illustration shows the chip after operation 220 is performed.

[0122] Figure 3F The illustration shows the chip after operation 222 is performed.

[0123] It will be understood that various embodiments may include the independent fabrication of normally-on depleted p-GaN HEMT power devices without one or more other power devices. Various embodiments may include fabricating multiple power devices on a single wafer, such as multiple normally-off p-GaN HEMT power devices and multiple normally-on depleted p-GaN HEMT power devices.

[0124] In various embodiments, in-situ plasma processing can be omitted, and instead, a wafer can be provided having a first portion of doped p-GaN (e.g., the portion containing gate 120) and a second portion of undoped GaN (e.g., the portion containing gate 122). This can occur via one or more of the following operations: growing an undoped GaN layer, and then performing selective ion implantation to selectively dope the first portion of this GaN layer with Mg while leaving the second portion of the GaN layer undoped. The undoped portion can then be used to form a normally-on HEMT.

[0125] Figure 4 The diagram illustrates a first capacitance versus voltage plot associated with a doped p-GaN gate and an undoped GaN gate. As described herein, a doped p-GaN gate can be used to form a normally-off HEMT power device. An undoped GaN gate can be used to conventionally form a normally-on HEMT power device. The first curve 410 is a capacitance versus voltage plot for the p-GaN gate, depicting a Schottky capacitance trend. The second curve 420 is associated with an undoped GaN gate, depicting a flattened capacitance plot.

[0126] In the Schottky capacitance trend, the trend initially rises sharply with an applied positive bias voltage, and then decreases with increasing voltage. This trend depends on the p-GaN activation, which in turn depends on the Mg concentration and the composition of the p-GaN and AlGaN layers. In a normally-on device with an undoped GaN gate, it is normally open at 0 volts. Undoped GaN has a capacitance that increases gradually with increasing voltage.

[0127] Figure 5 The illustration shows a first capacitor versus voltage diagram associated with one or more embodiments of this disclosure. Figure 5 The illustration shows a first curve 510 associated with a doped p-GaN gate, which can be used to form a normally-off HEMT power device as described herein. The illustration also shows a second curve 520 associated with a depleted p-GaN gate used in a normally-on HEMT power device. Curve 520 depicts a flat capacitance curve.

[0128] As can be seen from comparison curves 420 and 520, the depleted p-GaN gate of this disclosure can have the same flat capacitance curve as a conventional undoped GaN gate.

[0129] Figures 6A-6B The illustration shows a current versus voltage diagram associated with one or more embodiments of this disclosure. Figure 6A A semi-logarithmic scale was used for the current on the y-axis, while Figure 6B A linear scale was used for the current on the y-axis. Curves 610A and 610B are associated with the p-GaN gate. Curves 620A and 620B are associated with the depleted p-GaN gate. In-situ plasma treatment allows for a decrease in the voltage threshold, which is illustrated as a negative offset from 610A to 620A and from 610B to 620B.

[0130] It should be readily appreciated that, in addition to those explicitly described herein, embodiments of the methods, systems, and apparatus described herein can be configured in various additional and alternative ways. In various embodiments, this includes adding or omitting one or more operations. It should also be readily appreciated that the accompanying drawings are not drawn to scale, and therefore certain portions of the drawings may differ from those depicted.

[0131] in conclusion

[0132] The operations and / or functions of this disclosure have been described herein, such as in flowcharts. Flowchart frames support combinations of means for performing specific operations and / or functions, as well as combinations of operations and / or functions for performing specific operations and / or functions.

[0133] While this specification contains numerous specific embodiments and implementation details, these should not be construed as limiting any disclosure or scope of the claimed protection, but rather as descriptions of specific features characteristic of particular embodiments of the particular disclosure. Certain features described herein in the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations, and even claimed in this manner initially, one or more features from a claimed combination may be excluded from the combination in some cases, and the claimed combination may involve sub-combinations or variations thereof.

[0134] Although operations and / or functions are illustrated in a specific order in the accompanying drawings, this should not be construed as requiring such operations and / or functions to be performed in the specific order shown or sequentially, or as requiring the performance of all illustrated operations to achieve the desired result. In some cases, operations and / or functions in an alternative order may be advantageous. In some cases, the actions listed in the claims may be performed in a different order and still achieve the desired result. Therefore, while specific embodiments of the subject matter have been described, other embodiments are also within the scope of the following claims.

[0135] While this detailed description has illustrated some embodiments of the present invention, the appended claims cover other embodiments of the present invention that differ from the described embodiments, based on various modifications and improvements.

[0136] In the appended claims, unless the specific terms “means for…” or “steps for…” are used in a given claim, they are not intended to be interpreted under paragraph 6 of 35 USC §112.

Claims

1. An integrated circuit platform, characterized in that, The integrated circuit platform includes: Normally closed HEMTs and normally open HEMTs; The normally-off HEMT includes a p-doped GaN gate on an AlGaN layer; and The normally open HEMT includes a depleted p-GaN gate on the AlGaN layer, which is deactivated by in-situ plasma treatment.

2. The integrated circuit platform according to claim 1, characterized in that, The normally closed HEMT also includes multiple alumina layers; and The normally open HEMT further includes a single alumina layer.

3. The integrated circuit platform according to claim 1, characterized in that, The integrated circuit platform also includes a first silicon-based dielectric layer, wherein the first silicon-based dielectric layer has a thickness of 70 nm.

4. The integrated circuit platform according to claim 1, characterized in that, The depleted p-GaN gate includes Mg-H, which is formed by diffusing hydrogen into the depleted p-GaN gate.

5. The integrated circuit platform according to claim 1, characterized in that, The integrated circuit platform also includes a first portion of the AlGaN layer, wherein the first portion of the AlGaN layer includes deactivated magnesium derived from exposure to the in-situ plasma processing.

6. The integrated circuit platform according to claim 1, characterized in that, The normally-off HEMT further includes a metallization layer, which is associated with the normally-off HEMT gate, normally-off HEMT source, and normally-off HEMT drain; and The normally open HEMT further includes a metallization layer, which is associated with the normally open HEMT gate, normally open HEMT source, and normally open HEMT drain.

7. The integrated circuit platform according to claim 6, characterized in that, The normally closed HEMT further includes at least a first metallic shielding layer; and The normally open HEMT further includes at least a second metal shielding layer.

8. The integrated circuit platform according to claim 1, characterized in that, The depleted p-GaN gate of the normally open HEMT exhibits a gradual capacitance trend as voltage increases.

9. The integrated circuit platform according to claim 1, characterized in that, The p-doped GaN gate of the normally off HEMT exhibits a Schottky capacitance trend with increasing voltage.

10. The integrated circuit platform according to claim 1, characterized in that, The p-doped GaN gate is covered by a first TiN layer; and the depleted p-GaN gate is covered by a second TiN layer.

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