Wafer cutting channel structure and corresponding semiconductor chip

Abstract

The utility model provides a wafer cutting channel structure and a corresponding semiconductor chip. The wafer cutting channel structure comprises a device part, a sealing ring, a passivation layer and a cutting channel. The device part comprises a silicon substrate and a laminated structure, the laminated structure is arranged at the upper end of the silicon substrate, and the laminated structure is connected with the silicon substrate. The sealing ring comprises a first sealing part, and the first sealing part is arranged in the circumferential direction of the laminated structure. The first sealing part is connected with the laminated structure, and the thickness of the first sealing part in the length direction or the width direction of the laminated structure is 3-5 [mu] m. The passivation layer wraps the outer sides of the device part and the sealing ring, and the passivation layer is connected with the device part and the sealing ring. The cutting channels are arranged on the passivation layer, located between the two adjacent device parts and arranged in the circumferential direction of the device parts.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a wafer dicing channel structure and a corresponding semiconductor chip. Background Technology

[0002] In modern society, semiconductor chips are widely used in various industries. During the semiconductor chip manufacturing process, sealing rings are incorporated to reduce stress cracking caused by vertical vias. Existing sealing rings consist of metal layers and tungsten plugs; for reliability considerations, 2-3 sets of tungsten plug structures are typically placed between the metal layers. Due to the high stress of tungsten metal, the tungsten plug vias between the metal layers are often staggered. Therefore, existing sealing rings require additional space in the semiconductor device, reducing its space utilization. Thus, existing semiconductor devices suffer from the technical problem of low space utilization.

[0003] Therefore, it is necessary to provide a wafer dicing channel structure and a corresponding semiconductor chip to solve the above-mentioned technical problems. Utility Model Content

[0004] This invention provides a wafer dicing channel structure and a corresponding semiconductor chip, which effectively solves the technical problem of low space utilization in existing semiconductor devices.

[0005] This utility model provides a wafer dicing channel structure, which includes:

[0006] The device section includes,

[0007] silicon substrate;

[0008] A stacked structure is disposed at the upper end of the silicon substrate and connected to the silicon substrate;

[0009] A sealing ring includes a first sealing portion, which is disposed circumferentially along the stacked structure and connected to the stacked structure. The thickness of the first sealing portion in the length or width direction of the stacked structure is 3-5 μm.

[0010] A passivation layer is wrapped around the outside of the device part and the sealing ring, and is connected to the device part and the sealing ring;

[0011] A cutting channel is disposed on the passivation layer, located between two adjacent device portions, and disposed circumferentially along the device portion.

[0012] Furthermore, the sealing ring is formed by depositing a layer of metal on the outer periphery of the device portion.

[0013] Furthermore, the longitudinal section of the cutting channel is trapezoidal, and the width of the bottom of the cutting channel is smaller than the width of the opening of the cutting channel.

[0014] Furthermore, the bottom of the first sealing portion is closer to the edge of the stacked structure than the top of the first sealing portion.

[0015] Furthermore, the sealing ring includes a second sealing portion connected to the first sealing portion. The second sealing portion is annular and is disposed circumferentially between the stacked structure and the passivation layer. The second sealing portion connects the stacked structure and the passivation layer.

[0016] Furthermore, the sealing ring includes a third sealing portion, which is annular and disposed circumferentially between the stacked structure and the silicon substrate. The third sealing portion is connected to the first sealing portion and connects the silicon substrate and the stacked structure.

[0017] Furthermore, the stacked structure includes,

[0018] A gallium nitride layer is disposed on the upper end of the silicon substrate and is connected to the silicon substrate;

[0019] An aluminum gallium nitride layer is disposed on the upper end of the gallium nitride layer and connected to the gallium nitride layer;

[0020] A silicon nitride layer is disposed on the upper end of the aluminum gallium nitride layer and connected to the aluminum gallium nitride layer.

[0021] Furthermore, the stacked structure also includes,

[0022] A dielectric layer is disposed on the upper end of the silicon nitride layer and connected to the silicon nitride layer;

[0023] An isolation layer is disposed at the upper end of the dielectric layer and is connected to the dielectric layer;

[0024] A first intermetallic dielectric layer is disposed on the upper end of the dielectric layer and connected to the dielectric layer;

[0025] The second intermetallic dielectric layer is disposed on the upper end of the first intermetallic dielectric layer and is connected to the first intermetallic dielectric layer.

[0026] Furthermore, the stacked structure also includes,

[0027] An ohmic metal layer is connected to the interior of the aluminum gallium nitride layer, the silicon nitride layer, and the silicon nitride layer;

[0028] A first tungsten plug is located inside the dielectric layer and the isolation layer. One end of the first tungsten plug is connected to the ohmic metal layer, and the other end of the first tungsten plug is connected to the first metal layer.

[0029] The first metal layer is connected to the interior of the first intermetallic dielectric layer;

[0030] The second tungsten plug is located inside the first intermetallic dielectric layer. One end of the first tungsten plug is connected to the first metal layer, and the other end of the first tungsten plug is connected to the second metal layer.

[0031] The second metal layer is connected to the interior of the second intermetallic dielectric layer;

[0032] A third tungsten plug is located inside the second intermetallic dielectric layer. One end of the third tungsten plug is connected to the second metal layer, and the other end of the third tungsten plug is connected to the third metal layer.

[0033] The third metal layer is connected to the upper end of the second intermetallic dielectric layer.

[0034] A semiconductor chip comprising any of the wafer dicing structures described above.

[0035] Compared to existing technologies, this invention offers the following advantages: It provides a wafer dicing channel structure comprising a sealing ring and a device portion, the device portion including a stacked structure. The sealing ring is formed by depositing a metal layer on the outer periphery of the device portion, and the thickness of the first sealing portion of the sealing ring in the length or width direction of the stacked structure is 3-5 μm. Therefore, this sealing ring can prevent cracks generated by the dicing channel from extending into the device portion. Simultaneously, the sealing ring occupies only a small space in the wafer dicing channel structure, improving the space utilization of the semiconductor device. This effectively solves the technical problem of low space utilization in existing semiconductor devices, and helps reduce wasted wafer area. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments are briefly introduced below. The drawings described below are only the corresponding drawings of some embodiments of this utility model.

[0037] Figure 1 This is a front view of an embodiment of the wafer dicing channel structure of this utility model.

[0038] Figure 2 This is a planar schematic diagram of the sealing ring and the dicing channel in one embodiment of the wafer dicing channel structure of this utility model.

[0039] Figure 3This is a second planar schematic diagram of the sealing ring and the dicing channel in one embodiment of the wafer dicing channel structure of this utility model.

[0040] In the figure, 10 is the wafer dicing channel structure; 11 is the device section; 111 is the silicon substrate; 112 is the stacked structure; 1121 is the gallium nitride layer; 1122 is the aluminum gallium nitride layer; 1123 is the silicon nitride layer; 1124 is the dielectric layer; 1125 is the isolation layer; 1126 is the first intermetallic dielectric layer; 1127 is the second intermetallic dielectric layer; 1128 is the ohmic metal layer; 11281 is the first tungsten plug; 11282 is the first metal layer; 11283 is the second tungsten plug; 11284 is the second metal layer; 11285 is the third tungsten plug; 11286 is the third metal layer; 12 is the sealing ring; 121 is the first sealing part; 122 is the second sealing part; 123 is the third sealing part; 13 is the passivation layer; and 14 is the dicing channel. Detailed Implementation

[0041] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0042] The directional terms mentioned in this utility model, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", "top" and "bottom", are only for reference to the orientation of the accompanying drawings. The directional terms used are for the purpose of explaining and understanding this utility model, and are not intended to limit this utility model.

[0043] The terms "first" and "second" in this utility model are used for descriptive purposes only and should not be construed as indicating or implying relative importance, nor as a restriction on the order of events.

[0044] In the diagram, units with similar structures are represented by the same labels.

[0045] Please refer to Figure 1This invention provides a wafer dicing channel structure 10. The wafer dicing channel structure 10 includes a device portion 11, a silicon substrate 111, a stacked structure 112, a sealing ring 12, a passivation layer 13, and dicing channels 14. The device portion 11 includes the silicon substrate 111 and the stacked structure 112, with the stacked structure 112 disposed on the upper end of the silicon substrate 111 and connected to the silicon substrate 111. The sealing ring 12 includes a first sealing portion 121, which is disposed circumferentially along the stacked structure 112. The first sealing portion 121 is connected to the stacked structure 112, and its thickness in the length or width direction of the stacked structure 112 is 3-5 μm. The passivation layer 13 wraps around the outside of the device portion 11 and the sealing ring 12, and is connected to the device portion 11 and the sealing ring 12. A dicing channel 14 is disposed on the passivation layer 13, located between two adjacent device portions 11, and arranged circumferentially along the device portion 11. The sealing ring 12 is formed by depositing a layer of metal on the outer periphery of the device portion 11. The longitudinal section of the dicing channel 14 is trapezoidal, with the width of the bottom of the dicing channel 14 being smaller than the width of the opening of the dicing channel 14. Therefore, even with the dicing channel 14 in the wafer dicing channel structure 10, the device portion 11 possesses significant mechanical strength. Consequently, the device portion 11 is less prone to damage during prolonged use. Furthermore, the bottom of the first sealing portion 121 is closer to the edge of the stacked structure 112 than the top of the first sealing portion 121, thus making the first sealing portion 121 inclined. Compared to a vertically arranged first sealing portion 121, the inclined arrangement of the first sealing portion 121 increases the contact area with the stacked structure 112. Therefore, the connection between the first sealing portion 121 and the stacked structure 112 is more secure.

[0046] Please refer to Figure 1 The sealing ring 12 includes a second sealing portion 122, which is connected to the first sealing portion 121. The second sealing portion 122 is annular and is disposed circumferentially between the stacked structure 112 and the passivation layer 13, connecting the stacked structure 112 and the passivation layer 13. The second sealing portion 122 increases the contact area between the sealing ring 12 and the device portion 11, thereby making the connection between the sealing ring 12 and the device portion 11 more stable. The sealing ring 12 also includes a third sealing portion 123, which is annular. The third sealing portion 123 is disposed circumferentially between the stacked structure 112 and the silicon substrate 111, connecting the first sealing portion 121 and the silicon substrate 111 and the stacked structure 112. The third sealing part 123 can be provided to increase the contact area between the sealing ring 12 and the device part 11, thereby making the connection between the sealing ring 12 and the device part 11 more stable.

[0047] Please refer to Figure 1 The stacked structure 112 includes a gallium nitride layer 1121, an aluminum gallium nitride layer 1122, a silicon nitride layer 1123, a dielectric layer 1124, an isolation layer 1125, a first intermetallic dielectric layer 1126, a second intermetallic dielectric layer 1127, and a second intermetallic dielectric layer 1128. The gallium nitride layer 1121 is disposed on the upper end of the silicon substrate 111 and is connected to the silicon substrate 111. The aluminum gallium nitride layer 1122 is disposed on the upper end of the gallium nitride layer 1121 and is connected to the gallium nitride layer 1121. The silicon nitride layer 1123 is disposed on the upper end of the aluminum gallium nitride layer 1122 and is connected to the aluminum gallium nitride layer. The dielectric layer 1124 is disposed on the upper end of the silicon nitride layer 1123 and is connected to the silicon nitride layer 1123. An isolation layer 1125 is disposed on the upper end of the dielectric layer 1124 and is connected to the dielectric layer 1124. A first intermetallic dielectric layer 1126 is disposed on the upper end of the dielectric layer 1124 and is connected to the dielectric layer 1124. A second intermetallic dielectric layer 1127 is disposed on the upper end of the first intermetallic dielectric layer 1126 and is connected to the first intermetallic dielectric layer 1126.

[0048] Please refer to Figure 1 The stacked structure 112 further includes an ohmic metal layer 1128, a first tungsten plug 11281, a first metal layer 11282, a second tungsten plug 11283, a second metal layer 11284, a third tungsten plug 11285, and a third metal layer 11286. The ohmic metal layer 1128 is connected to the interior of the aluminum gallium nitride layer 1122, the silicon nitride layer 1123, and the silicon nitride layer 1123. The first tungsten plug 11281 is located inside the dielectric layer 1124 and the insulating layer 1125. One end of the first tungsten plug 11281 is connected to the ohmic metal layer 1128, and the other end of the first tungsten plug 11281 is connected to the first metal layer 11282. The first metal layer 11282 is connected to the interior of the first intermetallic dielectric layer 1126. The second tungsten plug 11283 is located inside the first intermetallic dielectric layer 1126. One end of the first tungsten plug 11281 is connected to the first metal layer 11282, and the other end of the first tungsten plug 11281 is connected to the second metal layer 11284. The second metal layer 11284 is connected to the interior of the second intermetallic dielectric layer 1127. The third tungsten plug 11285 is located inside the second intermetallic dielectric layer 1127. One end of the third tungsten plug 11285 is connected to the second metal layer 11284, and the other end of the third tungsten plug 11285 is connected to the third metal layer 11286. The third metal layer 11286 is connected to the upper end of the second intermetallic dielectric layer 1127.

[0049] Please refer to Figure 2 and Figure 3The wafer dicing structure 10 is applied in a semiconductor chip. The semiconductor chip has multiple device portions 11, sealing rings 12 are arranged circumferentially along the device portions 11, and dicing channels 14 are arranged outside the sealing rings 12. Furthermore, the dicing channels are arranged circumferentially along the sealing rings 12, and the dicing channels 14 are located between two adjacent sealing rings 12 of the device portions 11.

[0050] The manufacturing process of this utility model is as follows: First, the user provides a silicon substrate 111. The user fabricates a gallium nitride layer 1121 on the upper end of the silicon substrate 111. Then, the user fabricates an aluminum gallium nitride layer 1122 on the upper end of the gallium nitride layer 1121. The user fabricates a silicon nitride layer 1123 on the upper end of the aluminum gallium nitride layer 1122. The user connects an ohmic metal layer 1128 to the interior of the aluminum gallium nitride layer 1122 and the silicon nitride layer 1123. Subsequently, the user fabricates a dielectric layer 1124 on the upper end of the silicon nitride layer 1123, and an isolation layer 1125 on the upper end of the dielectric layer 1124. The user fabricates a first tungsten plug 11281 inside the dielectric layer 1124 and the isolation layer 1125. Next, the user fabricates a first intermetallic dielectric layer 1126 on the upper end of the dielectric layer 1124. The user fabricates a first metal layer 11282 and a second tungsten plug 11283 inside the first intermetallic dielectric layer 1126. Then, the user fabricates a second intermetallic dielectric layer 1127 at the upper end of the first intermetallic dielectric layer 1126. The user fabricates a second metal layer 11284 and a third tungsten plug 11285 inside the second intermetallic dielectric layer 1127, and the user fabricates a third metal layer 11286 at the upper end of the second intermetallic dielectric layer 1127. Subsequently, the user fabricates a sealing ring 12, which is formed by depositing a layer of metal on the outer periphery of the device portion 11. Next, the user fabricates a passivation layer 13 on the outer side of the device portion 11 and the sealing ring 12, which wraps around the outer side of the device portion 11 and the sealing ring 12. Furthermore, the first sealing portion 121 of the sealing ring 12 is disposed circumferentially along the laminated structure 112. The second sealing portion 122 of the sealing ring 12 is disposed circumferentially between the stacked structure 112 and the passivation layer 13, and the third sealing portion 123 is disposed circumferentially between the stacked structure 112 and the silicon substrate 111. Subsequently, the user forms a dicing channel 14 on the passivation layer 13, and the wafer dicing channel structure 10 is thus completed.

[0051] This invention provides a wafer dicing channel structure comprising a sealing ring and a device portion, the device portion including a stacked structure. The sealing ring is formed by depositing a layer of metal on the outer periphery of the device portion, and the thickness of the first sealing portion of the sealing ring in the length or width direction of the stacked structure is 3-5 μm. Therefore, this sealing ring can be used to prevent cracks generated by the dicing channel from extending into the device portion. Simultaneously, this sealing ring occupies only a small space in the wafer dicing channel structure, improving the space utilization of the semiconductor device. It effectively solves the technical problem of low space utilization in existing semiconductor devices, and helps to reduce wasted wafer area.

[0052] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A wafer dicing channel structure, characterized in that, It includes, The device section includes, silicon substrate; A stacked structure is disposed at the upper end of the silicon substrate and connected to the silicon substrate; A sealing ring includes a first sealing portion, which is disposed circumferentially along the stacked structure and connected to the stacked structure. The thickness of the first sealing portion in the length or width direction of the stacked structure is 3-5 μm. A passivation layer is wrapped around the outside of the device part and the sealing ring, and is connected to the device part and the sealing ring; A cutting channel is disposed on the passivation layer, located between two adjacent device portions, and disposed along the circumference of the device portion.

2. The wafer dicing channel structure according to claim 1, characterized in that, The sealing ring is formed by depositing a layer of metal on the outer periphery of the device portion.

3. The wafer dicing channel structure according to claim 1, characterized in that, The longitudinal section of the cutting channel is trapezoidal, and the width of the bottom of the cutting channel is smaller than the width of the opening of the cutting channel.

4. The wafer dicing channel structure according to claim 1, characterized in that, The bottom of the first sealing portion is closer to the edge of the stacked structure than the top of the first sealing portion.

5. The wafer dicing channel structure according to claim 1, characterized in that, The sealing ring includes a second sealing portion connected to the first sealing portion. The second sealing portion is annular and is disposed circumferentially between the stacked structure and the passivation layer. The second sealing portion connects the stacked structure and the passivation layer.

6. The wafer dicing channel structure according to claim 1, characterized in that, The sealing ring includes a third sealing portion, which is annular and disposed circumferentially between the stacked structure and the silicon substrate. The third sealing portion is connected to the first sealing portion and connects the silicon substrate and the stacked structure.

7. The wafer dicing channel structure according to claim 1, characterized in that, The stacked structure includes, A gallium nitride layer is disposed on the upper end of the silicon substrate and is connected to the silicon substrate; An aluminum gallium nitride layer is disposed on the upper end of the gallium nitride layer and connected to the gallium nitride layer; A silicon nitride layer is disposed on the upper end of the aluminum gallium nitride layer and connected to the aluminum gallium nitride layer.

8. The wafer dicing channel structure according to claim 7, characterized in that, The stacked structure also includes, A dielectric layer is disposed on the upper end of the silicon nitride layer and connected to the silicon nitride layer; An isolation layer is disposed at the upper end of the dielectric layer and is connected to the dielectric layer; A first intermetallic dielectric layer is disposed on the upper end of the dielectric layer and connected to the dielectric layer; The second intermetallic dielectric layer is disposed on the upper end of the first intermetallic dielectric layer and is connected to the first intermetallic dielectric layer.

9. The wafer dicing channel structure according to claim 8, characterized in that, The stacked structure also includes, An ohmic metal layer is connected to the interior of the aluminum gallium nitride layer, the silicon nitride layer, and the dielectric layer; A first tungsten plug is located inside the dielectric layer and the isolation layer. One end of the first tungsten plug is connected to the ohmic metal layer, and the other end of the first tungsten plug is connected to the first metal layer. The first metal layer is connected to the interior of the first intermetallic dielectric layer; The second tungsten plug is located inside the first intermetallic dielectric layer. One end of the first tungsten plug is connected to the first metal layer, and the other end of the first tungsten plug is connected to the second metal layer. The second metal layer is connected to the interior of the second intermetallic dielectric layer; A third tungsten plug is located inside the second intermetallic dielectric layer. One end of the third tungsten plug is connected to the second metal layer, and the other end of the third tungsten plug is connected to the third metal layer. The third metal layer is connected to the upper end of the second intermetallic dielectric layer.

10. A semiconductor chip, characterized in that, It includes the wafer dicing structure as described in any one of claims 1-9.

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