Switching power supply system with self-powered control architecture

Abstract

The utility model discloses a switching power supply system with a self-powered control architecture, which relates to the technical field of switching power supplies and comprises a control chip and a power conversion circuit, and the control chip comprises a power switching circuit, a starting control circuit and a self-powered control circuit. The power switch circuit comprises a normally open high-voltage power switch and a low-voltage enhanced power switch which are connected in series; the drain end of the normally open high-voltage power switch is connected with the power conversion circuit; the gate end of the normally open high-voltage power switch is connected with the source end of the low-voltage enhanced power switch; a series node of the normally open high-voltage power switch and the low-voltage enhanced power switch is connected with the starting control circuit and the self-powered control circuit, and the starting control circuit and the self-powered control circuit are connected with a power supply VDD end of the control chip. According to the system, the self-power supply of the control chip can be realized, the VDD pin of the chip can be conveniently controlled below a lower voltage, and the device cost and the use cost can be reduced.

Description

Technical Field

[0001] This utility model relates to the field of switching power supply technology, and more specifically, to a switching power supply system with a self-powered control architecture. Background Technology

[0002] The commonly used AC-DC (alternating current to direct current) flyback power supply systems are as follows: Figure 1 As shown, this is a resistor-start mode. The AC voltage passes through the EMI filter E2, and then is rectified into a DC voltage Vbuck2 by the full-wave rectifier bridge B2 and capacitor C10. Capacitor C13 is charged through starting resistors Rst1 and Rst2 (typically 200V withstand resistors), causing the voltage of capacitor C13 to rise. When the voltage of capacitor C13 rises above the undervoltage lockout (UVLO) set by the PWM control chip IC2 (e.g., 15V), the undervoltage lockout is released, and the drive circuit of the PWM control chip IC2 starts working. It can receive the PWM signal and drive the power MOS M10 to turn on and off to adjust the duty cycle, ultimately achieving a stable output voltage Vo. After the PWM signal starts working, the auxiliary winding AUX of the transformer and diode D11 charge capacitor C13 to power IC2. The auxiliary winding AUX of the transformer supplying IC2 and the output winding Sec are in phase, and the VDD voltage is proportional to the output voltage Vo. For some systems with variable output voltage Vo, such as... Figure 2 The USB PD fast charging power supply system shown includes IC4, which is the USB PD protocol IC. Its CC1 / CC2 / DP / DN pins communicate with the load device (e.g., mobile phone, laptop) via a TYPE-C interface. Based on the voltage required by the load device, it changes the voltage division ratio of R0 / R1 via the VFB pin, thereby changing the output voltage. For USB PD 3.0, the output voltage range is 3–21V, while USB PD 3.1 requires an output voltage of 3–48V. The supply voltage of IC3 is proportional to the output voltage Vo3. If the output Vo3 varies by a factor of 7 from 3 to 21V, then the supply voltage VCC of IC3 must also be within a factor of 7. If the minimum supply voltage of IC3 is 10V, then the maximum operating voltage of IC3 must be at least 70V. If Vo3 varies by a factor of 16 from 3 to 48V, then the operating voltage range of IC3 needs to be 10–160V, which places very wide requirements on the operating voltage range of IC3.

[0003] In summary, existing switching power supply systems have the following drawbacks:

[0004] 1) In a resistor-based power supply system, the starting resistor continues to consume current after the startup process is complete, resulting in power consumption and failing to meet the low standby power consumption efficiency standard requirements.

[0005] 2) After startup, a transformer auxiliary winding, a diode, and a capacitor are required to power the controller chip. This is especially true for fast-charging power supply systems with variable output voltage. Since the controller supply voltage and output voltage are proportional, the VDD power supply pin of the controller chip needs a very high voltage withstand range, which greatly increases the cost of the controller IC. Utility Model Content

[0006] The present invention provides a switching power supply system with a self-powered control architecture, which can solve the above-mentioned problems.

[0007] To solve the above problems, the technical solution adopted by this utility model is as follows:

[0008] This invention provides a switching power supply system with a self-powered control architecture, including a control chip and a power conversion circuit. The control chip includes a power switching circuit, a startup control circuit, and a self-powered control circuit. The power switching circuit includes a normally open high-voltage power switch and a low-voltage enhancement-mode power switch connected in series. The drain terminal of the normally open high-voltage power switch is connected to the power conversion circuit. The gate terminal of the normally open high-voltage power switch is connected to the source terminal of the low-voltage enhancement-mode power switch. The series connection node of the normally open high-voltage power switch and the low-voltage enhancement-mode power switch is connected to the startup control circuit and the self-powered control circuit. The startup control circuit and the self-powered control circuit are connected to the power supply VDD terminal of the control chip.

[0009] Furthermore, the control chip also includes a drive circuit connected to the gate of the low-voltage enhancement-mode power switch, an AND gate connected to the output side of the drive circuit, an inverter and a PWM generation circuit connected to the input side of the AND gate, and a level conversion circuit connected to the input side of the PWM generation circuit; the self-powered control circuit is connected to the output side of the PWM generation circuit and the input side of the inverter; the undervoltage lockout signal output terminal of the start-up control circuit is connected to the input side of the AND gate; and the power supply VDD terminal of the control chip is connected to a bypass capacitor.

[0010] Furthermore, the normally open high-voltage power switch has a negative turn-on voltage and is a high-voltage depletion-type metal-oxide-semiconductor field-effect transistor or a high-voltage depletion-type gallium nitride high electron mobility transistor; the low-voltage enhancement-type power switch has a positive turn-on voltage and is a low-voltage enhancement-type metal-oxide-semiconductor field-effect transistor.

[0011] Furthermore, the input of the level conversion circuit is connected to the source of the low-voltage enhancement-mode power switch via a current sensing resistor Rs.

[0012] Specifically, the startup control circuit includes resistors R4 and R5, N-type MOS switches M3 and M4, diode D2, and an undervoltage lockout circuit; one end of resistor R5 is connected to the connection line between the normally open high-voltage power switch and the low-voltage enhancement-type power switch, as well as the self-powered control circuit; the other end of resistor R5 is connected to one end of resistor R4 and the drain of switch M3; the source of switch M3 is connected to the anode of diode D2, and the gate is connected to the other end of resistor R4 and the drain of switch M4; the gate of switch M4 is connected to the AND gate and the undervoltage lockout circuit; the input of the undervoltage lockout circuit is connected to diode D2, a bypass capacitor, and the self-powered control circuit.

[0013] Specifically, the self-powered control circuit includes an N-type MOS switch M7, P-type MOS switches M5 and M6, resistors R7, R8, R9, and R10, comparators cmp1 and cmp2, ​​a diode D3, a logic NOR gate NOR2, and a D flip-flop DFF1; the source of switch M5 is connected to the source of switch M6, one end of resistor R7, and resistor R5; the drain of switch M5 is connected to the positive input terminal of comparator cmp1 and the positive terminal of diode D3; the gate of switch M5 is connected to one end of resistor R8, the other end of resistor R7, and the gate of switch M6; resistors The other end of R8 is connected to the drain of switch M7; the gate of switch M7 is connected to the output of D flip-flop DFF1 and the input of inverter; the drain of switch M6 is connected to the negative input of comparator cmp1, and the output of comparator cmp1 is connected to logic NOR gate NOR2; the negative terminal of diode D3 is connected to the bypass capacitor and one end of resistor R9; the other end of resistor R9 is connected to resistor R10 and the positive input of comparator cmp2; the negative input of comparator cmp2 is connected to the reference voltage, and its output is connected to logic NOR gate NOR2; the output of logic NOR gate NOR2 is connected to D flip-flop DFF1.

[0014] Furthermore, the charging of the bypass capacitor at the VDD terminal by the series node of the normally open high-voltage power switch and the low-voltage enhancement-type power switch via the self-powered control circuit only occurs when the PWM signal output by the PWM generator circuit is at a high level.

[0015] Optionally, the power conversion circuit is a flyback circuit, a forward circuit, a buck circuit, a boost circuit, a half-bridge circuit, or a full-bridge circuit.

[0016] Compared with the prior art, the beneficial effects of this utility model are:

[0017] 1) After the power supply is started, the startup circuit is completely disconnected. The startup circuit does not consume any power after it is working normally. This greatly improves the power supply system’s no-load or light-load standby power consumption and can easily meet the most stringent standby power consumption and energy efficiency standards.

[0018] 2) The self-powered control circuit can control the VDD overvoltage protection voltage setting value, which is independent of the output voltage. The VDD pin can be controlled below a low voltage, which greatly saves the cost of the controller. Furthermore, under the condition that the controller consumes the same operating current, the power consumed by the controller is also lower due to the lower VDD voltage.

[0019] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, embodiments of this utility model are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a diagram of an existing AC-DC flyback power supply system;

[0022] Figure 2 This is a diagram of an existing USB PD fast charging power supply system;

[0023] Figure 3 This is a diagram of a flyback switching power supply system with a self-powered control architecture as described in the embodiment;

[0024] Figure 4 This is a schematic diagram of the working principle of the startup circuit in the embodiment;

[0025] Figure 5 This is a schematic diagram of the working principle of the self-powered control circuit in the embodiment. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments.

[0027] Please refer to Figure 3 This embodiment discloses a flyback switching power supply system with a self-powered control architecture, including a control chip IC1 and a power conversion circuit. The power conversion circuit includes an EMI filter E1, a rectifier bridge B1, capacitors C1, C2, and Cout, a snubber circuit, a transformer T1, a diode D1, resistors R0, R1, R2, and R3, a Zener diode TL431, and an optocoupler OPTO. The control chip IC1 is connected to a bypass capacitor C3 and a resistor Rs.

[0028] The control chip IC1 integrates a startup control circuit, a self-powered control circuit, a power switch circuit (including a normally open high-voltage power switch PM1 and a low-voltage enhancement-mode power switch PM2 connected in series (in this embodiment, an N-type MOS switch is selected). The normally open high-voltage power switch PM1 has a negative turn-on voltage Vth, which can be a high-voltage depletion-mode metal-oxide-semiconductor field-effect transistor or a high-voltage depletion-mode gallium nitride high electron mobility transistor. The low-voltage enhancement-mode power switch PM2 has a positive turn-on voltage), logic gates inv1 and AND1, a drive circuit, a level conversion circuit, and a PWM generator circuit.

[0029] The startup control circuit includes an undervoltage lockout circuit, switches M3 and M4 (both N-type MOS switches), resistors R4 and R5, and diode D2.

[0030] The self-powered control circuit includes P-type MOS switches M5 and M6, N-type MOS switch M7, resistors R7, R8, R9, and R10, diode D3, comparators cmp1 and cmp2, ​​logic gate NOR2, and D flip-flop DFF1.

[0031] The working principle of the start-up control circuit is as follows:

[0032] Figure 3 After AC is connected, the Vbuck node voltage becomes a high DC voltage after rectification by rectifier bridge B1. For example, if AC is connected at 220V, the Vbuck voltage will be... Figure 3 The normally open high-voltage power switch PM1 is a high-voltage depletion-type metal-oxide-semiconductor field-effect transistor or a high-voltage depletion-type gallium nitride high electron mobility transistor. Its turn-on voltage Vth is negative, for example, Vth = -20V, and its breakdown voltage BV = 700V. PM2 is a low-voltage enhancement-type MOSFET. Its turn-on voltage Vth is positive, for example, Vth = 3V, and its breakdown voltage BV = 40V. Figure 3When the VDD pin voltage of control chip IC1 is in undervoltage lockout state, the undervoltage lockout UVLO output signal pg is "0". After being input to the logic AND gate AND1, it outputs a "0" signal to the drive circuit, and the output drv is "0", turning off the low-voltage enhancement power switch PM2. Assuming the turn-on voltage of PM1 is V = -20V, the voltage at the Vsd node is 20V. The Vsd node voltage passes through the current-limiting resistor R5, switch M3, diode D2 to the VDD pin of control chip IC1, and then to the external capacitor C3. Since the undervoltage lockout UVLO output pg is "0", switch M4 is closed. Resistor R4 pulls the gate terminal Vg_m3 of switch M3 high, turning on M3. Therefore, the Vbuck voltage passes through transformer T1, the DRAIN pin of control chip IC1, the normally open high-voltage power switch PM1, the current-limiting resistor R5, switch M3, diode D2, and the VDD pin of control chip IC1 to charge the external capacitor C3. The pin voltage rises until it exceeds the undervoltage lockout (UVLO) voltage (e.g., 12V). The UVLO outputs a high-level "1" pg signal. This high-level "1" pg signal turns on switch M4, pulling the Vg_m3 voltage at the gate of the M3 NMOS down to "0". Switch M3 then turns off, stopping charging of the VDD pin. The startup circuit completes the entire startup process. Afterward, the PWM generation circuit operates normally, and the drive circuit (DRV) begins outputting pulse-level signals, such as... Figure 4 As shown.

[0033] The working principle of the self-powered control circuit is as follows:

[0034] After the start-up control circuit completes the start-up process Figure 3 The PWM generator circuit starts working normally; when Figure 3 When the rising edge of the PWM signal output from the PWM generator circuit to the D flip-flop DFF1 arrives, the output signal pwm_ch of the D flip-flop DFF1 is set to a high level "1". This high level turns on the M7 NMOS and sets the Vg_m5 signal to a low level through resistor R8. The low level signal of Vg_m5 turns on the main power switch M5 PMOS and the current detection switch M6. At this time, the pwm_ch signal passes through the inverter inv1 to the input of the logic "AND" gate AND1. After passing through the driver circuit, the output drv of the driver circuit remains at a low level "0", turning off the low-voltage enhancement power switch PM2. The normally open high-voltage power switch PM1 turns on. The Vbuck voltage passes through the transformer T1, the IC1DRAIN pin, the normally open high-voltage power switch PM1, then through the switch M5, diode D3 to the IC1VDD pin, charging the external capacitor C3. The voltage VCC of capacitor C3 rises, and the charging current Ic of C3 also rises linearly. When the charging current Ic exceeds the OCP overcurrent setting value Iocp, ( Figure 3The circuit consists of switches M5 and M6, a reference current Iref, and comparator cmp1, forming the overcurrent OCP detection circuit for switch M5. Assuming the size ratio of switches M5 and M6 is N, then Iocp = N * Iref. For example, if N = 1000 and Iref = 300uA, then Iocp = 1000 * 300uA = 300mA. The comparator cmp1 outputs a high-level OCP signal "1". After passing through the OR gate NOR2, it outputs "0" to the reset terminal R of D flip-flop DFF1, setting the output pwm_ch signal of DFF1 to "0". When pwm_ch is "0", switch M7 is closed. Then, resistor R7 pulls the Vg_m5 voltage high, closing switch M5. This, in turn, affects IC1's VDD voltage. The external capacitor C3 of the pin stops charging; after the pwm_ch signal outputs "0", it passes through the inverter inv1 and outputs a logic "1" signal to the input of the logic AND gate AND1. At this time, the logic AND gate AND1 can transmit the high-level "1" signal of the pwm generator output signal to the driver circuit, making the driver circuit output drv a high-level "1", which enables the circuit. Figure 3 In the low-voltage enhancement-mode power switch PM2, the Vbuck voltage passes through transformer T1, the IC1 DRAIN pin, the normally open high-voltage power switch PM1, the low-voltage enhancement-mode power switch PM2, then to the current sampling resistor Rs, and finally to the IC ground ic_gnd. The current on transformer T1 rises linearly, and the voltage Vcs (Vcs is negative relative to IC ground ic_gnd) on the current sampling resistor Rs decreases linearly. The voltage on the current sensing resistor Rs passes through the IC1 CS pin, then through the level conversion circuit (converting the negative voltage to a positive voltage), and is then sent to the PWM generation circuit until... Figure 3 The output voltage Vcs_int of the intermediate level conversion circuit and the voltage of the FB pin generate a PWM turn-off signal. The PWM generator circuit then outputs a low level "0" PWM signal. After passing through the AND1 logic, the output drv of the driver circuit becomes "0", thus turning off the PWM. Figure 3 The low-to-medium voltage enhancement-mode power switch PM2 continues this process until the rising edge of the PWM signal in the next cycle arrives, repeating the above process. This process achieves... Figure 3 The charging process of external capacitor C3 connected to the VDD pin of IC1 and the power supply process of capacitor C3 to IC1, such as... Figure 5 As shown in the first and second cycles.

[0035] Because capacitor C3 is charged in each cycle, when the voltage of capacitor C3, i.e., the VDD voltage in IC1, reaches the overvoltage protection setting value ( Figure 3The VDD overvoltage protection circuit consists of resistors R9 and R10, comparator cmp2, ​​and reference voltage vref. When the VDD voltage exceeds the reference voltage vref through the voltage divider of resistors R9 and R10, comparator cmp2 outputs a high level. This high level is then output to the reset terminal R of D flip-flop DFF1 via the OR gate NOR2, setting the pwm_ch signal to "0". The subsequent process is the same as the OCP protection described earlier, shutting down the circuit. Figure 3 Switch M5 turns on the low-voltage enhanced power switch PM2 until the PWM generation circuit output signal PWM is "0", then turns off the low-voltage enhanced power switch PM2; therefore, the overvoltage protection voltage... For example, if R9 = 1200K ohms, R10 = 200K ohms, and Vref = 2V, then Vovp = 14V. Figure 5 As shown in the 3rd and 4th cycles.

[0036] The self-powered control circuit incorporates a PWM generator circuit. Figure 3 The charging of external capacitor C3 on the VDD pin of control chip IC1 only occurs during the period when the PWM generation circuit output signal PWM is at a high level. In other words, the opening of switch M5 only occurs during the period when the PWM signal is at a high level. Figure 5 In other words, this refers to the high-level phase of pwm_ch (its high-level duration will not exceed the high-level duration of pwm); furthermore... Figure 3 The high-level PWM signal output from the PWM generator circuit is divided into two parts, one of which is the activation of switch M5. Figure 5During the high-level phase of pwm_ch, transformer T1 enters the energy storage state and simultaneously charges the external capacitor C3 connected to the VDD pin of controller IC1. The transformer current rises linearly, resulting in a linear decrease in the voltage across the current sampling resistor Rs. When pwm_ch goes low, M5 is turned off, ending the charging of capacitor C3. Then, the low-voltage enhancement-mode power transistor PM2 continues to be turned on through the drive circuit, and transformer T1 continues to maintain the energy storage state with its current rising linearly. This results in a linear decrease in the voltage across the current sampling resistor Rs until the pwm signal goes low. The energy stored in the transformer is then released to the output capacitor Cout through diode D1. In other words, charging the external capacitor C3 connected to the controller's VDD pin only occurs during the energy storage phase of transformer T1. The portion of the Vbuck voltage minus the VDD voltage of IC1 falls on the transformer. The transformer stores energy at the T1pri terminal (i.e., Vbuck and drain voltages). The advantage is that the power consumption of controller IC1 is the VDD voltage of controller IC1 multiplied by the operating current of IC1 (because the excess voltage between Vbuck and VDD is used for energy storage in the transformer, and is not wasted). However, if the external capacitor connected to controller IC1's VDD occurs during a non-PWM signal high-level phase, then the power consumption of controller IC1 is the Vbuck voltage multiplied by the operating current of IC1. The difference in power consumption between these two methods is significant. For example, assuming the operating current of controller IC1 is 1mA, and the IC1 VDD voltage is controlled at 14V (VDD overvoltage protection voltage) using the above power supply control method, then the power consumption of IC1 is 14V × 1mA = 14mW. Figure 3 If the AC input voltage is 220VAC, then the Vbuck voltage is 311V. If the above power supply control method is not used, i.e., if capacitor C3 is not charged during the energy storage stage of transformer T1, then the power consumption of controller IC1 would be 311V × 1mA = 311mW. This is a huge difference compared to the 14mW power consumption of IC1, making it impossible to achieve the low standby power consumption requirement. The above demonstrates that this power supply control method, in addition to achieving self-powering and saving components, also achieves the advantage of low standby power consumption.

[0037] The flyback switching power supply system with a self-powered control architecture described in this embodiment has the following advantages:

[0038] 1) Compared to Figure 1 The traditional flyback power supply system control architecture eliminates the need for high-voltage start-up resistors Rst1 and Rst2, transformer auxiliary winding Aux, rectifier diode D11, and other components, significantly reducing system costs. After power-on, the start-up circuit is completely disconnected, and the start-up circuit consumes no power after normal operation. Figure 1Traditional flyback power supply startup resistors Rst1 / Rst2 still consume power after startup, which greatly improves the power system's no-load or light-load standby power consumption and can easily meet the most stringent standby power consumption and energy efficiency standards.

[0039] 2) Compared to Figure 2 Compared to traditional flyback fast charging power supply systems, this system eliminates the need for high-voltage start-up resistors Rst3 and Rst4, transformer auxiliary winding Aux, rectifier diode D32, and other components, significantly reducing system costs. Furthermore, because the self-powered control circuit can control the VDD overvoltage protection voltage setting (e.g., 14V), independent of the output voltage Vo3, the withstand voltage range of the VDD pin can be controlled below 15V. Figure 2 The VDD operating range of the controller IC3 is 10-70V or 10-160V, which can greatly reduce the cost of the controller IC3; and under the condition that the controller consumes the same operating current, the power consumption of the controller is also lower due to the lower VDD voltage; at the same time, the self-starting circuit is also eliminated. Figure 2 The startup resistors Rst3 / Rst4 are included, thus eliminating the increase in standby power consumption caused by the startup resistors Rst3 / Rst4. This greatly improves the standby power consumption of the power system under no-load or light-load conditions, and can easily meet the most stringent standby power consumption and energy efficiency standards.

[0040] The above example illustrates a method for controlling the startup or self-powered circuit in a flyback power system using a high-voltage normally open power switch (with a negative turn-on voltage Vth), such as a high-voltage depletion-mode metal-oxide-semiconductor field-effect transistor or a high-voltage depletion-mode gallium nitride high electron mobility transistor connected in series with a low-voltage enhancement-mode MOSFET. This is merely an example and should not be limited to this architecture; it can be applied to other power topologies (such as forward, Buck, Boost, Buck-boost, etc.).

[0041] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A switching power supply system with a self-powered control architecture, characterized in that, The system includes a control chip and a power conversion circuit. The control chip includes a power switching circuit, a startup control circuit, and a self-powered control circuit. The power switching circuit includes a normally open high-voltage power switch and a low-voltage enhancement-mode power switch connected in series. The drain terminal of the normally open high-voltage power switch is connected to the power conversion circuit. The gate terminal of the normally open high-voltage power switch is connected to the source terminal of the low-voltage enhancement-mode power switch. The series connection node of the normally open high-voltage power switch and the low-voltage enhancement-mode power switch is connected to the startup control circuit and the self-powered control circuit. The startup control circuit and the self-powered control circuit are connected to the power supply VDD terminal of the control chip.

2. The switching power supply system with a self-powered control architecture according to claim 1, characterized in that, The control chip further includes a drive circuit connected to the gate of the low-voltage enhancement-mode power switch, an AND gate connected to the output side of the drive circuit, an inverter and a PWM generation circuit connected to the input side of the AND gate, and a level conversion circuit connected to the input side of the PWM generation circuit; the self-powered control circuit is connected to the output side of the PWM generation circuit and the input side of the inverter; the undervoltage lockout signal output terminal of the start-up control circuit is connected to the input side of the AND gate; and the power supply VDD terminal of the control chip is connected to a bypass capacitor.

3. The switching power supply system with a self-powered control architecture according to claim 2, characterized in that, The normally open high-voltage power switch has a negative turn-on voltage and is a high-voltage depletion-type metal-oxide-semiconductor field-effect transistor or a high-voltage depletion-type gallium nitride high electron mobility transistor; the low-voltage enhancement-type power switch has a positive turn-on voltage and is a low-voltage enhancement-type metal-oxide-semiconductor field-effect transistor.

4. The switching power supply system with a self-powered control architecture according to claim 3, characterized in that, The input of the level conversion circuit is connected to the source of the low-voltage enhancement power switch via a current sensing resistor Rs.

5. The switching power supply system with a self-powered control architecture according to claim 3, characterized in that, The startup control circuit includes resistors R4 and R5, N-type MOS switches M3 and M4, diode D2, and an undervoltage lockout circuit. One end of resistor R5 is connected to the connection line between the normally open high-voltage power switch and the low-voltage enhancement-type power switch, as well as the self-powered control circuit. The other end of resistor R5 is connected to one end of resistor R4 and the drain of switch M3. The source of switch M3 is connected to the anode of diode D2, and the gate is connected to the other end of resistor R4 and the drain of switch M4. The gate of switch M4 is connected to the AND gate and the undervoltage lockout circuit. The input of the undervoltage lockout circuit is connected to diode D2, a bypass capacitor, and the self-powered control circuit.

6. The switching power supply system with a self-powered control architecture according to claim 5, characterized in that, The self-powered control circuit includes an N-type MOS switch M7, P-type MOS switches M5 and M6, resistors R7, R8, R9, and R10, comparators cmp1 and cmp2, ​​a diode D3, a logic NOR gate NOR2, and a D flip-flop DFF1. The source of switch M5 is connected to the source of switch M6, one end of resistor R7, and resistor R5. The drain of switch M5 is connected to the positive input of comparator cmp1 and the positive terminal of diode D3. The gate of switch M5 is connected to one end of resistor R8, the other end of resistor R7, and the gate of switch M6. Resistor R8... The other end is connected to the drain of switch M7; the gate of switch M7 is connected to the output of D flip-flop DFF1 and the input of inverter; the drain of switch M6 is connected to the negative input of comparator cmp1, and the output of comparator cmp1 is connected to logic NOR gate NOR2; the negative terminal of diode D3 is connected to the bypass capacitor and one end of resistor R9; the other end of resistor R9 is connected to resistor R10 and the positive input of comparator cmp2; the negative input of comparator cmp2 is connected to the reference voltage, and its output is connected to logic NOR gate NOR2; the output of logic NOR gate NOR2 is connected to D flip-flop DFF1.

7. The switching power supply system with a self-powered control architecture according to claim 1, characterized in that, The power conversion circuit is a flyback circuit, a forward circuit, a buck circuit, a boost circuit, a half-bridge circuit, or a full-bridge circuit.

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