CMOS image sensor
By setting a polysilicon layer in the CMOS image sensor and electrically connecting it to the transmission transistor, the photoelectron transmission is controlled, which solves the problems of dark current and image trailing, improves the full-well capacity of pixels, and achieves better electronic isolation and transmission effects.
Patent Information
- Application Number
- CN202423015110.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2034-12-04
AI Technical Summary
Existing CMOS image sensors suffer from dark current problems, image trailing, and insufficient full-well pixel capacity, especially due to poor electron transport and reduced photodiode storage capacity caused by excessively high ion implantation concentration in the pinned layer.
A polysilicon layer is placed on the photodiode and electrically connected to the transmission transistor. The transmission of photoelectrons is controlled by controlling the voltage timing. The electric field of the polysilicon layer is used to isolate the oxide layer on the substrate surface and the photodiode, thereby promoting electron transfer.
It reduces dark current, improves image trailing, and increases pixel full-well capacity without changing the pinned layer ion implantation concentration.
Smart Images
Figure CN223515242U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, and in particular to a CMOS image sensor. Background Technology
[0002] With the advancement of technology, the structure of CIS (CMOS Image Sensor) has been optimized at an increasingly rapid pace, and its application has become more widespread. To improve the performance and stability of CIS, structural optimization of individual pixel units has become crucial. Currently, most individual pixel units in CIS consist of a PD (Photo Diode), FD (Floating Diffusion), Pin (Pinning Layer), and TG (Transfer Gate). The photodiode structure receives and stores photoelectrons, the floating diffusion region detects generated electrons, and the transfer gate controls the transmission of photoelectrons within the photodiode. To reduce dark current in CIS, the hole concentration in the pinning layer is typically increased to prevent charge flow from defects in the oxide layer on the substrate surface into the photodiode, thus improving the isolation effect of the pinning layer. However, excessively increasing the hole concentration from ion implantation in the pinning layer can affect the hole concentration distribution under the transfer gate, hindering electron transmission, causing severe image lag, and reducing the full-well capacity (FWC) of the photodiode. Utility Model Content
[0003] The purpose of this invention is to provide a CMOS image sensor to solve the dark current problem in CIS, improve image trailing, and increase pixel full-well capacity.
[0004] To solve the above-mentioned technical problems, this utility model provides a CMOS image sensor, comprising:
[0005] Base;
[0006] A photodiode, located within the substrate, for generating photoelectrons;
[0007] A polycrystalline silicon layer is located on the photodiode;
[0008] A transmission transistor, the transmission transistor being located on the substrate and electrically connected to the polysilicon layer;
[0009] The transmission transistor is synchronized with the voltage timing of the polysilicon layer to jointly control the transmission of photoelectrons in the photodiode.
[0010] Optionally, a first contact plug is formed on the polysilicon layer, and a second contact plug is formed on the transmission transistor, wherein the first contact plug and the second contact plug are electrically connected to the same conductive layer.
[0011] Optionally, the width of the polycrystalline silicon layer is at least greater than or equal to the width of the photodiode.
[0012] Optionally, the thickness of the polycrystalline silicon layer is 300 to 500 angstroms.
[0013] Optionally, a pinning layer is further provided within the substrate, the pinning layer being located on the photodiode and below the polysilicon layer, the pinning layer being used to isolate the photodiode from the upper surface of the substrate.
[0014] Optionally, the doping type of the photodiode is different from that of the pinning layer; the photodiode is doped with a second doping type, and the pinning layer is doped with a first doping type.
[0015] Optionally, a first dielectric layer is disposed between the polysilicon layer and the transmission transistor, the first dielectric layer being used to isolate the polysilicon layer and the transmission transistor.
[0016] Optionally, a floating gate diffusion region is further provided in the substrate, the floating gate diffusion region being located in the substrate on one side of the transmission transistor, and the floating gate diffusion region being the drain region of the transmission transistor.
[0017] Optionally, the doping type of the photodiode is the same as the doping type of the floating gate diffusion region, and the doping type of the photodiode and the doping type of the floating gate diffusion region are a second doping type.
[0018] Optionally, the substrate may further include a shallow trench isolation structure for isolating adjacent pixel units, wherein the pixel unit includes a photodiode, a transmission transistor, and a floating diffusion region.
[0019] In the CMOS image sensor provided by this invention, a polysilicon layer is disposed on the photodiode and electrically connected to the transmission transistor. The voltage timing of the transmission transistor and the polysilicon layer is synchronized to jointly control the transmission of photoelectrons in the photodiode. This invention has unexpected effects. When the transmission transistor and the polysilicon layer are simultaneously applied with a negative voltage, the electric field on the polysilicon layer causes holes in the substrate to accumulate towards the substrate surface, resulting in better isolation between the oxide layer on the substrate surface and the photodiode within the substrate. This prevents electrons or defects in the oxide layer on the substrate surface from diffusing into the photodiode, reducing the dark current of the CMOS image sensor. When the transmission transistor and the polysilicon layer are simultaneously applied with a positive voltage, the electric field on the polysilicon layer promotes electron transfer within the photodiode, improving the image trailing phenomenon of the CMOS image sensor. Furthermore, this invention increases the full-well capacity of the CMOS image sensor through the electric field effect of the polysilicon layer without changing the ion implantation concentration in the pinning layer. Attached Figure Description
[0020] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention.
[0021] Figure 1 This is a schematic diagram of the structure of a CMOS image sensor according to an embodiment of the present invention.
[0022] Figure 2 This is a flowchart of a method for forming a CMOS image sensor according to an embodiment of the present invention.
[0023] Figure 3 This is a schematic diagram of the structure of a CMOS image sensor after the formation of the first dielectric layer according to an embodiment of the present invention.
[0024] Figure 4 This is a schematic diagram of the structure of a CMOS image sensor after the formation of a polycrystalline silicon material layer according to an embodiment of the present invention.
[0025] Figure 5 This is a schematic diagram of the structure of a CMOS image sensor after a patterned photoresist layer has been formed, according to an embodiment of the present invention.
[0026] Figure 6 This is a schematic diagram of the structure of a CMOS image sensor after the formation of a polycrystalline silicon layer according to an embodiment of the present invention.
[0027] Figure 7 This is a schematic diagram of the structure of the CMOS image sensor after the formation of the second dielectric layer according to an embodiment of the present invention.
[0028] Figure 8This is a schematic diagram of the structure of the CMOS image sensor after the contact plug is formed according to an embodiment of the present invention.
[0029] Figure 9 This is an electrical characteristic curve of the CMOS image sensor according to an embodiment of the present invention.
[0030] Figure 10 This is a hole concentration curve in the substrate of the CMOS image sensor according to an embodiment of the present invention.
[0031] In the attached figures: 10-substrate; 11-epitaxy layer; 12-photodiode; 13-isolation layer; 14-shallow trench isolation structure; 15-pinning layer; 16-floating diffusion region; 17-transfer transistor; 18-first dielectric layer; 19-polysilicon material layer; 19a-polysilicon layer; 20-patterned photoresist layer; 21-second dielectric layer; 22a-first contact plug; 22b-second contact plug; 22c-third contact plug; 23a-first portion of metal layer; 23b-second portion of metal layer; 24-third dielectric layer. Detailed Implementation
[0032] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.
[0033] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0034] Figure 1 This is a schematic diagram of the structure of a CMOS image sensor according to an embodiment of the present invention. Figure 1 As shown, this utility model provides a CMOS image sensor, comprising:
[0035] Base;
[0036] A photodiode 12 is located within the substrate and is used to generate photoelectrons;
[0037] A polycrystalline silicon layer 19a is located on the photodiode 12;
[0038] A transmission transistor 17 is located on the substrate and electrically connected to the polysilicon layer 19a. The voltage timing of the transmission transistor 17 and the polysilicon layer 19a are consistent to jointly control the transmission of photoelectrons in the photodiode 12.
[0039] Specifically, the substrate includes a substrate 10 and an epitaxial layer 11 located on the substrate 10. The substrate 10 provides an operating platform for subsequent processes and can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Specifically, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate 10 is a silicon substrate. The substrate 10 is doped with a second doping type, and the epitaxial layer 11 is doped with a second doping type, such as p-type doping.
[0040] Please continue to refer to this. Figure 1 A pinning layer 15 is further disposed within the substrate; specifically, a pinning layer 15 is disposed within the epitaxial layer 11. The pinning layer 15 is located on the photodiode 12 and below the polysilicon layer 19a. The pinning layer 15 is used to isolate the photodiode 12 from the upper surface of the substrate, that is, the pinning layer 15 is used to isolate the photodiode 12 from the upper surface of the epitaxial layer 11. The doping type of the photodiode 12 is different from the doping type of the pinning layer 15. The photodiode 12 is doped with a second doping type, while the pinning layer 15 is doped with a first doping type. In this embodiment, the first doping type is, for example, P-type, and the second doping type is, for example, N-type; that is, the pinning layer 15 is doped with P-type, and the photodiode 12 is doped with N-type. A first dielectric layer 18 is also disposed between the pinning layer 15 and the polysilicon layer. The material of the first dielectric layer 18 is, for example, silicon oxide. Silicon oxide typically generates defects and traps during its formation. The pinning layer 15 can isolate the first dielectric layer 18 and the photodiode 12, preventing defects or electrons in the first dielectric layer 18 from diffusing into the photodiode 12 and forming a dark current in the photodiode 12.
[0041] Please continue to refer to this. Figure 1The width of the polysilicon layer 19a is at least greater than or equal to the width of the photodiode 12. The thickness of the polysilicon layer 12 is, for example, 300 angstroms to 500 angstroms. A first contact plug 22a is formed on the polysilicon layer 19a, and a second contact plug 22b is formed on the transmission transistor 17. The first contact plug 22a and the second contact plug 22b are electrically connected to the same conductive layer, which is, for example, a metal layer. Specifically, the first contact plug 22a and the second contact plug 22b are electrically connected to a first portion 23a of the metal layer. Therefore, the voltage timing of the transmission transistor 17 is consistent with that of the polysilicon layer 19a. Specifically, when the transmission transistor 17 and the polysilicon layer 19a are simultaneously subjected to a negative voltage, the electric field on the polysilicon layer 19a causes holes in the substrate to accumulate towards the substrate surface, thereby providing better isolation between the oxide layer on the substrate surface and the photodiode 12 in the substrate. This prevents electrons or defects in the oxide layer on the substrate surface from diffusing into the photodiode 12, reducing the dark current of the CMOS image sensor. When both the transmission transistor 17 and the polysilicon layer 19a are simultaneously applied with a positive voltage, the electric field on the polysilicon layer 19a promotes the transfer of electrons within the photodiode 12, thus improving the image trailing phenomenon of the CMOS image sensor. Furthermore, this invention increases the full-well capacity of the CMOS image sensor through the electric field effect of the polysilicon layer without changing the ion implantation concentration in the pinning layer.
[0042] Please continue to refer to this. Figure 1 The first dielectric layer 18 between the polysilicon layer 19a and the pinning layer 15 simultaneously covers the top and sidewalls of the transmission transistor 17, and the first dielectric layer 18 serves to isolate the polysilicon layer 19a and the transmission transistor 17.
[0043] Please continue to refer to this. Figure 1 A floating gate diffusion region 16 is also provided within the substrate, that is, a floating gate diffusion region 16 is provided within the epitaxial layer 11. The floating gate diffusion region 16 is located within the epitaxial layer 11 on one side of the transmission transistor 17, and the floating gate diffusion region 16 is the drain region of the transmission transistor 17. The floating diffusion region 16 is used to receive electrons generated by the photodiode 12. A third contact plug 22c is formed on the floating diffusion region 16, and the third contact plug 22c is electrically connected to the second part 23b of the metal layer. The doping type of the photodiode 12 is the same as the doping type of the floating gate diffusion region 16, and the doping type of the photodiode 12 and the floating gate diffusion region 16 is the second doping type, and the doping type of the floating gate diffusion region 16 is N-type.
[0044] Please continue to refer to this. Figure 1The substrate also includes a shallow trench isolation structure 14, specifically within the epitaxial layer 11. This shallow trench isolation structure 14 isolates adjacent pixel units. Each pixel unit includes a photodiode 12, a transmission transistor 17, and a floating diffusion region 16. An isolation layer 13 is formed on the bottom and sidewalls of the shallow trench isolation structure 14. The ion doping concentration in the isolation layer 13 is greater than that in the epitaxial layer 11. Since the epitaxial layer 11 is P-type doped, the isolation layer 13 is also P-type doped, meaning the P-type ion doping concentration in the isolation layer 13 is greater than that in the epitaxial layer 11. This isolates defects or electrons in the shallow trench isolation structure 14 from entering the epitaxial layer 11. Because the P-type ion doping concentration in the isolation layer 13 is greater than that in the epitaxial layer 11, the isolation layer 13 is also referred to as a P+ isolation layer.
[0045] Figure 2 This is a flowchart illustrating a method for forming a CMOS image sensor according to an embodiment of the present invention. Figure 2 As shown, this utility model provides a method for forming a CMOS image sensor, comprising:
[0046] Step S10: Provide a substrate in which a photodiode is formed and a transmission transistor is formed on the substrate, wherein the projections of the photodiode and the transmission transistor do not overlap.
[0047] Step S20: A polysilicon layer is formed, the polysilicon layer being located on the photodiode and adjacent to the transmission transistor;
[0048] Step S30: Form a first contact plug and a second contact plug, wherein the first contact plug is located on the polysilicon layer and electrically connected to the polysilicon layer, and the second contact plug is located on the transmission transistor and electrically connected to the transmission transistor;
[0049] Step S40: A conductive layer is formed. The first contact plug and the second contact plug are electrically connected to the same conductive layer. The transmission transistor is electrically connected to the polysilicon layer. The voltage timing of the transmission transistor and the polysilicon layer is consistent, so as to jointly control the transmission of photoelectrons in the photodiode.
[0050] Figure 3 This is a schematic diagram of the structure of a CMOS image sensor after the formation of the first dielectric layer according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of a CMOS image sensor after the formation of a polycrystalline silicon material layer according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure of a CMOS image sensor after a patterned photoresist layer has been formed, according to an embodiment of the present invention. Figure 6This is a schematic diagram of the structure of a CMOS image sensor after the formation of a polycrystalline silicon layer according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure of the CMOS image sensor after the formation of the second dielectric layer according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the CMOS image sensor structure after the contact plug is formed according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 3 to 8 Specific embodiments of this utility model will be described in detail.
[0051] Please refer to Figure 3 A substrate is provided, comprising a substrate 10 and an epitaxial layer 11 located on the substrate 10. The substrate 10 provides an operating platform for subsequent processes and can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components; it can be a bare die or a wafer processed by epitaxial growth. Specifically, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate 10 is a silicon substrate. The substrate 10 is doped with a second doping type, and the epitaxial layer 11 is doped with a second doping type, such as p-type doping.
[0052] Please continue to refer to this. Figure 3A photodiode 12 is formed within the epitaxial layer 11. The photodiode 12 converts light into electrons, i.e., generates photoelectrons. A pinning layer 15 is formed on the photodiode 12 to isolate impurities or defects in the substrate from entering the photodiode 12. The doping type of the photodiode 12 is different from that of the pinning layer 15. The photodiode 12 is doped with a second doping type, while the pinning layer 15 is doped with a first doping type. In this embodiment, the first doping type is, for example, P-type, and the second doping type is, for example, N-type. That is, the pinning layer 15 is doped with P-type, and the photodiode 12 is doped with N-type. A transmission transistor 17 is formed on the epitaxial layer 11, and the projections of the photodiode 12 and the transmission transistor 17 do not overlap. A floating gate diffusion region 16 is also formed within the substrate. The floating gate diffusion region 16 is located within the epitaxial layer 11 on one side of the transmission transistor 17 and serves as the drain region of the transmission transistor 17. The floating diffusion region 16 is used to receive electrons generated by the photodiode 12. The doping type of the photodiode 12 is the same as that of the floating diffusion region 16, and both the photodiode 12 and the floating diffusion region 16 are of the second doping type. The floating diffusion region 16 is of the N-type doping type. The transfer transistor 17 is used to control the transfer of photoelectrons generated in the photodiode 12 to the floating diffusion region 16. A shallow trench isolation structure 14 is also formed in the epitaxial layer 11, which is used to isolate adjacent pixel units. Each pixel unit includes a photodiode 12, a transfer transistor 17, and a floating diffusion region 16. An isolation layer 13 is also formed on the bottom and sidewalls of the shallow trench isolation structure 14. The doping type in the isolation layer 13 is the same as that in the epitaxial layer 11, and the doping concentration in the isolation layer 13 is greater than that in the epitaxial layer 11. That is, the doping concentration of P-type ions in the isolation layer 13 is greater than that in the epitaxial layer 11, so as to isolate defects or electrons in the shallow trench isolation structure 14 from entering the epitaxial layer 11. Since the doping concentration of P-type ions in the isolation layer 13 is greater than that in the epitaxial layer 11, the isolation layer 13 is also called the P+ isolation layer.
[0053] Please continue to refer to this. Figure 3 A first dielectric layer 18 is formed, which is made of materials such as silicon oxide and can be formed using chemical vapor deposition or thermal oxidation processes. The first dielectric layer 18 covers the top surface of the epitaxial layer 11 and the sidewalls and top of the transmission transistor 17. The first dielectric layer 18 serves to protect the transmission transistor 17. It is worth noting that silicon oxide typically contains defects or charges. The pinning layer 15 isolates the first dielectric layer 18 from the photodiode 12, preventing the charges generated in the first dielectric layer 18 from diffusing into the photodiode 12 and forming dark current within the photodiode 12.
[0054] Please refer to Figure 4 A polycrystalline silicon material layer 19 is formed, which covers the first dielectric layer 18. The polycrystalline silicon material layer 19 can be formed using a chemical vapor deposition process.
[0055] Please refer to Figure 5 A patterned photoresist layer 20 is formed, which covers the polysilicon material layer 19 above the photodiode 12.
[0056] Please refer to Figure 6 Using a patterned photoresist layer 20 as a mask, a polysilicon material layer 19 is etched, leaving the polysilicon material layer 19 above the photodiode 12 to form a polysilicon layer 19a. The width d1 of the polysilicon layer 19a is at least greater than or equal to the width of the photodiode 12, so that the control of electrons or holes in the photodiode 12 by the voltage applied to the polysilicon layer 19a covers the entire photodiode 12. The thickness of the polysilicon layer 19a is, for example, 300 angstroms to 500 angstroms.
[0057] Please refer to Figure 7 A second dielectric layer 21 is formed, which covers the polysilicon layer 19a and the first dielectric layer 18. The material of the second dielectric layer 21 is, for example, silicon oxide, and the second dielectric layer 21 can be formed by chemical vapor deposition.
[0058] Please refer to Figure 8 A first contact hole, a second contact hole, and a third contact hole are formed in the second dielectric layer 21. A first contact plug 22a is formed in the first contact hole, a second contact plug 22b is formed in the second contact hole, and a third contact plug 22c is formed in the third contact hole. The first contact plug 22a is electrically connected to the polysilicon layer 19a, the second contact plug 22b is electrically connected to the transmission transistor 17, and the third contact plug 22c is electrically connected to the floating diffusion region 16.
[0059] Please refer to Figure 1 A conductive layer is formed, which in this embodiment is, for example, a metal layer. The metal layer is etched to retain the first portion 23a and the second portion 23b of the metal layer. The second portion 23b of the metal layer is electrically connected to the third contact plug 22c. The first portion 23a of the metal layer is electrically connected to both the first contact plug 22a and the second contact plug 22b, thus the polysilicon layer 19a is electrically connected to the transmission transistor 17. Next, a third dielectric layer 24 is formed, which covers the second dielectric layer 21, the first portion 23a of the metal layer, and the second portion 23b of the metal layer. The third dielectric layer 24 is chemically mechanically polished to make the third dielectric layer 24 flush with the top surfaces of the first portion 23a and the second portion 23b of the metal layer.
[0060] Figure 9 This is an electrical characteristic curve of the CMOS image sensor according to an embodiment of the present invention. Figure 10 This is a hole concentration curve within the substrate of a CMOS image sensor according to an embodiment of this utility model. Figure 9 As shown, the horizontal axis represents time, the main axis represents voltage, and the secondary axis represents electron concentration. The voltage timing of the polysilicon layer 19a is consistent with that of the transmission transistor 17. When the transmission transistor 17 and the polysilicon layer 19a are simultaneously connected to a negative voltage, the electric field on the polysilicon layer 19a causes holes in the substrate to accumulate towards the substrate surface, resulting in better isolation between the oxide layer on the substrate surface and the photodiode in the substrate. This prevents electrons or defects in the oxide layer on the substrate surface from diffusing into the photodiode 12, reducing the dark current of the CMOS image sensor. As shown by the green line (the technical solution of this application) and the blue line (the solution in the prior art), when the transmission transistor 17 and the polysilicon layer 19a are simultaneously connected to a positive voltage, the electron concentration decrease rate of the green line is faster and the slope is steeper than that of the blue line, meaning faster electron transport. The channel below the transmission transistor 17 opens, and the electric field on the polysilicon layer 19a promotes the transfer of electrons in the photodiode 12, improving the image trailing phenomenon of the CMOS image sensor. The blue and green arrows represent the electronic energy stored in the photodiode. It can be seen that the length of the green arrow is greater than the length of the blue arrow, meaning that the electronic energy within the photodiode 12 in this embodiment is greater than the electronic energy within the photodiode 12 in the prior art. And as... Figure 10 As shown, the horizontal axis represents the substrate thickness, and the vertical axis represents the hole concentration. Curve 1 (blue line) represents the control group, i.e., the prior art, and curve 2 (green line) represents the experimental group, i.e., the technical solution in this embodiment. This invention increases the hole concentration on the substrate surface through the electric field of the polysilicon layer 19a without changing the ion implantation concentration in the pinning layer 15, thus increasing the full-well pixel capacity of the CMOS image sensor.
[0061] In summary, in the CMOS image sensor provided by this embodiment, a polysilicon layer is disposed on the photodiode, and the polysilicon layer is electrically connected to the transmission transistor. The voltage timing of the transmission transistor and the polysilicon layer is consistent to jointly control the transmission of photoelectrons in the photodiode. This invention has unexpected effects. When the transmission transistor and the polysilicon layer are simultaneously applied with a negative voltage, the electric field on the polysilicon layer causes holes in the substrate to accumulate towards the substrate surface, resulting in better isolation between the oxide layer on the substrate surface and the photodiode within the substrate. This prevents electrons or defects in the oxide layer on the substrate surface from diffusing into the photodiode, reducing the dark current of the CMOS image sensor. When the transmission transistor and the polysilicon layer are simultaneously applied with a positive voltage, the electric field on the polysilicon layer promotes electron transfer within the photodiode, improving the image trailing phenomenon of the CMOS image sensor. Furthermore, this invention increases the full-well capacity of the CMOS image sensor through the electric field effect of the polysilicon layer without changing the ion implantation concentration in the pinning layer.
[0062] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention's technical solutions using the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention's technical solutions. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention's technical solutions, shall still fall within the protection scope of the present invention's technical solutions.
Claims
1. A CMOS image sensor, characterized in that, include: Base; A photodiode, located within the substrate, for generating photoelectrons; A polycrystalline silicon layer is located on the photodiode; A transmission transistor, the transmission transistor being located on the substrate and electrically connected to the polysilicon layer; The transmission transistor is synchronized with the voltage timing of the polysilicon layer to jointly control the transmission of photoelectrons in the photodiode.
2. The CMOS image sensor according to claim 1, characterized in that, A first contact plug is formed on the polysilicon layer, and a second contact plug is formed on the transmission transistor. The first contact plug and the second contact plug are electrically connected to the same conductive layer.
3. The CMOS image sensor according to claim 1, characterized in that, The width of the polycrystalline silicon layer is at least greater than or equal to the width of the photodiode.
4. The CMOS image sensor according to claim 1, characterized in that, The thickness of the polycrystalline silicon layer is 300 to 500 angstroms.
5. The CMOS image sensor according to claim 1, characterized in that, A pinning layer is also provided within the substrate. The pinning layer is located on the photodiode and below the polysilicon layer. The pinning layer is used to isolate the photodiode from the upper surface of the substrate.
6. The CMOS image sensor according to claim 5, characterized in that, The doping type of the photodiode is different from that of the pinning layer. The photodiode is doped with the second doping type, while the pinning layer is doped with the first doping type.
7. The CMOS image sensor according to claim 1, characterized in that, A first dielectric layer is disposed between the polysilicon layer and the transmission transistor, the first dielectric layer being used to isolate the polysilicon layer and the transmission transistor.
8. The CMOS image sensor according to claim 1, characterized in that, A floating gate diffusion region is also provided within the substrate. The floating gate diffusion region is located within the substrate on one side of the transmission transistor, and the floating gate diffusion region is the drain region of the transmission transistor.
9. The CMOS image sensor according to claim 8, characterized in that, The doping type of the photodiode is the same as the doping type of the floating gate diffusion region, and the doping type of the photodiode and the doping type of the floating gate diffusion region are a second doping type.
10. The CMOS image sensor according to claim 8, characterized in that, The substrate also includes a shallow trench isolation structure for isolating adjacent pixel units, which include a photodiode, a transmission transistor, and a floating diffusion region.