Automatic driving domain controller, control system and vehicle

Abstract

The embodiment of the utility model relates to an automatic driving domain controller, a control system and a vehicle. The automatic driving domain controller comprises at least two switch chips and at least one system-on-chip, wherein the switch chips are cascaded, each system-on-chip is connected with one switch chip in the at least two switch chips, and a plurality of ports of each switch chip are connected with a plurality of external physical layer chips in a one-to-one correspondence manner; the plurality of external physical layer chips are used for externally providing a plurality of physical layer interfaces; according to the embodiment of the utility model, the number of the network interfaces is expanded through the cascaded switch chips, so that the switch can be adapted to peripherals with more numbers and wider interface bandwidth ranges.

Description

TECHNICAL FIELD

[0001] The utility model relates to an automatic driving technology field especially relates to a kind of automatic driving domain controller, control system and vehicle. BACKGROUND

[0002] Automatic driving domain controller is one of the core components in the field of automatic driving of car, and in practical application, it needs to adapt to a larger number of external sensors, such as cameras, laser radars and millimeter wave radars, etc., with a wider interface bandwidth. However, the interfaces of various sensors are not unified at present, and there are different interfaces such as 100M T1, 1000M T1, 100M TX and 10000M TX. This requires the domain controller to be able to adapt to all interfaces to meet the access of different sensors.

[0003] The mainstream automatic driving domain controller in the market at present basically adopts a single switch chip scheme. The number and type of network interfaces provided by the switch chip are the number and type of network interfaces provided by the domain controller externally. For example, some domain controllers provide 8 non-adjustable 1000M T1 interfaces, and some provide 8 1000M TX and 2 1000M T1.

[0004] When the sensor interface that the domain controller needs to access is 100M T1, or the domain controller needs to access more than 10 external devices, the current automatic driving domain controller based on a single switch chip cannot meet the requirements, that is, the scalability and adaptability of the automatic driving domain controller are relatively poor. SUMMARY

[0005] The utility model provides a kind of automatic driving domain controller, control system and vehicle to solve the technical problem that the scalability and adaptability of the automatic driving domain controller of single switch chip are poor.

[0006] In the first aspect, the utility model provides a kind of automatic driving domain controller, including at least two switch chips and at least one system level chip;Wherein, each described switch chip cascade, each described system level chip is connected with one of the at least two switch chips, and the multiple ports of each described switch chip are connected with multiple external physical layer chips one by one, and the multiple external physical layer chips are used to provide multiple physical layer interfaces externally.

[0007] In some embodiments, when there is more than one system level chip, each system level chip is cascaded.

[0008] In some embodiments, the plurality of external physical layer chips comprises a first external physical layer chip and a second external physical layer chip; the first external physical layer chip is configured to provide a vehicle-mounted Ethernet interface with a dynamic configuration function externally; and the second external physical layer chip is configured to provide an industrial Ethernet interface with an adaptive function externally.

[0009] In some embodiments, further comprising a microprocessor chip; one of the at least two switch chips is connected to the microprocessor chip, and each of the system-level chips is connected to the microprocessor chip; and the microprocessor chip is further configured to provide a preset communication protocol interface externally.

[0010] In some embodiments, the microprocessor chip is further configured to: transmit a received configuration instruction to the first external physical layer chip through the switch chip to realize dynamic configuration of the first external physical layer chip; and the dynamic configuration comprises at least one of: a transmission rate and a master-slave configuration.

[0011] In some embodiments, a selection switch is arranged between the microprocessor chip and the switch chip, and the selection switch is configured to select a switch chip in communication with the microprocessor chip.

[0012] In some embodiments, at least one of the following is included: the switch chips are cascaded through an XFI bus; each of the system-level chips is connected to one of the at least two switch chips through an XFI bus; part of the ports of the switch chips are connected to the first external physical layer chip through an SGMII interface; the remaining ports of the switch chips are connected to the second external physical layer chip through an RGMII interface; and the switch chips are connected to the microprocessor chip through an RGMII interface.

[0013] In some embodiments, each of the switch chips, each of the system-level chips, the first external physical layer chip, and the second external physical layer chip supports PTP time synchronization.

[0014] In some embodiments, the at least two switch chips comprise a first switch chip and a second switch chip, and the at least one system-level chip comprises a first system-level chip and a second system-level chip; the first switch chip is cascaded with the second switch chip, the first system-level chip is cascaded with the second system-level chip, the first switch chip is connected to the first system-level chip, and the second switch chip is connected to the second system-level chip.

[0015] In some embodiments, the first port, the second port, the third port, the fourth port, the fifth port, the sixth port of the first switch chip and the first port, the second port, the third port, the fourth port, the fifth port, the sixth port of the second switch chip are connected with a first external physical layer chip; the seventh port of the first switch chip and the seventh port, the eighth port of the second switch chip are connected with a second external physical layer chip; the ninth port of the first switch chip is connected with the tenth port of the second switch chip, the seventh port of the first switch chip is connected with the microprocessor chip, the tenth port of the first switch is connected with the first system level chip, and the ninth port of the second switch chip is connected with the second system level chip.

[0016] In a second aspect, the utility model embodiment provides a kind of automatic driving domain control system, comprising the automatic driving domain controller and external device as any one of first aspect, and the external device is connected with the automatic driving domain controller by the multiple physical layer interfaces provided by the external physical layer chip.

[0017] In a third aspect, the utility model embodiment provides a kind of vehicle, comprising vehicle body and the automatic driving domain control system as described in second aspect.

[0018] The automatic driving domain controller, control system and vehicle provided by the utility model embodiment, the automatic driving domain controller at least two switch chips and at least one system level chip;Wherein, each the switch chip cascade, each the system level chip is connected with one of the at least two switch chips, the multiple ports of each the switch chip are connected with multiple external physical layer chips one by one, and the multiple external physical layer chips are used to provide multiple physical layer interfaces to outside;That is, the utility model embodiment expands network interface quantity by cascaded switch chip, and can be adapted to more number, wider interface bandwidth range external device. BRIEF DESCRIPTION OF DRAWINGS

[0019] The drawings incorporated into the specification and forming part of the specification, show the embodiments consistent with the utility model, and together with the specification for explaining the principle of the utility model.

[0020] In order to more clearly illustrate the technical scheme in the utility model embodiment or prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced as follows, and obviously, other drawings can be obtained by the drawings without creative labor for those skilled in the art.

[0021] Figure 1 The structure schematic diagram of the automatic driving domain controller provided by the utility model embodiment is shown.

[0022] Figure 2 Another structure schematic view of an automatic driving domain controller provided by the embodiment of the present application is provided;

[0023] Figure 3 Another structure schematic view of an automatic driving domain controller provided by the embodiment of the present application is provided;

[0024] Figure 4 Another structure schematic view of an automatic driving domain controller provided by the embodiment of the present application is provided;

[0025] Figure 5 A MCU dynamic configuration schematic view provided by the embodiment of the present application is provided;

[0026] Figure 6 A schematic view of connecting SOC and SWITCH based on XFI bus provided by the embodiment of the present application is provided;

[0027] Figure 7 A schematic view of connecting SWITCH and T1 PHY based on SGMII bus provided by the embodiment of the present application is provided;

[0028] Figure 8 A schematic view of connecting SWITCH and Tx PHY based on RGMII bus provided by the embodiment of the present application is provided;

[0029] Figure 9 A schematic view of connecting SWITCH and MCU based on RGMII bus provided by the embodiment of the present application is provided;

[0030] Figure 10 Another structure schematic view of an automatic driving domain controller provided by the embodiment of the present application is provided. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0032] It is to be noted that, in the present document, relational terms such as "first" and "second", and the like, can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0033] The automatic driving domain controller (which can be referred to as a domain controller for short) is one of the core components in the field of automatic driving of vehicles, and needs to adapt to various external sensors such as cameras, laser radars and millimeter wave radars in actual application. At present, various sensor interfaces are not unified, and there are different interfaces such as 100M T1, 1000M T1, 100M TX and 10000M TX, which requires the domain controller to be able to adapt to all interfaces to meet the access of different sensors.

[0034] At present, the mainstream domain controllers on the market basically adopt a single switch chip scheme, and the number and type of network interfaces provided by the switch chip are the number and type of network interfaces provided by the domain controller. For example, some domain controllers provide 8 1000M T1 interfaces (not supporting dynamic adjustment), and some domain controllers provide 8 1000M TX and 2 1000M T1 (T1 number is small, and total bandwidth is low).

[0035] When the sensor interface to be connected by the domain controller is 100M T1, such as a one-dimensional blind filling radar, or when the domain controller needs to access multiple Ethernet devices (such as more than 10), the domain controller based on a single switch chip cannot meet the requirements. That is, the scalability and adaptability of the current domain controller are relatively poor.

[0036] In order to solve the above technical problems, the technical concept of the present application is to cascade at least two switch chips to obtain more network interfaces and improve the scalability and adaptability of the domain controller.

[0037] Figure 1 A structure schematic diagram of an automatic driving domain controller provided by the embodiment of the present application, Figure 2 Another structure schematic diagram of an automatic driving domain controller provided by the embodiment of the present application, Figure 3 Still another structure schematic diagram of an automatic driving domain controller provided by the embodiment of the present application.Figures 1-3 As shown, the automatic driving domain controller comprises at least two switch chips and at least one system-level chip; wherein each switch chip is cascaded, each system-level chip is connected with one of the at least two switch chips, and a plurality of ports of each switch chip are connected with a plurality of external physical layer chips one by one, and the plurality of external physical layer chips are used to provide a plurality of physical layer interfaces externally.

[0038] Specifically, the automatic driving domain controller provided in the embodiment comprises two or more switch chips (SWITCH) and one or more system-level chips (SOC), each switch chip is cascaded, and each system-level chip is connected with one of the switch chips, which can be specifically divided into the following three cases:

[0039] ① When the number of SOC chips is less than the number of SWITCH chips, each SOC chip is connected with any one of the SWITCH chips. For example, in a case of one SOC chip and two SWITCH chips, the SOC chip can be connected with any one of the SWITCH chips, as shown in Figure 1 .

[0040] ② When the number of SOC chips is equal to the number of SWITCH chips, the SOC chips are connected with the SWITCH chips one by one, as shown in Figure 2 .

[0041] ③ When the number of SOC chips is greater than the number of SWITCH chips, the SOC chips can be connected with the SWITCH chips in a plurality of corresponding modes such as many-to-one and one-to-one. Generally, each SWITCH chip has at most two ports for connecting to the SOC chips, that is, the corresponding mode of two-to-one and one-to-one can be used for connection. As shown in Figure 3 , part of the SOC chips are connected with the SWITCH chips one by one, and each two of the other part of the SOC chips are connected to the same SWITCH chip.

[0042] In the embodiment, a plurality of ports (Port, referred to as P) of each switch chip are connected with a plurality of external physical layer chips (referred to as external PHY chips), and the external PHY chips provide a plurality of physical layer interfaces externally, which generally include a vehicle Ethernet interface (T1 interface) and an industrial Ethernet interface (Tx interface).

[0043] In some embodiments, in the case of more than one system-level chip, each system-level chip is cascaded. Continuing to refer to Figure 2 , 3 , if there are two or more SOC chips, in order to facilitate data sharing, the SOC chips can be connected in cascade.

[0044] The working process of the automatic driving domain controller provided by the embodiment is as follows: various external sensors transmit the collected data to the SOC chip through the multiple physical layer interfaces of the external PHY chip and the SWITCH chip; the SOC chip calculates and decides the received data by using high-level algorithms to generate corresponding control instructions; and the SOC chip transmits the control instructions to the actuators or other control units through CAN communication to realize automatic driving control of the vehicle.

[0045] In some embodiments, the plurality of external physical layer chips include a first external physical layer chip and a second external physical layer chip; the first external physical layer chip is configured to provide a vehicle-mounted Ethernet interface with a dynamic configuration function externally; and the second external physical layer chip is configured to provide an industrial Ethernet interface with an adaptive function externally.

[0046] Specifically, different external PHY chips can be adapted to the ports of the switch chip according to different requirements, for example, a T1 PHY chip corresponds to a T1 interface, and the T1 interface can be dynamically configured, for example, the transmission rate of the T1 interface can be initially set as a default value of 1000M, and then dynamically adjusted according to requirements, for example, adjusted to 100M, etc.; for another example, a Tx PHY chip corresponds to a Tx interface, and the Tx interface is adaptive to 10M / 100M / 1000M. It should be noted that the T1 interface and the Tx interface of the domain controller provided by the embodiment are in the same switch system, and data can be accessed to each other.

[0047] Figure 4 Another structure diagram of an automatic driving domain controller is provided by the embodiment of the utility model. As shown in Figure 4 In some embodiments, the automatic driving domain controller further includes a microprocessor chip; one of the at least two switch chips is connected with the microprocessor chip, each system-level chip is connected with the microprocessor chip, and the microprocessor chip further provides a preset communication protocol interface externally.

[0048] Specifically, the microprocessor chip provides a preset communication protocol interface (such as a CANFD interface) externally, various external sensors can transmit the collected data to the MCU chip through the CANFD interface, the MCU chip transmits the collected data to the corresponding system-level chip through the PHY-MAC interface; meanwhile, the data of the external sensors are transmitted to the corresponding system-level chip through the multiple physical layer interfaces of the external PHY chip, and the system-level chip fuses, processes and decides the data; finally, the system-level chip transmits the vehicle control instructions to the MCU chip through the PHY-MAC interface, and the MCU chip transmits the control instructions to the vehicle control related systems such as the motor controller, the braking system and the steering system through the CANFD interface to realize automatic driving control of the vehicle.

[0049] In some embodiments, the microprocessor chip is further configured to: the microprocessor chip is further configured to: transmit the received configuration instruction to the first external physical layer chip through the switch chip to realize dynamic configuration of the first external physical layer chip; wherein the dynamic configuration includes at least one of: transmission rate, master-slave configuration.

[0050] In some embodiments, a selection switch is arranged between the microprocessor chip and the switch chip, and the selection switch is configured to select the switch chip in communication with the microprocessor chip.

[0051] Specifically, the MCU develops a visual software which can configure the SWITCH and the external PHY chip through an external connected serial port device, and can realize the transmission rate (such as 100M, 1000M, etc.) of the T1 interface, the master-slave dynamic configuration and the like to enhance the adaptability of the switch. The master-slave configuration of the traditional T1 chip does not have adaptability, but in the present application, the master-slave mode of the external PHY chip can be modified through the MCU, for example, when the external device needs to transmit data to the switch chip, the external PHY chip can be configured in master mode through the MCU, at this time, the PHY chip is responsible for controlling the data sending process, and for example, when the external device needs to receive data sent from the switch chip, the external PHY chip can be configured in slave mode through the MCU, at this time, the external PHY chip will receive and process data according to the control signal from the master device. Further, the MCU uses the SMI bus to configure the SWITCH, and the SWITCH has a transparent function, so that the MCU can access the external PHY chip through the transparent function to complete the transmission rate and master-slave configuration of the external PHY chip.

[0052] In addition, the MCU chip has only one SMI communication bus, so the default address of each switch chip is the same. In order to reduce the difficulty of software development, a single address mode is used to access and configure the switch chip, therefore, a selection switch for SMI communication between the MCU chip and the switch chip is added, so that the MCU chip can ensure that it communicates with only one of the switch chips at a certain moment through the control of the selection switch, thereby avoiding the conflict of the same default address of the switch chips.

[0053] As Figure 5The MCU dynamic configuration diagram provided by the embodiment of the utility model, taking two switch chips as an example, the default addresses of the two SWI TCH chips are the same 0x00, the MCU can realize access and control of internal registers of the SWI TCH chip through the SMI bus, in addition, the SWI TCH chip itself supports SMI communication transparent transmission function, SMI communication data sent by the MCU and SMI communication data returned by the PHY chip mounted on the SWI TCH chip can be respectively transmitted to the external PHY and the MCU chip, so that the purpose that the MCU chip accesses and controls the PHY chip mounted on the SWI TCH chip through the SWI TCH chip is achieved.

[0054] In addition, the automatic driving domain controller also performs hardware IO configuration and external flash configuration, wherein the hardware IO configuration is to configure the configuration pin of the chip by using the pull-up resistor and the pull-down resistor, so that the chip has initialization configuration after power-on, that is, all ports of the SWITCH are enabled by default, the PHY of T1 is in the default 1000M master mode, and the PHY of TX is in the default adaptive start mode.

[0055] In some embodiments, at least one of the following is included: the switch chips are cascaded through an XFI bus; each system-level chip is connected with one of the at least two switch chips through an XFI bus; part of the ports of the switch chips are connected with the first external physical layer chip through an SGMII interface, and the remaining ports of the switch chips are connected with the second external physical layer chip through an RGMII interface; and the switch chips are connected with the microprocessor chip through an RGMII interface.

[0056] Specifically, the embodiment includes XFI, SGMII and RGMII three kinds of high-speed signals, and the three kinds of high-speed signals can be used for SOC and SWITCH interconnection and SWITCH and external PHY interconnection. Figure 6 The schematic diagram for connecting the SOC and the SWITCH based on the XFI bus provided by the embodiment of the utility model can reach 10Gbps in bandwidth; Figure 7 The schematic diagram for connecting the SWITCH and the T1 PHY based on the SGMII bus provided by the embodiment of the utility model has a bus bandwidth of 1000M; Figure 8A schematic diagram provided by the embodiment of the utility model for connecting SWITCH and Tx PHY based on RGMII bus, the bus bandwidth is 1000M. Figure 9 A schematic diagram provided by the embodiment of the utility model for connecting SWITCH and MCU based on RGMII bus, the bus bandwidth is 1000M.

[0057] In some embodiments, each of the switch chips, each of the system-level chips, the first external physical layer chip and the second external physical layer chip support PTP time synchronization.

[0058] Specifically, in addition to needing to adapt all peripheral sensors, the domain controller also needs all peripheral sensors to be able to achieve time synchronization, the embodiment provides simple and easy-to-implement PTP time synchronization, which is based on a Linux system of an SOC, so that the time precision of data communication of all networks of the switch is in the sub-microsecond level.

[0059] In some embodiments, the autonomous driving domain controller further comprises at least one of a power conversion circuit, a crystal oscillator circuit, a reset circuit, an address design circuit, a first interface protection circuit and a second interface protection circuit; wherein the power conversion circuit is configured to convert the power supply voltage provided by the vehicle-mounted power supply into the required voltage required by the switch chip, the first external physical layer chip and the second external physical layer chip; the crystal oscillator circuit comprises a first crystal oscillator circuit and a second crystal oscillator circuit, the switch chip, the first external physical layer chip and the second external physical layer chip are connected to the first crystal oscillator circuit, the first crystal oscillator circuit is configured to provide a crystal oscillator with a first preset frequency, the system-level chip is connected to the second crystal oscillator circuit, and the second crystal oscillator circuit is configured to provide a crystal oscillator with a second preset frequency; the switch chip, the first external physical layer chip and the second external physical layer chip are connected to the reset circuit, and the reset circuit is configured to restore the initial configuration of the autonomous driving domain controller; the address design circuit is configured to make the address of each port of a plurality of ports of each switch chip the same as the address of the connected first external physical layer chip or second external physical layer chip; the first interface protection circuit is connected to the vehicle-mounted Ethernet interface, and the second interface protection circuit is connected to the industrial Ethernet interface.

[0060] Specifically, the peripheral circuit of the domain controller mainly designs power supply, crystal oscillator, reset, address and protection. When designing the power supply, a DC\DC conversion circuit is used, which can convert the voltage of 12V of the battery on the car into the voltage levels of 3.3V, 1.5V and 1.05V required by SWITCH, the voltage levels of 3.3V, 1.2V and 0.75V required by T1 PHY, and the voltage levels of 3.3V and 1.0V required by TX PHY.

[0061] SWITCH, T1 PHY and TX PHY all need 25M crystal oscillator, which is provided by passive crystal oscillator, 10G network of SOC needs 156.25M differential crystal oscillator, which is also provided by passive crystal oscillator.

[0062] SWITCH chip and PHY chip both need a reset time to initialize at power-on time, the reset circuit adopts RC circuit design, and different resistance values and capacitance values are selected according to different reset times.

[0063] Multiple ports of the SWITCH are connected with external PHY chips, according to the recommended design of the SWITCH, the port address of the SWITCH is required to be the same as the PHY address, so that the default configuration of the SWITCH can directly communicate with the PHY and obtain the status of the PHY.

[0064] The external interfaces of the external PHY chips are all designed with EMC protection to ensure that they can pass EMC test normally. Currently, the ESD protection test passes the severe level test of air ±15KV and contact ±8KV.

[0065] The automatic driving domain controller provided by the embodiment of the utility model, including at least two switch chips and at least one system level chip, wherein, each switch chip is cascaded, each system level chip is connected with one of the at least two switch chips, multiple ports of each switch chip are connected with multiple external physical layer chips one by one, and the multiple external physical layer chips are used to provide multiple physical layer interfaces, namely, the embodiment can provide more network interfaces through the cascaded switch chips, and the network interfaces can be dynamically configured to improve the expansibility and adaptability, the network communication interface between the switch chip and the system level chip supports 10Gbps bandwidth at most, and simple and easy-to-implement PTP time synchronization is provided.

[0066] On the basis of the foregoing embodiment, Figure 10 Another structure schematic view of the automatic driving domain controller provided by the embodiment of the utility model is as follows, Figure 10 As shown in the figure,

[0067] The at least two switch chips include a first switch chip and a second switch chip, and the at least one system level chip includes a first system level chip and a second system level chip; the first switch chip is cascaded with the second switch chip, the first system level chip is cascaded with the second system level chip, the first switch chip is connected with the first system level chip, and the second switch chip is connected with the second system level chip.

[0068] Specifically, refer to Figure 10As shown, the automatic driving domain controller includes two switch chips SWITCH1 and SWITCH2, two system-level chips SOC1 and SOC2, SWITCH1 and SWITCH2 are cascaded, SOC1 and SOC2 are cascaded, SWITCH1 is connected with SOC1, and SWITCH2 is connected with SOC2.

[0069] In some embodiments, the first port, the second port, the third port, the fourth port, the fifth port, and the sixth port of the first switch chip, and the first port, the second port, the third port, the fourth port, the fifth port, and the sixth port of the second switch chip are connected with a first external physical layer chip; the seventh port of the first switch chip, and the seventh port and the eighth port of the second switch chip are connected with a second external physical layer chip; the ninth port of the first switch chip is connected with the tenth port of the second switch chip, the seventh port of the first switch chip is connected with the microprocessor chip, the tenth port of the first switch is connected with the first system-level chip, and the ninth port of the second switch chip is connected with the second system-level chip.

[0070] Reference Figure 10 As shown, in addition to the two switch chips SWITCH1 and SWITCH2 and the two system-level chips SOC1 and SOC2, the automatic driving domain controller of the embodiment further includes a microprocessor chip MCU. Among them, P1-P6 of SWITCH1 are connected with a first external PHY chip using an SGMII interface, the first external PHY chip provides a 1000M T1 interface (by default) externally, P8 of SWITCH1 is connected with a second external PHY chip using an RGMII interface, the second external PHY chip provides a 100\1000M adaptive Tx interface externally, and P7 of SWITCH1 is connected with the MCU using an RGMII, without generating an interface externally. P1-P6 of SWITCH2 are connected with a first external PHY chip using an SGMII interface, the first external PHY chip provides a 1000M T1 interface (by default) externally, P7 and P8 of SWITCH2 are connected with a second external PHY chip using an RGMII interface, and the second external PHY chip provides a 100\1000M adaptive Tx interface externally. The CANFD interface of the MCU chip is also connected with a plurality of external devices, such as a line control device, a millimeter wave radar, an ultrasonic radar, a bus display screen, and the like.

[0071] The automatic driving domain controller provided in the embodiment is cascaded through two switch chips, interfaces of the switch use external PHY chips, different PHY chips can be used for adaptation according to different requirements, and the automatic driving domain controller can provide up to 12 1000M / 100M dynamically configurable T1 interfaces and 3 10 / 100M / 1000M adaptive Tx interfaces; the two system-level chips can interact with external devices at a network bandwidth of 10 Gbps at most; and all the chips support PTP time synchronization. Figure 10 The automatic driving domain controller provided in the embodiment can basically adapt to mainstream Ethernet peripherals on the market, supports access of up to 15 Ethernet devices (for example, 12 T1 interfaces of P1-P6 of SWITCH1 and P1-P6 of SWITCH2, 3 Tx interfaces of P7 of SWITCH1, P7 and P8 of SWITCH2, and a total of 15 Ethernet interfaces in the above embodiment), and the data bandwidth between the SOC and the automatic driving domain controller reaches 10 Gbps, which can meet the demand for large data bandwidth in the future.

[0072] The utility model embodiment further provides an automatic driving domain control system, including the automatic driving domain controller and external equipment as described above, the external equipment is connected with the automatic driving domain controller through a plurality of physical layer interfaces provided by the external physical layer chip.

[0073] Specifically, the external equipment can include a camera, a laser radar and a millimeter wave radar, which are connected with the automatic driving domain controller through corresponding 100M / 1000M T1 interfaces or 100M / 1000M Tx interfaces, and the implementation principle and technical effects are similar to those of the above embodiment, which will not be described here.

[0074] The utility model embodiment further provides a vehicle, including vehicle body and the automatic driving domain control system as described above.

[0075] At least one of each module mentioned in the utility model embodiment can be at least partially implemented as a hardware circuit, for example, a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable way of integrating or packaging a circuit, a hardware or firmware, or any one of software, hardware and firmware or a proper combination of any of them. Alternatively, one or more of the above modules can be at least partially implemented as a computer program module, which can perform corresponding functions when running.

[0076] While this specification contains many specifics, these should not be construed as limitations on the scope of any inventions, but rather as descriptions of particular implementations of the inventions. Certain features that are, for clarity, described above in the context of separate implementations can also be provided in combinations of implementations. Conversely, various features that are, for brevity, described above in the context of a single implementation can also be provided separately or in any suitable subcombination. In addition, while features can be described above as being implemented in certain combinations and can be sought to be claimed as such, one or more features from a claimed combination can in some cases be removed from the combination, and the claim can be sought to be

[0077] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring this particular order, or sequential order, to achieve the desired results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0078] Accordingly, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, operations can be performed in a different order, and still achieve desirable results. In some embodiments, the processes depicted in the accompanying figures do not necessarily require the particular order illustrated, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0079] The previous description of the disclosed implementations is provided to enable any person skilled in the art to make or use the present application. Various modifications to these implementations will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the implementations shown herein but is to be accorded the widest scope consistent with the following claims, the principles and the practical application of the subject application herein disclosed.

Claims

1. An automatic driving domain controller, characterized by, The system comprises at least two switch chips and more than one system-level chip; The switch chips are connected in series, the system-level chips are connected in series, each system-level chip is connected with one of the at least two switch chips, and the ports of each switch chip are connected with the external physical layer chips one by one, and the external physical layer chips are used to provide various physical layer interfaces. The automatic driving domain controller further comprises a microprocessor chip, one of the at least two switch chips is connected with the microprocessor chip, and each system-level chip is connected with the microprocessor chip, and the microprocessor chip further provides a preset communication protocol interface. The external physical layer chips comprise a first external physical layer chip and a second external physical layer chip. The first external physical layer chip is used to provide a vehicle-mounted Ethernet interface with a dynamic configuration function, and the second external physical layer chip is used to provide an industrial Ethernet interface with an adaptive function. The microprocessor chip is further used to transmit the received configuration instruction to the first external physical layer chip through the switch chip to realize dynamic configuration of the first external physical layer chip.

2. The automatic driving domain controller according to claim 1, characterized by, The dynamic configuration comprises at least one of transmission rate and master-slave configuration.

3. The automatic driving domain controller according to claim 1, characterized in that, A selection switch is arranged between the microprocessor chip and the switch chip, and the selection switch is used to select the switch chip in communication with the microprocessor chip.

4. The automatic driving domain controller according to claim 1, characterized by, The system comprises at least one of the following: The switch chips are connected in series through an XFI bus. Each system-level chip is connected with one of the at least two switch chips through an XFI bus. Part of the ports of the switch chip are connected with the first external physical layer chip through an SGMII interface, and the remaining ports of the switch chip are connected with the second external physical layer chip through an RGMII interface. The switch chip is connected with the microprocessor chip through an RGMII interface.

5. The automatic driving domain controller according to any one of claims 1 to 3, characterized in that, Each switch chip, each system-level chip, the first external physical layer chip and the second external physical layer chip support PTP time synchronization.

6. The automatic driving domain controller according to any one of claims 1 to 3, characterized by, The at least two switch chips comprise a first switch chip and a second switch chip, and the at least one system-level chip comprises a first system-level chip and a second system-level chip. The first switch chip is connected with the second switch chip in series, and the first system-level chip is connected with the second system-level chip in series.

7. The automatic driving domain controller according to claim 6, characterized in that, The first port, the second port, the third port, the fourth port, the fifth port and the sixth port of the first switch chip, and the first port, the second port, the third port, the fourth port, the fifth port and the sixth port of the second switch chip are connected with the first external physical layer chip. The seventh port of the first switch chip, and the seventh port and the eighth port of the second switch chip are connected with the second external physical layer chip. The ninth port of the first switch chip is connected with the tenth port of the second switch chip, the seventh port of the first switch chip is connected with the microprocessor chip, the tenth port of the first switch is connected with the first system level chip, and the ninth port of the second switch chip is connected with the second system level chip.

8. An automated driving domain control system, characterized by, The automatic driving domain controller and an external device are included, and the external device is connected with the automatic driving domain controller through a plurality of physical layer interfaces provided by the external physical layer chip.

9. A vehicle characterized by comprising: The automatic driving domain control system includes a vehicle body and the automatic driving domain control system as claimed in claim 8.

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