Output buffer and electronic device

Abstract

The utility model provides an output buffer and electronic equipment. The output buffer comprises an input module, a logic circuit module and an output module. The input module comprises a comparator and a first resistor; the non-inverting input end of the comparator is used as a signal input end, and the inverting input end of the comparator is used for accessing reference voltage; one end of the first resistor is connected with the signal input end, and the other end is used for accessing power voltage; the logic circuit module comprises a plurality of cascaded phase inverters, and the input end of the logic circuit module is connected with the output end of the comparator; the output module comprises a first NMOS tube, a grid electrode is connected with the output end of the logic circuit module, a source electrode and a substrate are grounded, and a drain electrode serves as a signal output end and is used for being connected with a pull-up resistor. According to the output buffer, the input signal level and the reference voltage can be compared, the problem that the function of a device fails due to the fact that high and low levels input by a logic circuit module composed of phase inverters after irradiation cannot be correctly recognized is solved, and the input end of the output buffer can be suspended and is compatible with TTL levels.

Description

Technical Field

[0001] This application relates to the field of CMOS integrated circuit technology, specifically to an output buffer and electronic device, and more particularly to a CMOS open-drain output buffer and an electronic device comprising the same. Background Technology

[0002] CMOS (Complementary Metal Oxide Semiconductor) open-drain output buffers are buffer circuits with open-drain outputs manufactured using CMOS technology. They primarily function as interface circuits to buffer and drive input signals or shift logic levels (high to low or low to high). Due to their high current sinking capacity, CMOS open-drain output buffers can currently be directly used to drive TTL logic circuits, relays, or display devices.

[0003] For CMOS integrated circuits such as CMOS open-drain output buffers, thick gate oxide layers are typically used to meet voltage withstand requirements, and the thicker the gate oxide layer, the better the voltage withstand performance. However, under the influence of space radiation, the gate oxide layer ionizes, generating a large number of electron-hole pairs. Even at room temperature, electrons in SiO2 are mobile and can quickly move away from the SiO2 layer towards the positively biased gate electrode. On the other hand, holes in the SiO2 layer generate oxide charges Q. OX At this point, the charge on the positive oxide layer causes a shift in the turn-on voltage, and the amount of this shift is proportional to the square of the SiO2 thickness. Therefore, when a MOSFET with a thick gate oxide layer is exposed to long-term radiation, its turn-on voltage (threshold voltage) will shift. Specifically, the threshold voltage of an NMOS transistor decreases, and the threshold voltage of a PMOS transistor (which is negative) also decreases (i.e., its absolute value increases). Since existing output buffers typically include multiple cascaded CMOS inverters, if the threshold voltage of the MOSFET shifts, it is highly likely that the switching level of the CMOS inverter will decrease significantly.

[0004] Especially in CMOS circuits that are compatible with TTL (Transistor-Transistor Logic) logic levels (VIL is 0.8V, VIH is 2V), the switching level itself is relatively low (assuming the original switching point level is 1.4V). If it is further negatively drifted by more than 1V, the switching point level will be less than 0.4V, which will cause the low-level input voltage test to fail and even cause functional failure. Therefore, it cannot meet the requirement of TTL level compatibility for high and low input levels after irradiation.

[0005] Therefore, providing a CMOS open-drain output buffer that is radiation resistant, compatible with TTL levels, and withstands high voltage is a problem that needs to be solved. Utility Model Content

[0006] To address the aforementioned problems in the prior art, embodiments of this application provide an output buffer; embodiments of this application also provide an electronic device including the aforementioned output buffer.

[0007] To achieve the above objectives, a first aspect of this application provides an output buffer, specifically including an input module, a logic circuit module, and an output module, wherein:

[0008] The input module includes a comparator and a first resistor; the non-inverting input of the comparator serves as the signal input of the output buffer, and the inverting input is used to connect to the reference voltage; one end of the first resistor is connected to the signal input, and the other end is used to connect to the power supply voltage.

[0009] The logic circuit module includes multiple cascaded inverters, and the input of the logic circuit module is connected to the output of the comparator.

[0010] The output module includes a first NMOS transistor. The gate of the first NMOS transistor is connected to the output terminal of the logic circuit module, the source is grounded to the substrate, the drain serves as the signal output terminal of the output buffer, and the drain is used to connect a pull-up resistor.

[0011] In the aforementioned scheme, when no input signal is connected, the signal input terminal of the output buffer, i.e., the non-inverting input terminal of the comparator, is connected to the power supply voltage through the first resistor. At this time, the signal input terminal is connected to a high level, and the voltage connected to the signal input terminal is the power supply voltage; therefore, the signal input terminal can be left floating. When an input signal is connected, the power supply voltage is connected to the signal input terminal through the first resistor, forming a path and generating an input current. The voltage at the signal input terminal at this time is the voltage of the connected input signal. Furthermore, the magnitude of the current at the signal input terminal can be controlled by adjusting the resistance value of the aforementioned first resistor.

[0012] More importantly, the aforementioned solution adds an input module including a comparator. By comparing the input signal level with the reference voltage, it can avoid the problem that when the logic circuit module composed of inverters is directly used as the input terminal, the high and low input levels cannot be correctly identified after irradiation, which leads to the failure of device function.

[0013] Optionally, the input module also includes a second resistor and a third resistor connected in series; one end of the second resistor is connected to the power supply voltage, and the other end is connected to the inverting input of the comparator; one end of the third resistor is connected to the inverting input, and the other end is grounded.

[0014] The two resistors connected in series, namely the second and third resistors, act as a voltage divider, providing the comparator with the required reference voltage. By adjusting the resistance values ​​of the two resistors, different reference voltage values ​​can be obtained to meet different application requirements; for example, to ensure compatibility with TTL levels, the reference voltage can be adjusted to 1.4V.

[0015] Optionally, both the second and third resistors include multiple resistors connected in series. The multiple resistors in the second resistor and the multiple resistors in the third resistor have the same specifications, and their numbers may be the same or different.

[0016] In the aforementioned alternative scheme, when irradiation occurs, since the resistors have the same specifications, the change in resistance value of each resistor is also the same. Thus, the reference voltage is only related to the number of resistors that make up the second and third resistors, and the reference voltage can remain stable without being affected by irradiation.

[0017] Optionally, the comparator includes a first PMOS transistor and a second PMOS transistor of the same specifications, with the gate of the first PMOS transistor serving as the non-inverting input and the gate of the second PMOS transistor serving as the inverting input.

[0018] In this alternative scheme, since the first PMOS transistor and the second PMOS transistor have the same specifications, even if the threshold voltage of the two PMOS transistors drifts negatively by more than 1V after irradiation, it is still less than the power supply voltage minus the reference level, so the PMOS transistors can still work normally and the function of the comparator can be unaffected.

[0019] Furthermore, the comparator also includes:

[0020] The third PMOS transistor has its source and substrate connected to the power supply voltage, its gate grounded via a resistor, and its drain connected to the source of the first and second PMOS transistors.

[0021] The drain of the second NMOS transistor is connected to the drain of the first PMOS transistor, and the source is grounded to the substrate.

[0022] The third NMOS transistor has its drain connected to the drain of the second PMOS transistor, and its source grounded to the substrate.

[0023] in,

[0024] The gates of the second NMOS transistor and the third NMOS transistor are both connected to the drain of the first PMOS transistor;

[0025] The substrates of both the first and second PMOS transistors are used to connect to the power supply voltage, and the drain of the second PMOS transistor serves as the output terminal of the comparator.

[0026] Optionally, the number of inverters in the logic circuit module is odd. This is because the NMOS transistor in the output module is itself equivalent to an inverter, and this optional solution is designed to provide a non-inverting buffer, therefore the logic circuit module contains an odd number of inverter chains.

[0027] Optionally, a fourth resistor is also included, which serves as the aforementioned pull-up resistor. One end of the fourth resistor is connected to an external power supply, and the other end is connected to the signal output terminal, i.e., the drain of the aforementioned first NMOS transistor. By adjusting the resistance value of the fourth resistor and the voltage value of the external power supply, the output level can be pulled up to a maximum of 30V.

[0028] Optionally, the comparison module, logic circuit module, and output module may be formed in different layout areas of the same chip.

[0029] Optionally, the output buffer includes multiple channels; each channel includes multiple spaced layout areas that respectively set up the comparison module, logic circuit module and output module.

[0030] Optionally, the comparator and the first resistor in the comparison module can be located in different layout areas.

[0031] The second aspect of this application provides an electronic device, including the technical solution provided in the first aspect above, and the output buffer described in any of its optional solutions.

[0032] In summary, the output buffer provided in this embodiment, compared with the prior art, adds an input module, including a first resistor and a comparator. This not only allows the signal input terminal to be left floating, but also improves or solves the problem of low circuit input level switching point, parameter deviation, or functional failure caused by excessive MOSFET turn-on voltage drift after long-term irradiation in high-voltage CMOS integrated circuits with thick gate oxide layers. This ensures the correctness of signal transmission, the reliability of the output buffer function, and compatibility with TTL levels.

[0033] The electronic device provided in this application embodiment has the same advantages because it includes the above-described output buffer. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0035] Figure 1 This is a circuit schematic diagram of the output buffer provided in an embodiment of this application;

[0036] Figure 2 An exemplary circuit structure of a comparator in an output buffer provided in an embodiment of this application is shown;

[0037] Figure 3 This is an exemplary layout structure of the output buffer provided in the embodiments of this application;

[0038] Figure 4 The layout structure of one channel of the output buffer is shown in an embodiment of this application.

[0039] The image is labeled as follows:

[0040] 1: First map area; 2: Second map area;

[0041] 201: First sub-territory area, 202: Second sub-territory area, 203: Third sub-territory area, 204: Fourth sub-territory area. Detailed Implementation

[0042] In this specification, it will also be understood that when a component / module is referred to as being "connected to" other components / modules relative to them, such as "connected to" other components / modules, the component / module may be directly connected to or directly coupled to other components / modules, or there may be an intermediary third component / module; in addition, in the embodiments of this application, "connection" specifically refers to electrical connection.

[0043] This application will now be described more fully below with reference to the accompanying drawings. However, this application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided herein to make this application more detailed and complete, and to fully convey the scope of this application to those skilled in the art. The same reference numerals denote the same objects throughout the drawings.

[0044] In view of the two requirements for output buffers in practical applications, namely: (1) compatibility with TTL level and (2) high voltage resistance, as well as the problems that exist in the prior art, such as the signal input terminal not being able to be left floating and the difficulty in being compatible with TTL level after long-term irradiation, this application provides a CMOS open-drain output buffer that is irradiation resistant, compatible with TTL level and high voltage resistant.

[0045] like Figure 1 As shown, the CMOS open-drain output buffer provided in this embodiment includes an input module, a logic circuit module, and an output module, wherein the input module has a signal input terminal A, and the output module has a signal output terminal Y.

[0046] The connection methods of each module are as follows: Figure 1 As shown, the signal is input from the signal input terminal A, passes through the input module, logic circuit module and output module in sequence, forms an output signal and is output from the signal output terminal Y.

[0047] In an embodiment, such as Figure 1 As shown, the input module includes a first resistor R1 and a comparator COMP. The comparator COMP has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal of the comparator COMP serves as the signal input terminal A, and the inverting input terminal is used to connect to the reference voltage. One end of the first resistor R1 is connected to the signal input terminal A, and the other end is used to connect to the power supply voltage VCC.

[0048] Compared to existing technologies, the output buffer provided in the aforementioned embodiment adds an input module. The input module includes a first resistor R1 and a comparator COMP. When no input signal is connected, the signal input terminal A is connected to the power supply voltage VCC through the first resistor R1. At this time, the signal input terminal A remains at a high level, and the voltage remains at the power supply voltage VCC. Therefore, the signal input terminal A of the circuit can be left floating. When an input signal is connected, the power supply voltage VCC forms a path through the first resistor R1 to the signal input terminal A and outputs current to the signal input terminal A. The voltage at the signal input terminal A is the voltage of the connected input signal.

[0049] In an optional embodiment, the resistance value of the first resistor R1 can be adjusted to control the current magnitude at the input signal input terminal A.

[0050] In this embodiment, the reference voltage can be provided by a preset, adjustable constant voltage source, or, in a typical implementation, such as Figure 1 As shown, the input module further includes a second resistor R2 and a third resistor R3 connected in series; wherein, one end of the second resistor R2 is used to connect to the power supply voltage, and the other end is connected to the inverting input terminal of the comparator COMP; one end of the third resistor R3 is connected to the inverting input terminal of the comparator COMP, and the other end is grounded.

[0051] During operation, when an input signal is connected to signal input terminal A, the input signal enters comparator CMOP through the first resistor R1. The voltage obtained by the voltage divider of the second resistor R2 and the third resistor R3 serves as the reference voltage V. REF Connect the inverting input of comparator COMP, where the reference voltage V REF The voltage value is:

[0052]

[0053] In the formula V CC R1 represents the power supply voltage, and R2 and R3 represent the resistance values ​​of the second and third resistors, respectively.

[0054] In a typical embodiment, considering the reference voltage V after prolonged irradiation... REFThe second resistor R2 and the third resistor R3 must remain constant. Both are configured to consist of multiple resistors connected in series. These resistors have identical specifications, but the number of resistors in the second resistor R2 and the third resistor R3 can be the same or different. Therefore, by changing the number of resistors, the resistance values ​​of the second resistor R2 and the third resistor R3 can be adjusted, thereby further adjusting the reference voltage V. REF The voltage value. Since all resistors have identical specifications, the change in resistance value is also the same when exposed to radiation. Thus, the reference voltage V... REF It depends only on the number of resistors that make up the second resistor R2 and the third resistor R3, and thus remains unchanged regardless of the irradiation.

[0055] For example: the second resistor R2 consists of 6 resistors connected in series, and the third resistor R3 consists of 2 resistors connected in series. A total of 8 resistors use the same specifications. Thus, when the power supply voltage VCC = 5.6V, the reference voltage V... REF It can maintain a voltage of 1.4V and is not easily affected by radiation.

[0056] The comparator COMP in the input module is configured to compare the input signal and the reference voltage V. REF The system performs a comparison and outputs a control signal based on the comparison result.

[0057] In a typical embodiment, the circuit structure of the comparator COMP is as follows: Figure 2 As shown, the input signal IN and the reference voltage V REF The gates of two PMOS transistors, P1 and P2, are connected respectively, and the specifications and parameters of the two PMOS transistors are identical. This arrangement ensures that even if the threshold voltages of the two PMOS transistors drift negatively by more than 1V after irradiation, the absolute value of the threshold voltage will still be less than the power supply voltage minus the reference level. Therefore, the PMOS transistors can still operate normally, and the function of the comparator COMP will remain unaffected. Thus, if the input signal voltage is higher than the reference voltage V... REF If the input signal voltage is lower than the reference voltage V, then the output of comparator COMP will be high. REF If so, the output of comparator COMP will be low.

[0058] In a typical embodiment, the specific circuit structure of the comparator COMP is as follows: Figure 2 As shown, along the top-to-bottom direction in the diagram, it includes:

[0059] The third PMOS transistor P3 has its source and substrate connected to the power supply voltage VCC, its gate grounded via a resistor, and its drain connected to the sources of the first PMOS transistor P1 and the second PMOS transistor P2, respectively.

[0060] The substrates of the two PMOS transistors mentioned above, the first PMOS transistor P1 and the second PMOS transistor P2, are used to connect to the power supply voltage, and the drain of the second PMOS transistor P2 also serves as the output terminal OUT of the comparator.

[0061] The second NMOS transistor N2 has its drain connected to the drain of the first PMOS transistor P1, and its source grounded to the substrate. The third NMOS transistor N3 has its drain connected to the drain of the second PMOS transistor P2, and its source grounded to the substrate. The gates of both the second NMOS transistor N2 and the third NMOS transistor N3 are connected to the drain of the first PMOS transistor P1.

[0062] In summary, the input module in this embodiment compares the voltage of the input signal with the reference voltage using the comparator COMP. This avoids the problem that when the input signal is directly connected to the logic circuit module, the CMOS inverter cannot correctly identify the high and low levels of the input after irradiation, which could lead to functional failure.

[0063] In other words, the input module avoids the problem that external input signals directly enter the inverter, causing the level to shift and fail to correctly identify high and low input levels after prolonged irradiation.

[0064] Furthermore, by increasing or decreasing the number of resistors and adjusting the resistance values ​​of the second resistor R2 and the third resistor R3, different reference voltage values ​​can be generated to meet different usage requirements; for example, to be compatible with TTL levels, the reference voltage can be adjusted to 1.4V.

[0065] like Figure 1 As shown, the output of the input module, i.e., the output of the comparator COMP, is connected to the logic circuit module, and the control signal generated by the comparator COMP is output to the logic circuit module. The logic circuit module includes multiple cascaded inverters, or an inverter chain. For example, as shown... Figure 1 As shown, the logic circuit module includes n inverters cascaded sequentially, from INV1, INV2 to INVn.

[0066] Multiple cascaded inverters perform phase transformation on the aforementioned control signal. Since the input module of the previous stage has already compared the input signal voltage with the reference voltage to obtain a high or low level control signal, it is no longer necessary to use a PMOS transistor with a channel width smaller than that of an NMOS transistor. The first-stage inverter INV1 in the logic circuit unit can adopt a typical CMOS inverter input mode, that is, the channel width ratio of the POS transistor and the NMOS transistor is 2:1 (WP:WN = 2:1). Subsequently, multiple cascaded inverters can progressively increase the driving capability of the control signal, and then output the processed control signal to the output module.

[0067] In this embodiment, phase conversion between in-phase and out-of-phase can be achieved by adjusting the number of cascaded inverters, specifically by adjusting the odd and even numbers of the inverters.

[0068] In a typical embodiment, it is required to implement the function of an in-phase output buffer. Since the first NMOS transistor N1 contained in the output module is itself equivalent to an inverter, an odd number of cascaded inverters, such as 3, 5, or 7 inverters, are set in the logic circuit module to form an inverter chain.

[0069] like Figure 1 As shown, the output module is used to receive the control signal after it has been processed by the cascaded inverter in the logic circuit module, process the control signal, and then output it through the output terminal Y. Normally, the output terminal Y is also connected to a pull-up resistor.

[0070] In an embodiment, such as Figure 1 As shown, the output module includes a first NMOS transistor N1, and the output buffer provided in this embodiment has an open-drain function. The gate of the first NMOS transistor N1 is connected to the output terminal of the logic circuit module, the source is grounded to the substrate, the drain serves as the signal output terminal Y, and the drain is also used to connect a pull-up resistor.

[0071] In a typical embodiment, such as Figure 1 As shown, the pull-up resistor is specifically the fourth resistor R4. One end of the fourth resistor R4 is connected to the external power supply VDD, and the other end is connected to the signal output terminal Y. Preferably, the fourth resistor R4 is an external component, that is, it is not integrated into the same chip as the input module, logic circuit module, and output module. Of course, the fourth resistor R4 can also be part of the output module.

[0072] According to the aforementioned embodiment, if the signal output from the logic circuit module is high, the first NMOS transistor N1 is turned on, and the signal output terminal Y is low; conversely, if the signal output from the logic circuit module is low, the first NMOS transistor N1 is turned off, and under the combined action of the external power supply VDD and the fourth resistor R4, the signal output terminal Y is high.

[0073] By connecting a pull-up resistor, the output module can output a high voltage to meet the requirements of subsequent loads. For example, by adjusting the resistance value of the fourth resistor R4 and the voltage value of the external power supply VDD, the output signal voltage can be pulled up to a maximum of 30V.

[0074] Based on the aforementioned circuit structure and principle, this application embodiment further provides a layout that the output buffer can adopt.

[0075] like Figure 3As shown, the layout of the output buffer may include a first layout area 1 and a second layout area 2, wherein the first layout area 1 is located around the chip, and the second layout area 2 is located in the middle of the layout and is surrounded by the first layout area 1.

[0076] The first layout, area 1, contains multiple pads, and each pad can also have an electrostatic discharge (ESD) protection structure on both sides. For example... Figure 1 The circuit includes six signal input pads A1 to A6, six signal output pads Y1 to Y6, a power supply pad VCC, and a ground pad GND. The second version of the drawing, section 2, contains the aforementioned input module, logic circuit module, and output module.

[0077] Figure 3 Each dashed box in the diagram indicates a second layout area 2, and each second layout area 2 represents a channel. In this embodiment, a six-channel open-drain output buffer is used as an example. Figure 3 The layout structure shown includes 6 channels, that is, 6 second layout areas 2. It should be understood that the embodiments of this application are not limited to the aforementioned multi-output buffers, but can also be single-output buffers, meaning the chip layout includes only one channel. Furthermore, each channel corresponds to a signal input pad and a signal output pad.

[0078] Each channel's layout includes an input module, a logic circuit module, and an output module. Furthermore, each second layout area 2 comprises multiple spaced sub-layout areas. Preferably, the comparator and voltage divider resistors (if any) in the input module are located in one sub-layout area, and the first resistor is located in another sub-layout area.

[0079] In a typical embodiment, such as Figure 4 As shown, the layout within a channel includes: a first sub-layout area 201, a second sub-layout area 202, a third sub-layout area 203, and a fourth sub-layout area 204. The first sub-layout area 201 contains a first resistor R1 for providing pull-up resistance; the second sub-layout area 202 contains a comparator COMP, a second resistor R2 connected in series, and a third resistor R3; the third sub-layout area 203 contains the aforementioned logic circuit module; and the fourth sub-layout area 204 contains the aforementioned output module.

[0080] Each of the aforementioned sub-layout areas is connected to the power pad and ground pad in the first layout area 1 via metal wiring, and is connected to the signal input / output pad in the first layout area 1 according to the circuit structure described in the aforementioned embodiments, so as to obtain input signals or provide output signals.

[0081] In this embodiment, the fourth resistor R4 may not be located in any layout area, but may be connected as an external resistor structure to the signal output terminal Y on the (chip) layout area.

[0082] This application also provides an electronic device, including a load and the aforementioned output buffer. The input terminal of the load is connected to the output terminal of the output buffer, and the load may specifically be a relay, a display device, or the like.

[0083] In summary, the output buffer provided in this application embodiment allows the signal input terminal to be left floating. It can also improve or solve the problems of low input level switching point, out-of-tolerance parameters, or functional failure in integrated circuits of high-voltage CMOS process with thick gate oxide layers after long-term irradiation, ensuring the correctness of signal transmission, the reliability of chip function, and compatibility with TTL levels.

[0084] The above description is only a partial embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An output buffer, characterized in that, It includes an input module, a logic circuit module, and an output module, wherein: The input module includes a comparator and a first resistor; the non-inverting input of the comparator serves as the signal input of the output buffer, and the inverting input is used to connect to a reference voltage; one end of the first resistor is connected to the signal input, and the other end is used to connect to the power supply voltage. The logic circuit module includes multiple cascaded inverters, and the input terminal of the logic circuit module is connected to the output terminal of the comparator. The output module includes a first NMOS transistor, the gate of which is connected to the output terminal of the logic circuit module, the source of which is grounded to the substrate, and the drain of which serves as the signal output terminal of the output buffer. The drain is also used to connect a pull-up resistor.

2. The output buffer according to claim 1, characterized in that, The input module further includes a second resistor and a third resistor connected in series, wherein: One end of the second resistor is connected to the power supply voltage, and the other end is connected to the inverting input terminal of the comparator; One end of the third resistor is connected to the inverting input terminal, and the other end is grounded.

3. The output buffer according to claim 2, characterized in that, Both the second and third resistors consist of multiple resistors connected in series; The resistors in the second resistor have the same specifications as, or the same or different quantities as, the resistors in the third resistor.

4. The output buffer according to claim 1, characterized in that, The comparator includes a first PMOS transistor and a second PMOS transistor of the same specifications. The gate of the first PMOS transistor serves as the non-inverting input terminal, and the gate of the second PMOS transistor serves as the inverting input terminal.

5. The output buffer according to claim 4, characterized in that, The comparator further includes: The third PMOS transistor has its source and substrate connected to the power supply voltage, its gate grounded via a resistor, and its drain connected to the source of the first and second PMOS transistors. The second NMOS transistor has its drain connected to the drain of the first PMOS transistor, and its source grounded to the substrate. The third NMOS transistor has its drain connected to the drain of the second PMOS transistor, and its source grounded to the substrate. in, The gates of the second NMOS transistor and the third NMOS transistor are both connected to the drain of the first PMOS transistor; The substrates of both the first and second PMOS transistors are used to connect to the power supply voltage, and the drain of the second PMOS transistor serves as the output terminal of the comparator.

6. The output buffer according to claim 1, characterized in that, The number of inverters in the logic circuit module is odd.

7. The output buffer according to any one of claims 1 to 6, characterized in that, The output module also includes a fourth resistor, one end of which is connected to an external power supply, and the other end is connected to the drain of the first NMOS transistor.

8. An electronic device, characterized in that, Includes the output buffer as described in any one of claims 1-7.

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