Integrated circuit chip packaging device
By integrating the pin and die stage design, the heat dissipation channels are expanded, solving the miniaturization and high heat dissipation problems of power integrated circuit chip packaging, and achieving a high-efficiency packaging structure and cost reduction.
Patent Information
- Application Number
- CN202422119433.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-08-29
AI Technical Summary
How to achieve miniaturization and high heat dissipation performance in the packaging of power integrated circuit chips? Existing technologies struggle to balance the requirements of efficient heat dissipation and miniaturization in the packaging structure.
By adopting a design with widened pins and a substrate stage to form an integral structure, the heat dissipation channel is expanded. Through improvements to the surface mount structure and lead frame, the impedance of the connection lines and material costs are reduced. Combined with connection methods such as conductive adhesive and insulating adhesive, the package structure achieves high heat dissipation and miniaturization.
This achieves high heat dissipation performance and miniaturized packaging for integrated circuit chips, reduces assembly costs, expands the heat dissipation area, and improves product reliability and heat dissipation efficiency.
Smart Images
Figure CN223552535U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the semiconductor field, and in particular to an integrated circuit chip packaging device. Background Technology
[0002] The manufacturing process of integrated circuit (IC) chips mainly includes the following stages: IC chip design, IC chip fabrication, IC chip packaging, and IC chip testing. After IC chip fabrication, it typically has multiple solder pads. During the packaging stage, these solder pads are electrically connected to their corresponding lead frames. IC chips are usually attached to the lead frames using adhesives (conductive or insulating), solder paste, wire bonding, or ball bonding, thus electrically connecting the solder pads to the lead frame contacts and achieving the internal electrical connections within the IC chip's package structure.
[0003] With the increasing use of power integrated circuit chips, how to achieve miniaturization and high heat dissipation performance in the packaging of power integrated circuit chips has become a common concern in the semiconductor industry. Utility Model Content
[0004] In view of one or more of the problems mentioned above, an integrated circuit chip packaging apparatus according to an embodiment of the present invention is provided.
[0005] An integrated circuit chip packaging apparatus according to an embodiment of the present invention includes a lead frame, wherein the lead frame includes a plurality of pins and one or more die carriers, at least one of the plurality of pins is formed as a widened pin and integrally formed with one of the one or more die carriers.
[0006] In some embodiments, the front side of each of the one or more wafer carriers is used to carry an integrated circuit chip and be packaged inside an integrated circuit chip packaging apparatus, and the back side of at least one of the one or more wafer carriers is exposed outside the integrated circuit chip packaging apparatus.
[0007] In some embodiments, inside the integrated circuit chip packaging apparatus, one or more pins of a plurality of leads are raised relative to at least one die stage. The one or more die stages and the plurality of leads are on the same plane outside the integrated circuit chip packaging apparatus. The integrated circuit chip packaging apparatus employs a surface mount structure.
[0008] In some embodiments, one or more pins, excluding the widened pins, are connected together. The different widened pins of the multiple pins are each integrated with a different wafer stage in one or more wafer stages.
[0009] In some embodiments, the edges of multiple pins or one or more wafer stages are provided with adhesive locking holes. One or more wafer stages are provided with partial silver plating areas and / or V-grooves. Attached Figure Description
[0010] The present invention can be better understood from the following description of specific embodiments in conjunction with the accompanying drawings, wherein:
[0011] Figure 1A A top view of an integrated circuit chip packaging apparatus according to an embodiment of the present invention is shown;
[0012] Figure 1B A top view of another integrated circuit chip packaging apparatus according to an embodiment of the present invention is shown;
[0013] Figure 1C It shows Figure 1A and Figure 1B The diagram shows a cross-sectional view of the integrated circuit chip packaging device along AA;
[0014] Figure 1D It shows Figure 1B A top view of a variant of the integrated circuit chip packaging device shown;
[0015] Figure 2A It shows the use in Figure 1A A top view of the lead frame in the integrated circuit chip packaging device shown;
[0016] Figure 2B It shows the use in Figure 1A A top view of another lead frame in the integrated circuit chip packaging device shown;
[0017] Figure 2C It shows the use in Figure 1B A top view of the lead frame in the integrated circuit chip packaging device shown;
[0018] Figure 2D It shows Figures 2A to 2C The cross-sectional view of the lead frame along BB is shown;
[0019] Figure 3A , Figure 3B , Figure 3C ,and Figure 3D It shows Figure 2A A top view of the variant of the lead frame shown;
[0020] Figure 4A , Figure 4B , Figure 4C It shows Figure 1A and Figure 1DA top view of the internal packaging structure of the integrated circuit chip packaging device shown;
[0021] Figure 4D It shows Figure 1B The diagram shows a top view of the internal packaging structure of an integrated circuit chip packaging device. Detailed Implementation
[0022] The features and exemplary embodiments of various aspects of this utility model will now be described in detail. In the following detailed description, numerous specific details are set forth in order to provide a comprehensive understanding of this utility model. However, it will be apparent to those skilled in the art that this utility model can be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this utility model by illustrating examples of it. This utility model is by no means limited to any specific configuration set forth below, but covers any modifications, substitutions, and improvements to elements and components without departing from the spirit of this utility model. In the accompanying drawings and the following description, well-known structures and techniques are not shown in order to avoid causing unnecessary obscurity to this utility model. Furthermore, it should be noted that the term "connected to B" as used herein can mean "directly connected to B" or "indirectly connected to B via one or more other elements."
[0023] With the increasing use of power integrated circuit chips, achieving miniaturization, high integration, and high heat dissipation performance in integrated circuit chip packaging has become a common concern in the semiconductor industry. In view of this, an integrated circuit chip packaging apparatus according to an embodiment of the present invention is provided.
[0024] Figure 1A A top view of an integrated circuit chip packaging apparatus according to an embodiment of the present invention is shown. Figure 1B A top view of another integrated circuit chip packaging apparatus according to an embodiment of the present invention is shown. Figure 1A and Figure 1B As shown, an integrated circuit chip packaging apparatus according to an embodiment of the present invention includes an integrated circuit chip, a lead frame, and a package body, wherein the lead frame includes a plurality of pins and one or more die-mounted stages (e.g., Figure 1A and Figure 1B The stage shown in the dashed box), at least one of the multiple pins (e.g., pin 6 shown in Figure 1 and...). Figure 2APins 6 and 7 shown are formed as widened leads and integrally integrated with one of one or more die-mount stages to create a heat dissipation channel between the integrated circuit chip and the external environment outside the package. Here, the integrated circuit chip includes one or more of the following: control integrated circuit chips, power integrated circuit chips, and surface mount devices (e.g., surface mount resistors, surface mount capacitors, etc.).
[0025] Figure 1C It shows Figure 1A and Figure 1B The diagram shows a cross-sectional view of an integrated circuit chip packaging device along axis AA. Figure 1C As shown, in the integrated circuit chip packaging apparatus according to an embodiment of the present invention, the front side of each die carrier is used to hold the integrated circuit chip and is packaged inside the package body (i.e., packaged inside the integrated circuit chip packaging apparatus), and the back side of at least one die carrier is exposed outside the package body (i.e., exposed outside the integrated circuit chip packaging apparatus) to expand the heat dissipation channel between the integrated circuit chip and the external environment outside the package body. In some cases, multiple pins and each die carrier can be on the same plane outside the integrated circuit chip packaging apparatus. With the same package body top area, compared with the conventional small outline package (SOP) structure, this packaging structure can be made larger, achieve higher power output, and save pin length and reduce lead frame material costs.
[0026] Figure 1D A top view of yet another integrated circuit chip packaging apparatus according to an embodiment of the present invention is shown. Figure 1D As shown, in an integrated circuit chip packaging apparatus according to an embodiment of the present invention, for the same wafer stage, multiple widened pins (e.g., pin 6 and pin 7) can be integrally formed with the wafer stage to reduce external molding stress.
[0027] In some embodiments of the present invention, the integrated circuit chip packaging apparatus can adopt a surface mount structure, which is applicable to both the traditional reflow soldering process in printed circuit board assembly (PCBA) factories and the wave soldering process of the traditional through-hole structure. It can be used for assembly and surface mounting in various assembly plants, which greatly reduces assembly costs.
[0028] Figure 2A It shows the use in Figure 1A The top view of the lead frame in the integrated circuit chip packaging device shown. Figure 2B It shows the use in Figure 1A A top view of another lead frame in the integrated circuit chip packaging device shown. Figure 2A and Figure 2B As shown, in Figure 1AIn the integrated circuit chip packaging device shown, multiple pins (e.g., pins 2 to 5) other than the widened pin (e.g., pin 6) can be independent of each other or connected together. For the multiple pins connected together, the integrated circuit chip can be connected to these pins by aluminum or copper strip processes to reduce the impedance of the connection lines between the integrated circuit chip and these pins.
[0029] Figure 2C It shows the use in Figure 1B The top view of the lead frame in the integrated circuit chip packaging device shown. Figure 2C As shown, in Figure 1B In the integrated circuit chip packaging device shown, different widened pins can be integrated with different wafer stages to form a whole.
[0030] Figure 2D It shows Figures 2A to 2C The diagram shows a cross-sectional view of the lead frame along the BB line. Figure 2D As shown, in Figures 2A to 2C In the lead frame shown (i.e., inside the integrated circuit chip packaging device), the pins located on at least one side of the die carrier are raised relative to the die carrier to facilitate connection of the integrated circuit chip to the corresponding pins, while also facilitating the exposure of the back side of the die carrier to the outside of the package.
[0031] To expose the back side of the wafer stage to the outside of the integrated circuit chip packaging apparatus, the thickness of the integrated circuit chip packaging apparatus can be reduced. Furthermore, the wafer stage can be made larger (e.g., its area accounts for 10% to 90%, such as more than 30%, of the total area of the package of the integrated circuit chip packaging apparatus), enabling the wafer stage to support larger power integrated circuit chips while having a larger heat dissipation area exposed to the outside of the integrated circuit chip packaging apparatus.
[0032] Figure 3A , Figure 3B , Figure 3C ,and Figure 3D It shows Figure 2A A top view of the variant of the lead frame shown. Figure 3A and Figure 3B As shown, Figure 2A The leadframe pins and / or the edge of the wafer stage shown may be provided with locking holes (e.g., circular or semi-circular locking holes) to increase the bonding strength between the package and the leadframe, thereby increasing product reliability. Figure 3C As shown, Figure 2A The stage of the lead frame shown can be provided with a local silver-plated area (e.g., Figure 3C The shaded area (shown in the image) represents the silver plating area, which satisfies both the wire bonding requirements and increases product reliability. For example... Figure 3D As shown, Figure 2A The stage of the lead frame shown can be provided with a V-groove (e.g., Figure 3D The V-shaped groove (shown by two parallel lines in the horizontal and vertical directions) controls the quality of glue or solder overflow, meeting wire bonding requirements and increasing product reliability.
[0033] Figure 4A It shows Figure 1A and Figure 1D A top view of the internal packaging structure of the integrated circuit chip packaging device shown. Figure 4A As shown, in Figure 1A In the integrated circuit chip packaging apparatus shown, the die carrier stage can be implemented to have a larger size as needed to support a larger power integrated circuit chip, and a smaller control integrated circuit chip can be attached above the power integrated circuit chip; the die carrier stage is integral with at least one widened pin (e.g., pin 6), such that the heat dissipation channel between the power integrated circuit chip and the external environment outside the package includes at least one widened pin; the back side of the die carrier stage is exposed to the outside of the package, further expanding the heat dissipation channel between the power integrated circuit chip and the external environment outside the package.
[0034] Figure 4B It shows Figure 1A and Figure 1D A top view of another internal packaging structure of the integrated circuit chip packaging device shown. (See attached image.) Figure 4B As shown, in Figure 1A In the integrated circuit chip packaging apparatus shown, the power integrated circuit chip and the control chip can be laid flat on the die carrier stage. The power integrated circuit chip can be connected to multiple pins (e.g., pins 2 to 5 connected together) using aluminum ribbon. This reduces the impedance of the connection lines from the power integrated circuit chip to these pins and reduces the heat generation of the power integrated circuit chip. The die carrier stage is integrated with at least one widened pin (e.g., widened pin 6) so that the heat dissipation channel between the power integrated circuit chip and the external environment outside the package includes at least one widened pin. The back side of the die carrier stage is exposed to the outside of the package, further expanding the heat dissipation channel between the power integrated circuit chip and the external environment outside the package.
[0035] Figure 4C It shows Figure 1A and Figure 1D This is a top view of another internal packaging structure of the integrated circuit chip packaging device shown. (See attached image.) Figure 4C As shown, in Figure 1AIn the integrated circuit chip packaging apparatus shown, the power integrated circuit chip, the control chip, and the surface mount capacitor can be laid flat on the die carrier stage; the die carrier stage is connected to at least one widened pin (e.g., widened pin 6) so that the heat dissipation channel between the power integrated circuit chip and the external environment outside the package includes at least one widened pin; the back side of the die carrier stage is exposed to the outside of the package, further expanding the heat dissipation channel between the power integrated circuit chip and the external environment outside the package.
[0036] Figure 4D It shows Figure 1B A top view of the internal packaging structure of the integrated circuit chip packaging device shown. Figure 4D As shown, the power integrated circuit chip and the control chip can be respectively laid flat on two wafer carriers; the two wafer carriers are each integrated with at least one widened pin (e.g., integrated with pin 6 and pin 7 respectively), so that the heat dissipation channel between the power integrated circuit chip and the control chip and the external environment outside the package includes at least two widened pins; the back side of the wafer carrier is exposed to the outside of the package, further expanding the heat dissipation channel between the power integrated circuit chip and the external environment outside the package. Figure 4D The internal packaging structure shown can reduce the size of power integrated circuit chips while maintaining the required power, thereby reducing costs.
[0037] In some embodiments, integrated circuit chips and surface mount devices can be connected to the substrate or pins via different combinations of methods such as conductive adhesive, insulating adhesive, solder, solder paste, wire bonding, or bridging (base island to base island, base island to pin, or via insulating pads). In the case of wire bonding, metal wires of the same or different diameters between 0.7 and 2.0 mils can be used, as well as aluminum or copper strips of different specifications. Integrated circuit chips can be bonded to base islands using conductive adhesive, insulating adhesive, solder, or solder paste, or connected to base islands using wire bonding, or a hybrid method of bonding and wire bonding.
[0038] In some embodiments, a heat sink may be provided at the bottom of the package, and the gap between multiple pins located on at least one side of the die-mount stage and the heat sink is greater than or equal to 1.2 mm. The gap between at least one high-voltage pin and the surrounding pins and the heat sink is greater than or equal to 1.2 mm. This gap design of greater than or equal to 1.2 mm allows for a safe distance withstand voltage of 600V or higher when mounted on a board by the end customer. Additionally, the extension length of each pin relative to the package is between 0.3 and 0.6 mm, and the thickness of the die-mount stage and pins can be set in the range of 0.125 to 0.30 mm. The thickness of the integrated circuit chip packaging device can be set in the range of 1.0 to 1.5 mm, and it can adopt a common square or rectangular shape (sizes such as 5mm*5mm, 6mm*6mm, 4mm*6mm, 5mm*7mm, etc.).
[0039] It should be understood that although the above description uses a package structure with 6 or 7 pins as an example, the integrated circuit chip packaging device according to the embodiments of the present invention is not limited to including 6 or 7 pins, but may include more or fewer pins.
[0040] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details have been provided in the foregoing description to give a full understanding of embodiments of the present invention. However, those skilled in the art will recognize that the technical solutions of the present invention can be practiced without one or more of the specific details described, or other methods, components, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical concept of the present invention.
[0041] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.
Claims
1. An integrated circuit chip packaging device, characterized in that, The device includes a lead frame comprising a plurality of pins and one or more die carriers, at least one of the plurality of pins being formed as a wide pin and integrally formed with one of the one or more die carriers, the front side of each of the one or more die carriers being used to host an integrated circuit chip and be packaged inside the integrated circuit chip packaging apparatus, and the back side of at least one of the one or more die carriers being exposed outside the integrated circuit chip packaging apparatus.
2. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, Inside the integrated circuit chip packaging apparatus, one or more of the plurality of pins are raised relative to the at least one wafer stage.
3. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, The one or more wafer stages and the plurality of pins are located on the same plane outside the integrated circuit chip packaging device.
4. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, The integrated circuit chip packaging device adopts a surface mount structure.
5. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, One or more of the multiple pins, excluding the widened pin, are connected together.
6. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, The different widened pins among the plurality of pins form a whole with the different wafer stages among the one or more wafer stages.
7. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, The edges of the plurality of pins or the one or more substrate stages are provided with locking holes.
8. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, One or more wafer stages are provided with localized silver-plated areas.
9. The integrated circuit chip packaging apparatus according to claim 1, characterized in that, The one or more slide stages are provided with V-grooves.