Electronic device and electrostatic discharge protection circuit

Abstract

The utility model provides an electronic device and an electrostatic discharge protection circuit. The electronic device comprises a core logic circuit coupled to a power supply voltage rail and an operation voltage rail. During standard operation, the supply voltage rail has a supply voltage, the operating voltage rail has an operating voltage, and the post-driver voltage rail has an overdrive voltage greater than the operating voltage. The electronic device further includes a first power clamping circuit coupled to the supply voltage rail and the rear driver voltage rail; a low side logic high voltage rail coupled to a first end of the core logic circuit; and a first power-to-power clamping circuit coupled to the low-side logic high voltage rail and the rear driver voltage rail. The first power-to-power clamp circuit is configured to receive an electrostatic discharge (ESD) current between the rear driver voltage rail and the low-side logic high voltage rail.

Description

Technical Field

[0001] This invention relates to an electrostatic discharge protection circuit for electronic devices. Background Technology

[0002] Electrostatic discharge (ESD) protection circuitry is a circuit implemented within an electronic device to protect its components during an ESD event. An ESD event occurs when charge transfers from one component of an electronic device to another, or from one component to a device or circuit outside the device. For example, an ESD event may occur due to a lightning strike, a rapid power outage of the electronic device, or a sudden electrical short circuit between two components of the electronic device. Summary of the Invention

[0003] The electronic device of the present invention includes: a core logic circuit, a rear driver voltage rail, a first power clamping circuit, a low-side logic high voltage rail, and a first power-pair power clamping circuit. The core logic circuit has a first terminal coupled to a power supply voltage rail and a second terminal coupled to an operating voltage rail, the power supply voltage rail having a power supply voltage during standard operation, and the operating voltage rail having an operating voltage during the standard operation. The rear driver voltage rail has an overdrive voltage during the standard operation, the overdrive voltage being greater than the operating voltage. The first power clamping circuit has a first terminal coupled to the power supply voltage rail and a second terminal coupled to the rear driver voltage rail. The low-side logic high voltage rail is coupled to the first terminal of the core logic circuit. The first power-pair power clamping circuit has a first terminal coupled to the low-side logic high voltage rail and a second terminal coupled to the rear driver voltage rail, the first power-pair power clamping circuit being configured to receive electrostatic discharge (ESD) current between the rear driver voltage rail and the low-side logic high voltage rail.

[0004] The electrostatic discharge (ESD) protection circuit of the present invention includes a first power clamping circuit, a first power-to-power clamping circuit, and a second power-to-power clamping circuit. The first power clamping circuit has a first terminal coupled to a power supply voltage rail and a second terminal coupled to a rear driver voltage rail. The first power-to-power clamping circuit has a first terminal coupled to a low-side logic high voltage rail and a second terminal coupled to the rear driver voltage rail, the low-side logic high voltage rail being coupled to a low-voltage terminal of the core logic circuit. The first power-to-power clamping circuit is configured to receive the electrostatic discharge current between the rear driver voltage rail and the low-side logic high voltage rail. The second power-to-power clamping circuit has a first terminal coupled to a high-side logic low voltage rail and a second terminal coupled to the rear driver voltage rail, the high-side logic low voltage rail being coupled to a high-voltage terminal of the core logic circuit. The second power-to-power clamping circuit is configured to receive the electrostatic discharge current between the rear driver voltage rail and the high-side logic low voltage rail.

[0005] The method for protecting an electronic device according to the present invention includes: increasing the operating voltage of a core logic circuit at an operating voltage rail to an overdrive voltage at a rear driver voltage rail; maintaining a first voltage difference between the rear driver voltage rail and a power supply voltage rail using a first power clamping circuit, the first power clamping circuit being configured to receive an electrostatic discharge (ESD) current between the rear driver voltage rail and the power supply voltage rail during an electrostatic discharge event; and maintaining a second voltage difference between the rear driver voltage rail and a low-side logic high voltage rail using a first power-to-power clamping circuit, the low-side logic high voltage rail being coupled... To the low-voltage terminal of the core logic circuit, the first power-to-power clamping circuit is configured to receive the electrostatic discharge current between the rear driver voltage rail and the low-side logic high voltage rail during an electrostatic discharge event; and to maintain a third voltage difference between the rear driver voltage rail and the high-side logic low voltage rail using a second power-to-power clamping circuit, the high-side logic low voltage rail being coupled to the high-voltage terminal of the core logic circuit, the second power-to-power clamping circuit being configured to receive the electrostatic discharge current between the rear driver voltage rail and the high-side logic low voltage rail during an electrostatic discharge event. Attached Figure Description

[0006] The following detailed description will be better understood when read in conjunction with the accompanying drawings. Certain embodiments of the present disclosure are shown in the drawings for illustrative purposes. However, it should be understood that the invention is not limited to the precise arrangements and means shown. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the system and apparatus according to the invention and, together with the description, serve to explain the advantages and principles of the invention.

[0007] Figure 1An electronic device with electrostatic discharge (ESD) protection circuitry is illustrated according to some embodiments;

[0008] Figure 2 Detailed diagrams of electronic devices with ESD protection circuitry according to some embodiments are shown;

[0009] Figure 3 Detailed diagrams of an electronic device having an ESD protection circuit including a first diode string and a second diode string according to some embodiments are shown.

[0010] Figure 4 A detailed diagram of an electronic device having an ESD protection circuit including a first diode string, a second diode string, and a third diode string, according to some embodiments;

[0011] Figure 5 A power pair clamping circuit including a string of diodes is illustrated according to some embodiments;

[0012] Figure 6 A power-to-power clamping circuit including transistors is illustrated according to some embodiments;

[0013] Figure 7A A stacked p-channel transistor is illustrated for a power-to-power clamping circuit according to some embodiments;

[0014] Figure 7B The illustration depicts a stacked n-channel transistor for a power-to-power clamping circuit according to some embodiments;

[0015] Figure 8 A diagram illustrating an electronic device with ESD protection circuitry according to some embodiments;

[0016] Figure 9 A method for protecting an electronic device according to some embodiments is illustrated.

[0017] Explanation of icon numbers

[0018] 100: Electronic devices / electrical devices;

[0019] 101. VSS: Power supply voltage rail / power supply voltage node;

[0020] 102. VDDPST: Rear driver voltage rail;

[0021] 103. VDD: Operating voltage rail;

[0022] 104: ESD protection circuit;

[0023] 201: First power clamping circuit;

[0024] 202: Second power clamping circuit;

[0025] 203: Third power clamping circuit;

[0026] 204: Fourth power clamping circuit;

[0027] 205: First power pair power clamping circuit;

[0028] 206: Second power pair clamping circuit / Power pair clamping circuit;

[0029] 207. VDDL: Low-side logic high voltage rail;

[0030] 208. VSSH: High-side logic low-voltage rail;

[0031] 209: First diode;

[0032] 210: Second diode;

[0033] 211: Third diode;

[0034] 212: Fourth diode;

[0035] 301: First diode string;

[0036] 302: Second diode string;

[0037] 303: Third diode string;

[0038] 500: Form;

[0039] 601: Fourth diode string;

[0040] 701, R1: Resistors;

[0041] 702, C1: Capacitor;

[0042] 703, MP1: First p-channel transistor;

[0043] 704, MN1: First n-channel transistor;

[0044] 705, MN2: Second n-channel transistor;

[0045] 706: ESD transistor;

[0046] 707: First node;

[0047] 708: Second node;

[0048] 801: p-channel gate terminal node;

[0049] 802: Single p-channel transistor;

[0050] 803: Stacked p-channel transistor;

[0051] 804: n-channel gate terminal node;

[0052] 805: A single n-channel transistor;

[0053] 806: Stacked n-channel transistor;

[0054] 1001: First step;

[0055] 1002: Second step;

[0056] 1003: Third step;

[0057] 1004: Fourth step;

[0058] DSA1, DSA2~DSAN, DSB1, DSB2~DSBN, DSC1, DSC2~DSCN, DSD1, DSD2~DSDN: Diodes. Detailed Implementation

[0059] The following detailed description is provided to assist the reader in fully understanding the methods, apparatus, and / or systems described herein. Therefore, various modifications, refinements, and equivalents of the systems, apparatus, and / or methods described herein will be implied to those skilled in the art. Furthermore, for clarity and brevity, descriptions of well-known functions and structures may be omitted.

[0060] It should be understood that the phrases and terms used herein are for illustrative purposes and should not be considered restrictive. For example, the use of singular terms such as "a" is not intended to limit the number of items. Furthermore, for clarity, relational terms such as, but not limited to, "top," "bottom," "left," "right," "upper," "lower," "down," "up," and "side" are used in the description, and these relational terms are not intended to limit the scope of the invention or the appended claims. Moreover, it should be understood that any of the described features may be used alone or in combination with other features. Other systems, methods, features, and advantages of the invention will be apparent or will become apparent to those skilled in the art upon examination of the detailed description. All such additional systems, methods, features, and advantages are intended to be included within the scope of this description, included within the scope of the invention, and protected by the appended claims.

[0061] As described above, an ESD event occurs when charge is transferred from one component of an electronic device to another component of the same device, or when charge is transferred from one component of an electronic device to an external device or circuit. For example, an ESD event may occur due to a lightning strike, a rapid power outage of the electronic device, or a sudden electrical short circuit between two components of the electronic device. Some ESD protection circuits have several drawbacks. For example, an ESD protection circuit may include a path that allows ESD current from an ESD event to flow from an electrical component to a common node (e.g., a power supply voltage rail) of the electrical device. For electronic devices with nodes having overdrive voltage, this path to the common node can generate a large amount of ESD current, which can damage intermediate circuitry and components not equipped to handle such current. Such electronic devices may be defective and require costly repairs in the event of an ESD event—if such electronic devices are repairable.

[0062] In embodiments, it may be desirable for ESD protection circuitry to include ESD current paths that do not include critical components of the electrical device (e.g., logic circuitry). Furthermore, it may be desirable to have multiple ESD current paths that do not include shared nodes to improve the reliability and robustness of the electronic device. The embodiments disclosed herein relate to ESD current paths that do not include logic circuitry. Additionally, the embodiments disclosed herein reduce the magnitude of the ESD current generated due to a given ESD event.

[0063] Figure 1 An electronic device with electrostatic discharge (ESD) protection circuitry according to some embodiments is illustrated. Figure 1 In the illustrated example, electronic device 100 includes a power supply voltage rail VSS 101. The power supply voltage rail VSS 101 is coupled to electrical ground. Electronic device 100 further includes an operating voltage rail VDD 103 and a post-driver voltage rail VDDPST 102. The operating voltage rail VDD 103 is a node having the operating voltage of the core logic circuitry within electronic device 100 and is coupled to various components within electronic device 100. The post-driver voltage rail VDDPST 102 is a node having an overdrive voltage (e.g., the operating voltage of input / output (I / O) interface circuitry within electronic device 100). ESD protection circuitry 104 is coupled to the power supply voltage rail VSS 101, the operating voltage rail VDD 103, and the post-driver voltage rail VDDPST 102.

[0064] In some exemplary embodiments, electronic device 100 operates with an overdrive voltage. When electronic device 100 operates with an overdrive voltage, the level of the rear driver voltage rail VDDPST 102 is higher than the level of the operating voltage rail VDD 103. Furthermore, additional voltage rails may be present in electronic device 100, having a level different from both the operating voltage rail VDD 103 and the rear driver voltage rail VDDPST 102. Various electrical components and circuits of electronic device 100 may exist between the voltage rails. An electrostatic discharge (ESD) event can cause current to flow within electronic device 100 from one voltage rail to another (e.g., from the rear driver voltage rail VDDPST 102 to the operating voltage rail VDD 103). ESD protection circuitry 104 is configured to prevent damage to electrical components and circuits within electronic device 100 during an ESD event.

[0065] Figure 2 Detailed diagrams of electronic devices with ESD protection circuitry according to some embodiments are shown. Figure 2 In the exemplary embodiment shown, the ESD protection circuit 104 includes a low-side logic high voltage rail VDDL 207. The low-side logic high voltage rail VDDL 207 is coupled to a low-voltage terminal of the core logic circuit and contains a level representing a logic high ("1") relative to the low-voltage terminal. The ESD protection circuit 104 further includes a high-side logic low voltage rail VSSH 208. The high-side logic low voltage rail VSSH 208 is coupled to a high-voltage terminal of the core logic circuit and contains a level representing a logic low ("0") relative to the high-voltage terminal.

[0066] The ESD protection circuit 104 further includes a first power clamping circuit 201, which has a first terminal coupled to the power supply voltage rail VSS 101 and a second terminal coupled to the rear driver voltage rail VDDPST 102. The first power clamping circuit 201 maintains the voltage difference between the power supply voltage rail VSS 101 and the rear driver voltage rail VDDPST 102. For example, the rear driver voltage rail VDDPST 102 may have a level of approximately 1.2 volts. Therefore, the first power clamping circuit 201 can maintain a level of 1.2 volts between the power supply voltage rail VSS 101 and the rear driver voltage rail VDDPST 102. The first power clamping circuit 201 also prevents current from flowing from the power supply voltage rail VSS 101 to the rear driver voltage rail VDDPST 102, while allowing current to flow from the rear driver voltage rail VDDPST 102 to the power supply voltage rail VSS 101. For example, the first power clamping circuit 201 may include one or more diodes having a cathode coupled to a power supply voltage rail VSS101 and an anode coupled to a rear driver voltage rail VDDPST102. The ESD protection circuit 104 further includes a first diode 209. The first diode 209 has a cathode coupled to the rear driver voltage rail VDDPST102 and an anode coupled to the power supply voltage rail VSS101. The first diode 209 may be a diode separate from the first power clamping circuit 201, or it may represent a parasitic (e.g., internal) diode of the first power clamping circuit 201.

[0067] ESD protection circuit 104 further includes a second power clamping circuit 202, which has a first terminal coupled to a power supply voltage rail VSS101 and a second terminal coupled to a low-side logic high voltage rail VDDL207. The second power clamping circuit 202 maintains a voltage difference (e.g., 0.75 volts) between the power supply voltage rail VSS101 and the low-side logic high voltage rail VDDL207. The second power clamping circuit 202 also prevents current from flowing from the power supply voltage rail VSS101 to the low-side logic high voltage rail VDDL207, while allowing current to flow from the low-side logic high voltage rail VDDL207 to the power supply voltage rail VSS101. For example, the second power clamping circuit 202 may include one or more diodes having a cathode coupled to the power supply voltage rail VSS101 and an anode coupled to the low-side logic high voltage rail VDDL207. ESD protection circuit 104 further includes a second diode 210. The second diode 210 has a cathode coupled to the low-side logic high voltage rail VDDL 207 and an anode coupled to the power supply voltage rail VSS101. The second diode 210 may be a diode separate from the second power clamping circuit 202, or it may represent a parasitic (e.g., internal) diode of the second power clamping circuit 202.

[0068] ESD protection circuit 104 further includes a third power clamping circuit 203 having a first terminal coupled to a power supply voltage rail VSS 101 and a second terminal coupled to a high-side logic low voltage rail VSSH 208. The third power clamping circuit 203 maintains a voltage difference (e.g., 0.45 volts) between the power supply voltage rail VSS 101 and the high-side logic low voltage rail VSSH 208. The third power clamping circuit 203 also prevents current from flowing from the power supply voltage rail VSS 101 to the high-side logic low voltage rail VSSH 208, while allowing current to flow from the high-side logic low voltage rail VSSH 208 to the power supply voltage rail VSS 101. For example, the third power clamping circuit 203 may include one or more diodes having a cathode coupled to the power supply voltage rail VSS 101 and an anode coupled to the high-side logic low voltage rail VSSH 208. ESD protection circuit 104 further includes a third diode 211. The third diode 211 has a cathode coupled to the high-side logic low voltage rail VSSH 208 and an anode coupled to the power supply voltage rail VSS101. The third diode 211 may be a diode separate from the third power clamping circuit 203, or may represent a parasitic (e.g., internal) diode of the third power clamping circuit 203.

[0069] ESD protection circuit 104 further includes a fourth power clamping circuit 204 having a first terminal coupled to a power supply voltage rail VSS 101 and a second terminal coupled to an operating voltage rail VDD 103. The fourth power clamping circuit 204 maintains a voltage difference (e.g., 0.75 volts) between the power supply voltage rail VSS 101 and the operating voltage rail VDD 103. The fourth power clamping circuit 204 also prevents current from flowing from the power supply voltage rail VSS 101 to the operating voltage rail 103 while allowing current to flow from the operating voltage rail 103 to the power supply voltage rail VSS 101. For example, the fourth power clamping circuit 204 may include one or more diodes having a cathode coupled to the power supply voltage rail VSS 101 and an anode coupled to the operating voltage rail VDD 103. ESD protection circuit 104 further includes a fourth diode 212. The fourth diode 212 has a cathode coupled to the operating voltage rail 103 and an anode coupled to the power supply voltage rail VSS 101. The fourth diode 212 may be a diode separate from the fourth power clamping circuit 204, or it may represent a parasitic (e.g., internal) diode of the fourth power clamping circuit 204.

[0070] ESD protection circuit 104 further includes a first power-to-power clamp circuit 205 and a second power-to-power clamp circuit 206. The first power-to-power clamp circuit 205 has a first terminal coupled to a low-side logic high voltage rail VDDL 207 and a second terminal coupled to a rear driver voltage rail VDDPST 102. The first power-to-power clamp circuit 205 maintains a voltage difference (e.g., 0.45 volts) between the low-side logic high voltage rail VDDL 207 and the rear driver voltage rail VDDPST 102. The first power-to-power clamp circuit 205 also allows current to flow from the rear driver voltage rail VDDPST 102 to the low-side logic high voltage rail VDDL 207 while preventing current from flowing from the low-side logic high voltage rail VDDL 207 to the rear driver voltage rail VDDPST 102.

[0071] The second power pair clamping circuit 206 has a first terminal coupled to the high-side logic low voltage rail VSSH 208 and a second terminal coupled to the rear driver voltage rail VDDPST 102. The second power pair clamping circuit 206 maintains a voltage difference (e.g., 0.75 volts) between the high-side logic low voltage rail VSSH 208 and the rear driver voltage rail VDDPST 102. The second power pair clamping circuit 206 also allows current to flow from the rear driver voltage rail VDDPST 102 to the high-side logic low voltage rail VSSH 208 while preventing current from flowing from the high-side logic low voltage rail VSSH 208 to the rear driver voltage rail VDDPST 102. In addition to maintaining the levels between various voltage rails, the first power clamp circuit 201, the second power clamp circuit 202, the third power clamp circuit 203, and the fourth power clamp circuit 204, as well as the first power pair power clamp circuit 205 and the second power pair power clamp circuit 206, can provide current paths during ESD events.

[0072] For example, a first power pair clamping circuit 205 can provide a current path for current to flow from the rear driver voltage rail VDDPST 102 to the low-side logic high voltage rail VDDL 207 during an ESD event. Similarly, a second power pair clamping circuit 206 can provide a current path for current to flow from the rear driver voltage rail VDDPST 102 to the high-side logic low voltage rail VSSH 208 during an ESD event. Therefore, the first power pair clamping circuit 205 and the second power pair clamping circuit 206 can protect components and circuitry within the electronic device during an ESD event. For example, the electronic device 100 may include components coupled to a power supply voltage node VSS 101. By providing a current path from the rear driver voltage rail VDDPST 102 to the low-side logic high voltage rail VDDL 207, the first power pair power clamping circuit 205 can prevent ESD current from flowing between the rear driver voltage rail VDDPST 102 and the low-side logic high voltage rail VDDL 207 during an ESD event through components coupled to the power supply voltage node VSS 101.

[0073] Figure 3 Detailed diagrams are shown of an electronic device having an ESD protection circuit including a first diode string and a second diode string, according to some embodiments. Figure 3 In the illustrated exemplary embodiment, electronic device 100 includes a first diode string 301 having one or more diodes (DSA1, DSA2...DSAN). The first diode string 301 is coupled to a low-side logic high voltage rail VDDL 207 and a rear driver voltage rail VDDPST 107. The one or more diodes within the first diode string 301 may be coupled in series with each other. The one or more diodes include an anode coupled to the low-side logic high voltage rail VDDL 207 and a cathode coupled to the rear driver voltage rail VDDPST 107.

[0074] As described above, the first power clamping circuit 205 prevents current from flowing from the low-side logic high voltage rail VDDL 207 to the rear driver voltage rail VDDPST 107. Therefore, the first diode string 301 provides a path for ESD current during an ESD event causing electrostatic discharge from the low-side logic high voltage rail VDDL 207 to the rear driver voltage rail VDDPST 107. Furthermore, when the low-side logic high voltage rail VDDL 207 is logic high and the rear driver voltage rail VDDPST 107 is logic low, the first diode string 301 suppresses leakage current within the electronic device 100. In instances where the low-side logic high voltage rail VDDL 207 has a relatively high logic high level, a greater number of diodes can be implemented within the first diode string 301 to suppress leakage current within the electronic device 100.

[0075] The electronic device 100 further includes a second diode string 302 having one or more diodes (DSB1, DSB2...DSBN). The second diode string 302 is coupled to a high-side logic low voltage rail VSSH 208 and a rear driver voltage rail VDDPST 107. The one or more diodes within the second diode string 302 may be coupled in series with each other. The one or more diodes include an anode coupled to the high-side logic low voltage rail VSSH 208 and a cathode coupled to the rear driver voltage rail VDDPST 107.

[0076] As described above, the second power clamping circuit 206 prevents current from flowing from the high-side logic low voltage rail VSSH 208 to the rear driver voltage rail VDDPST 107. Therefore, the second diode string 302 provides a path for ESD current during an ESD event causing electrostatic discharge from the high-side logic low voltage rail VSSH 208 to the rear driver voltage rail VDDPST 107. Furthermore, the second diode string 302 suppresses leakage current within the electronic device 100 when the high-side logic low voltage rail VSSH 208 is at logic high and the rear driver voltage rail VDDPST 107 is at logic low. In instances where the high-side logic low voltage rail VSSH 208 has a relatively high logic high level, more diodes can be implemented within the second diode string 302 to suppress leakage current within the electronic device 100.

[0077] Figure 4 Detailed diagrams are shown of an electronic device having an ESD protection circuit including a first diode string, a second diode string, and a third diode string, according to some embodiments. Figure 4 In the illustrated exemplary embodiment, a third diode string 303 is used instead of Figure 2 and Figure 3 The illustrated third power clamping circuit 203. The third diode string 303 includes one or more diodes (DSC1, DSC2...DSCN) coupled in series with each other. The one or more diodes within the third diode string 303 include an anode coupled to the high-side logic low voltage rail VSSH 208 and a cathode coupled to the power supply voltage rail VSS101. The number of diodes implemented within the third diode string 303 depends on the level of the high-side logic low voltage rail VSSH 208 during standard operation. For example, more diodes may be implemented within the third diode string 303 to suppress leakage current from the higher-level high-side logic low voltage rail VSSH 208 during standard operation. In embodiments where the high-side logic low voltage rail VSSH 208 has a lower level during standard operation, fewer diodes (e.g., one or two diodes) may be implemented within the third diode string 303. This results in a reduced layout area and lower leakage current, thereby reducing cost and improving efficiency.

[0078]

[0079] Table 500

[0080] Table 500 above illustrates ESD current paths for various voltage rails according to some embodiments. In the exemplary embodiment illustrated in Table 500, the first column of Table 500 shows the electrostatic charging voltage rail for a given ESD event, and the first row of Table 500 shows the low voltage rail for a given ESD event. The cells of the table represent the ESD current paths for ESD events with a specified electrostatic charging voltage rail and a specified low voltage rail. For example, Table 500 shows that during an ESD event with the electrostatic charging voltage rail having the rear driver voltage rail VDDPST 102 and the low voltage rail having the operating voltage rail VDD 103, the ESD current path passes through the first power clamping circuit 201 and the fourth diode 212. Furthermore, Table 500 shows that during an ESD event with the electrostatic charging voltage rail having the rear driver voltage rail VDDPST 102 and the low voltage rail having the high-side logic low voltage rail VSSH 208, the ESD current path passes through the second power pair power clamping circuit 206.

[0081] Figure 5 A power-to-power clamping circuit including a string of diodes is illustrated according to some embodiments. Exemplary embodiments of the power-to-power clamping circuit may be implemented as a first power-to-power clamping circuit 205 or a second power-to-power clamping circuit 206. Figure 5 The power-to-power clamping circuit shown includes a series of four diodes (DSD1, DSD2...DSDN) coupled in series with each other, numbered 601. Figure 5 The power-to-power clamping circuit shown is an embodiment of the first power-to-power clamping circuit 205. The fourth diode string 601 includes an anode coupled to the rear driver voltage rail VDDPST 102 and a cathode coupled to the low-side logic high voltage rail VDDL 207. In this embodiment... Figure 5 The power-to-power clamping circuit shown is an embodiment of the second power-to-power clamping circuit 206, in which the fourth diode string 601 includes an anode coupled to the rear driver voltage rail VDDPST 102 and a cathode coupled to the high-side logic low voltage rail VSSH 208.

[0082] The number of diodes in the fourth diode string 601 depends on the voltage difference between the rear driver voltage rail VDDPST 102 and the low-side logic high voltage rail VDDL 207, or the voltage difference between the rear driver voltage rail VDDPST 102 and the high-side logic low voltage rail VSSH 208. For example, a higher voltage difference between the rear driver voltage rail VDDPST 102 and the low-side logic high voltage rail VDDL 207 or the high-side logic low voltage rail VSSH 208 may require more diodes in the fourth diode string 601 to suppress power leakage current during normal operation of the electronic device 100.

[0083] Figure 6 A power-to-power clamping circuit including transistors is illustrated according to some embodiments. Figure 6 In the illustrated exemplary embodiment, the power-to-power clamping circuit may be implemented as either or both of the first power-to-power clamping circuit 205 and the second power-to-power clamping circuit 206. Figure 6 The illustrated power-to-power clamping circuit includes resistor R1701, which has a first terminal coupled to the rear driver voltage rail VDDPST 102. Resistor R1701 has a second terminal coupled to the first terminal of capacitor C1702. Capacitor C1702 includes a second terminal coupled to either the low-side logic high rail VDDL 207 or the high-side logic low rail VSSH 208. Resistor R1701 and capacitor C1702 are connected in series with each other.

[0084] Figure 6 The illustrated power-to-power clamping circuit further includes a first n-channel transistor (e.g., a metal-oxide-semiconductor field-effect transistor, MOSFET) MN1704. The first n-channel transistor MN1704 includes a gate terminal coupled to a first node 707. The first node 707 is further coupled to a second terminal of a resistor R1701 and a first terminal of a capacitor C1702. The first n-channel transistor MN1704 further includes a drain terminal coupled to a second node 708 and a source terminal coupled to a low-side logic high voltage rail VDDL 207 or a high-side logic low voltage rail VSSH208. The second node 708 is coupled to a power supply voltage rail VSS101.

[0085] The power-to-power clamping circuit further includes a first p-channel transistor 703, which has a gate terminal coupled to a first node 707. The first p-channel transistor 703 further includes a source terminal coupled to a rear driver voltage rail VDDPST 102 and a drain terminal coupled to a second node 708. The power-to-power clamping circuit further includes a second n-channel transistor MN2705. The second n-channel transistor MN2705 includes a gate terminal coupled to a low-side logic high voltage rail VDDL 207 or a high-side logic low voltage rail VSSH 208, a source terminal coupled to the second node 708, and a drain terminal coupled to the rear driver voltage rail VDDPST 102. The power-to-power circuit further includes an ESD transistor 706. The ESD transistor 706 includes a gate terminal coupled to the second node 708. The ESD transistor 706 further includes a drain terminal coupled to the rear driver voltage rail VDDPST 102 and a source terminal coupled to the low-side logic high voltage rail VDDL 207 or the high-side logic low voltage rail VSSH 208.

[0086] The second n-channel transistor MN2705 is configured to disable (e.g., turn off) the ESD transistor 706 when the low-side logic high voltage rail VDDL 207 or the high-side logic low voltage rail VSSH 208 is in a logic high ("1") state and the rear driver voltage rail VDDPST is in a logic low ("0") state. This configuration reduces leakage current during operation of the electronic device 100. During standard operation of the electronic device 100, the low-side logic high voltage rail VDDL 207, the high-side logic low voltage rail VSSH 208, and the rear driver voltage rail VDDPST are in a logic high state. Therefore, during standard operation of the electronic device 100, the second n-channel transistor MN2705 is disabled. Since the ESD transistor 706 is connected to the power supply voltage rail VSS101, there is no leakage current from the low-side logic high voltage rail VDDL 207 or the high-side logic low voltage rail VSSH 208 to the parasitic diode of the ESD transistor 706 when the low-side logic high voltage rail VDDL 207 or the high-side logic low voltage rail VSSH 208 is in a logic high state and the rear driver voltage rail VDDPST 102 is in a logic low state.

[0087] Figure 7A A stacked p-channel transistor for a power-to-power clamping circuit is illustrated according to some embodiments. Figure 7A In the illustrated exemplary embodiment, a single p-channel transistor 802 may be replaced by a stacked p-channel transistor 803. The stacked p-channel transistor 803 includes a plurality of p-channel transistors. A single p-channel transistor 802 may represent, for example... Figure 6The first p-channel transistor MP1703 is illustrated. The stacked p-channel transistor 803 includes a p-channel gate terminal node 801 coupled to the gate terminal of each of the plurality of p-channel transistors. The source terminal sub-nodes of the p-channel transistors within the stacked p-channel transistor 803 are coupled to the drain terminal of the adjacent p-channel transistor.

[0088] Figure 7B This illustration depicts a stacked n-channel transistor for a power-to-power clamping circuit according to some embodiments. Figure 7B In the exemplary embodiment shown, a single n-channel transistor 805 may be replaced by a stacked n-channel transistor 806. The stacked n-channel transistor 806 includes a plurality of n-channel transistors. A single n-channel transistor 805 may represent, for example... Figure 6 The first n-channel transistor MN1704 or the second n-channel transistor 705 are illustrated. The stacked n-channel transistor 806 includes an n-channel gate terminal node 804 coupled to the gate terminal of each of the plurality of n-channel transistors. The drain terminal node of the n-channel transistor within the stacked n-channel transistor 806 is coupled to the source terminal of the adjacent n-channel transistor.

[0089] Figure 8 A diagram illustrating an electronic device with ESD protection circuitry according to some embodiments is provided. Figure 8 In the illustrated exemplary embodiment, the first power pair power clamping circuit 205 includes a plurality of diodes having an anode coupled to the rear driver voltage rail 102 and a cathode coupled to the low-side logic high voltage rail VDDL 207 or the high-side logic low voltage rail VSSH 208. Figure 8 The first power pair clamping circuit 205 illustrated can be, for example... Figure 5 The first power pair power clamping circuit 205 is shown in the figure. Figure 8 The illustrated second power pair clamping circuit 206 can be substantially similar to Figure 6 The illustrated power-to-power clamping circuit 206. The remaining components of the electronic device 100 may be substantially similar to... Figure 4 Components of the illustrated electronic device 100.

[0090] Figure 9 A method for protecting an electronic device according to some embodiments is illustrated. Method 1000 includes a first step 1001, in which the operating voltage of the core logic circuit at the operating voltage rail is increased to an overdrive voltage at the rear driver voltage rail. For example... Figure 1 and Figure 2As shown, the electronic device 100 includes an operating voltage rail 103. The operating voltage at the operating voltage rail 103 is increased to an overdrive voltage at the rear driver voltage rail 102. The method 1000 further includes a second step 1002, in which a first voltage difference between the rear driver voltage rail and the power supply voltage rail is maintained using a first power clamping circuit configured to receive electrostatic discharge (ESD) current between the rear driver voltage rail and the power supply voltage rail during an ESD event. Figure 2 As shown, the first power clamping circuit 201 maintains a first voltage difference between the rear driver voltage rail 102 and the power supply voltage rail 101. As shown in Table 500, the first power clamping circuit is configured to receive ESD current between the rear driver voltage rail 102 and the power supply voltage rail 101 during an ESD event.

[0091] Method 1000 further includes a third step 1003, in which a first power-to-power clamping circuit is used to maintain a second voltage difference between the post-driver voltage rail and the low-side logic high voltage rail. The first power-to-power clamping circuit is configured to receive ESD current between the post-driver voltage rail and the low-side logic high voltage rail during an ESD event. Figure 2 As shown, the first power pair clamping circuit 205 maintains a second voltage difference between the rear driver voltage rail 102 and the low-side logic high voltage rail VDDL 207. Furthermore, Table 500 shows that the first power pair clamping circuit 205 is configured to receive the ESD current between the rear driver voltage rail 102 and the low-side logic high voltage rail VDDL 207 during an ESD event.

[0092] Method 1000 further includes a fourth step 1004, in which a second power pair clamping circuit is used to maintain a third voltage difference between the post-driver voltage rail and the high-side logic low voltage rail. The second power pair clamping circuit is configured to receive ESD current between the post-driver voltage rail and the high-side logic low voltage rail during an ESD event. Figure 2 As shown, the second power pair clamping circuit 206 maintains a third voltage difference between the rear driver voltage rail 102 and the high-side logic low voltage rail VSSH 208. Furthermore, Table 500 shows that the second power pair clamping circuit 206 is configured to receive the ESD current between the rear driver voltage rail 102 and the high-side logic low voltage rail VSSH 208 during an ESD event.

[0093] This document describes systems and methods. In one example, an electronic device includes core logic circuitry having a first terminal coupled to a power supply voltage rail and a second terminal coupled to an operating voltage rail. The power supply voltage rail has a power supply voltage during standard operation, while the operating voltage rail has an operating voltage during standard operation. The electronic device further includes a rear driver voltage rail having an overdrive voltage during standard operation. The overdrive voltage is greater than the operating voltage. The electronic device further includes a first power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the rear driver voltage rail. The electronic device further includes a low-side logic high voltage rail coupled to the first terminal of the core logic circuitry. The electronic device further includes a first power-to-power clamping circuit having a first terminal coupled to the low-side logic high voltage rail and a second terminal coupled to the rear driver voltage rail. The first power-to-power clamping circuit is configured to receive electrostatic discharge (ESD) current between the rear driver voltage rail and the low-side logic high voltage rail.

[0094] In the above embodiments, the first power pair power clamping circuit includes a forward diode string, the forward diode string including an anode coupled to the rear driver voltage rail and a cathode coupled to the low-side logic high voltage rail.

[0095] In the above embodiments, the first power pair power clamping circuit includes a resistor and a capacitor connected in series, as well as a plurality of transistors.

[0096] In the above embodiments, the electronic device further includes a second power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the low-side logic high voltage rail.

[0097] In the above embodiments, the electronic device further includes a first diode string comprising one or more diodes, the first diode string having an anode coupled to the low-side logic high voltage rail and a cathode coupled to the rear driver voltage rail.

[0098] In the above embodiments, the electronic device further includes: a high-side logic low voltage rail coupled to the second terminal of the core logic circuit; and a second power pair power clamping circuit having a first terminal coupled to the high-side logic low voltage rail and a second terminal coupled to the rear driver voltage rail, the second power pair power clamping being configured to receive electrostatic discharge current between the rear driver voltage rail and the high-side logic low voltage rail during a second electrostatic discharge event.

[0099] In the above embodiments, the second power pair power clamping circuit includes a forward diode string, the forward diode string including an anode coupled to the rear driver voltage rail and a cathode coupled to the high-side logic low voltage rail.

[0100] In the above embodiments, the second power pair power clamping circuit includes a resistor and a capacitor connected in series, as well as a plurality of transistors.

[0101] In the above embodiments, the electronic device further includes a second diode string comprising one or more diodes, the second diode string including an anode coupled to the high-side logic low voltage rail and a cathode coupled to the rear driver voltage rail.

[0102] In the above embodiments, the electronic device further includes a third power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the high-side logic low voltage rail.

[0103] In the above embodiments, the electronic device further includes: a first diode having an anode coupled to the power supply voltage rail and a cathode coupled to the rear driver voltage rail; a second diode having an anode coupled to the power supply voltage rail and a cathode coupled to the low-side logic high voltage rail; a third diode having an anode coupled to the power supply voltage rail and a cathode coupled to the high-side logic low voltage rail; and a fourth diode having an anode coupled to the power supply voltage rail and a cathode coupled to the operating voltage rail.

[0104] In the above embodiments, the electronic device further includes a fourth power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the operating voltage rail.

[0105] In another example, an ESD protection circuit includes a first power clamping circuit having a first terminal coupled to a power supply voltage rail and a second terminal coupled to a rear driver voltage rail. The ESD protection circuit further includes a first power-to-power clamping circuit having a first terminal coupled to a low-side logic high voltage rail and a second terminal coupled to a rear driver voltage rail. The low-side logic high voltage rail is coupled to a low-voltage terminal of the core logic circuit. The first power-to-power clamping circuit is configured to receive ESD current between the rear driver voltage rail and the low-side logic high voltage rail. The ESD protection circuit further includes a second power-to-power clamping circuit having a first terminal coupled to a high-side logic low voltage rail and a second terminal coupled to a rear driver voltage rail. The high-side logic low voltage rail is coupled to a high-voltage terminal of the core logic circuit. The second power-to-power clamping circuit is configured to receive ESD current between the rear driver voltage rail and the high-side logic low voltage rail.

[0106] In the above embodiments, the electrostatic discharge protection circuit further includes: a second power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the low-side logic high voltage rail, the second power clamping circuit being configured to receive electrostatic discharge current between the power supply voltage rail and the low-side logic high voltage rail; a third power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the high-side logic low voltage rail, the third power clamping circuit being configured to receive electrostatic discharge current between the power supply voltage rail and the high-side logic low voltage rail; and a fourth power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the operating voltage rail, the fourth power clamping circuit being configured to receive electrostatic discharge current between the power supply voltage rail and the operating voltage rail.

[0107] In the above embodiments, the first power pair power clamping circuit includes a forward diode string, the forward diode string including an anode coupled to the rear driver voltage rail and a cathode coupled to the low-side logic high voltage rail.

[0108] In the above embodiments, the first power pair power clamping circuit includes a resistor and a capacitor connected in series, as well as a plurality of transistors.

[0109] In the above embodiments, the second power pair power clamping circuit includes a forward diode string, the forward diode string including an anode coupled to the rear driver voltage rail and a cathode coupled to the low-side logic high voltage rail.

[0110] In the above embodiments, the second power pair power clamping circuit includes a resistor and a capacitor connected in series, as well as a plurality of transistors.

[0111] In another example, a method for protecting an electronic device includes increasing the operating voltage of the core logic circuit at an operating voltage rail to an overdrive voltage at a rear driver voltage rail. The method further includes using a first power clamping circuit to maintain a first voltage difference between the rear driver voltage rail and a power supply voltage rail. The first power clamping circuit is configured to receive ESD current between the rear driver voltage rail and the power supply voltage rail during an ESD event. The method further includes using a first power-to-power clamping circuit to maintain the first voltage difference between the rear driver voltage rail and the power supply voltage rail. The first power clamping circuit is configured to receive ESD current between the rear driver voltage rail and a low-side logic high voltage rail during an ESD event. The method further includes using a second power-to-power clamping circuit to maintain a third voltage difference between the rear driver voltage rail and a high-side logic low voltage rail. The high-side logic low voltage rail is coupled to a high-voltage terminal of the core logic circuit. The second power-to-power clamping circuit is configured to receive ESD current between the rear driver voltage rail and the high-side logic low voltage rail during an ESD event.

[0112] In the above embodiments, the method further includes preventing electrostatic discharge current from passing through electronic components within the electronic device, the electronic components being coupled to the power supply voltage rail.

[0113] Those skilled in the art will understand that various modifications can be made to the above embodiments without departing from the broad inventive concept of the embodiments described above. Therefore, it should be understood that the invention disclosed herein is not limited to the specific embodiments disclosed, and is intended to cover various modifications within the spirit and scope of the invention.

Claims

1. An electronic device, characterized in that, include: The core logic circuit has a first terminal coupled to a power supply voltage rail and a second terminal coupled to an operating voltage rail, wherein the power supply voltage rail has a power supply voltage during standard operation and the operating voltage rail has an operating voltage during the standard operation. The rear driver voltage rail has an overdrive voltage during the standard operation, the overdrive voltage being greater than the operating voltage. The first power clamping circuit has a first terminal coupled to the power supply voltage rail and a second terminal coupled to the rear driver voltage rail; The low-side logic high-voltage rail is coupled to the first terminal of the core logic circuit; as well as A first power pair clamping circuit has a first terminal coupled to the low-side logic high voltage rail and a second terminal coupled to the rear driver voltage rail, the first power pair clamping circuit being configured to receive electrostatic discharge current between the rear driver voltage rail and the low-side logic high voltage rail.

2. The electronic device according to claim 1, characterized in that, The first power pair power clamping circuit includes a forward diode string, the forward diode string including an anode coupled to the rear driver voltage rail and a cathode coupled to the low-side logic high voltage rail.

3. The electronic device according to claim 1, characterized in that, It further includes a second power clamping circuit, the second power clamping circuit having a first terminal coupled to the power supply voltage rail and a second terminal coupled to the low-side logic high voltage rail.

4. The electronic device according to claim 1, characterized in that, It further includes a first diode string comprising one or more diodes, the first diode string having an anode coupled to the low-side logic high voltage rail and a cathode coupled to the rear driver voltage rail.

5. The electronic device according to claim 1, characterized in that, Including: A high-side logic low-voltage rail is coupled to the second terminal of the core logic circuit; and The second power pair clamping circuit has a first terminal coupled to the high-side logic low voltage rail and a second terminal coupled to the rear driver voltage rail. The second power pair clamping circuit is configured to receive electrostatic discharge current between the rear driver voltage rail and the high-side logic low voltage rail during a second electrostatic discharge event.

6. An electrostatic discharge protection circuit, characterized in that, include: The first power clamping circuit has a first terminal coupled to the power supply voltage rail and a second terminal coupled to the rear driver voltage rail; The first power pair clamping circuit has a first terminal coupled to a low-side logic high voltage rail and a second terminal coupled to the rear driver voltage rail, the low-side logic high voltage rail being coupled to a low voltage terminal of the core logic circuit, and the first power pair clamping circuit is configured to receive electrostatic discharge current between the rear driver voltage rail and the low-side logic high voltage rail. as well as The second power pair clamping circuit has a first terminal coupled to a high-side logic low voltage rail and a second terminal coupled to the rear driver voltage rail, the high-side logic low voltage rail being coupled to a high voltage terminal of the core logic circuit, and the second power pair clamping circuit is configured to receive electrostatic discharge current between the rear driver voltage rail and the high-side logic low voltage rail.

7. The electrostatic discharge protection circuit according to claim 6, characterized in that, Including: The second power clamping circuit has a first terminal coupled to the power supply voltage rail and a second terminal coupled to the low-side logic high voltage rail, and the second power clamping circuit is configured to receive electrostatic discharge current between the power supply voltage rail and the low-side logic high voltage rail. A third power clamping circuit has a first terminal coupled to the power supply voltage rail and a second terminal coupled to the high-side logic low voltage rail, and the third power clamping circuit is configured to receive electrostatic discharge current between the power supply voltage rail and the high-side logic low voltage rail. as well as A fourth power clamping circuit has a first terminal coupled to the power supply voltage rail and a second terminal coupled to the operating voltage rail, the fourth power clamping circuit being configured to receive electrostatic discharge current between the power supply voltage rail and the operating voltage rail.

8. The electrostatic discharge protection circuit according to claim 6, characterized in that, The first power pair power clamping circuit includes a forward diode string, the forward diode string including an anode coupled to the rear driver voltage rail and a cathode coupled to the low-side logic high voltage rail.

9. The electrostatic discharge protection circuit according to claim 6, wherein the first power pair clamping circuit comprises a resistor and a capacitor connected in series, and a plurality of transistors.

10. The electrostatic discharge protection circuit of claim 6, wherein the second power pair clamping circuit includes a forward diode string, the forward diode string including an anode coupled to the rear driver voltage rail and a cathode coupled to the low-side logic high voltage rail.

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