Photovoltaic grid-connected inverter inductance voltage-sharing circuit

Abstract

The utility model belongs to the field of photovoltaic inverters, and particularly relates to an inductance voltage-sharing circuit of a photovoltaic grid-connected inverter. The inductance voltage-sharing circuit comprises a main power supply unit, a sampling unit, a detection unit, a control unit, a driving unit and a balancing unit, the main power supply unit comprises an A group of capacitors and a B group of capacitors, and the sampling unit respectively collects voltages of the A group of capacitors and the B group of capacitors and detects which group of capacitors is high in voltage through the detection unit. And if the two groups of capacitors have voltage difference, the control unit drives the driving unit, the driving unit conducts the balancing unit, and the balancing unit actively balances the voltage of the A group of capacitors and the B group of capacitors. The inductance voltage-sharing circuit is high in equalization precision, integrally belongs to an inductance type energy transfer process, is low in energy consumption and high in efficiency, does not generate heat, and can be applied to severe environments due to the characteristics of electromagnetic conversion. When the two groups of main capacitors have a voltage difference, charges are transferred from a high capacitor to a low capacitor, and the purpose of active equalization can be achieved in the charging process.

Description

Technical Field

[0001] This utility model belongs to the field of photovoltaic inverters, and specifically relates to the inductor voltage equalization circuit of a photovoltaic grid-connected inverter. Background Technology

[0002] like Figure 1 As shown, the photovoltaic (PV) string converts DC power to AC power via a PV inverter and connects to the grid. The PV inverter includes a boost circuit, a voltage equalization circuit, and an inverter circuit. After the PV string's voltage is boosted by the boost circuit, it needs to be equalized by the voltage equalization circuit before the inverter circuit converts the DC power back to AC power. The boost circuit and the inverter circuit need to be connected via a DC bus. The DC bus provides a high-amplitude pulsating current to the inverter circuit and generates a pulsating voltage on the bus, thus requiring a capacitor to support the DC bus. The bus capacitor mainly absorbs the high-amplitude pulsating current on the DC bus, keeping the input voltage fluctuation within the allowable range. Simultaneously, the bus capacitor acts as a buffer between the PV input power and the grid-connected output power, achieving a balance between input and output energy. It is an essential component for decoupling input DC power and output AC power. The reliability of the bus capacitor directly affects the reliability of the inverter's operation, becoming a crucial aspect of inverter performance.

[0003] In photovoltaic inverters, due to the high operating voltage of the DC bus and the difficulty in selecting capacitors with this voltage rating, two capacitors with lower voltage ratings but the same voltage and capacitance are typically connected in series, and multiple sets are connected in parallel to make the total voltage adapt to the bus operating voltage level. Due to individual differences in the capacitors, the voltages on the two voltage-dividing capacitors will differ during inverter operation, with one voltage higher than the other. The higher voltage may exceed the capacitor's voltage rating, causing damage. Existing technology uses voltage equalization circuits to solve this problem, but currently, there is no voltage equalization circuit capable of actively equalizing voltage. Utility Model Content

[0004] To address the aforementioned problems, this utility model provides a novel inductor voltage equalization circuit for photovoltaic grid-connected inverters.

[0005] The specific technical solution of this utility model is as follows:

[0006] This utility model provides an inductive voltage equalization circuit for a photovoltaic grid-connected inverter. Its input terminal is a photovoltaic string. The photovoltaic string sequentially passes through a boost circuit, a voltage equalization circuit, and an inverter circuit to output AC power and connect to the mains grid. The boost circuit, the voltage equalization circuit, and the inverter circuit are connected via a BUS line. The voltage equalization circuit is an inductive voltage equalization circuit and includes a main power supply unit, a sampling unit, a detection unit, a control unit, a drive unit, and an equalization unit. The main power supply unit includes capacitors A and B. The sampling unit collects the voltages of capacitors A and B respectively and detects which capacitor group has a higher voltage using the detection unit. If there is a voltage difference between the two groups of capacitors, the control unit drives the drive unit, which in turn activates the equalization unit. The equalization unit actively equalizes the voltages of capacitors A and B.

[0007] In a further improvement, the A group of capacitors consists of multiple capacitors C1 connected in parallel, the B group of capacitors consists of multiple capacitors C2 connected in parallel, one end of the A group of capacitors is connected to the main capacitor BUS+, one end of the B group of capacitors is connected to the main capacitor BUS-, and the A group of capacitors and the B group of capacitors are connected in series and a neutral point BUS_M is led out.

[0008] In a further improvement, the photovoltaic grid-connected inverter inductor voltage equalization circuit also includes a voltage divider unit. One end of the voltage divider unit is connected to the main capacitor BUS+ and the other end is grounded. The voltage divider unit includes a first resistor string, a Zener diode D9, and a capacitor C86. The first resistor string is a series connection of multiple resistors R1. The Zener diode D9 is connected in parallel with the capacitor C86 and then connected in series with the first resistor string to lead out a first neutral point. The control unit is connected to the first neutral point.

[0009] In a further improvement, the sampling unit includes sampling resistors R2, R3, R4, and R5. Multiple sampling resistors R2 are connected in series to the main capacitor BUS+ and output BUS+_V. Multiple sampling resistors R3 are connected in series to the main capacitor BUS_M and output BUS+_M. Multiple sampling resistors R4 are connected in series to the main capacitor BUS_M and output BUS-_M. Multiple sampling resistors R5 are connected in series to the main capacitor BUS- and output BUS-_V.

[0010] In a further improvement, the detection unit includes optocoupler U105 and optocoupler U106. Pin 1 of optocoupler U105 is connected to BUS+_M, pin 2 of optocoupler U105 is connected to BUS+_V and BUS-_V, pin 1 of optocoupler U106 is connected to BUS+_V and BUS-_V, and pin 2 of optocoupler U106 is connected to BUS-_M. Pins 4 of both optocoupler U105 and optocoupler U106 are connected to the power supply. Pin 3 of optocoupler U105 outputs optocoupler KS2, and pins 3 of optocoupler U106 output optocoupler KS1.

[0011] In a further improvement, the control unit includes a first group of control units and a second group of control units, the drive unit includes a first group of drive units and a second group of drive units, and the equalization unit includes a first switching unit, a second switching unit, and an inductor; when the voltage of capacitor A is higher than the voltage of capacitor B, optocoupler U106 is turned on and sends a signal to the first group of control units, the voltage divider unit supplies power to the first group of drive units through the first group of control units, the first group of drive units turns on the first switching unit and charges capacitor B through the inductor; when the voltage of capacitor B is higher than the voltage of capacitor A, optocoupler U105 is turned on and sends a signal to the second group of control units, the voltage divider unit supplies power to the second group of drive units through the second group of control units, the second group of drive units turns on the second switching unit and charges capacitor A through the inductor; when the voltage of capacitor A is balanced with the voltage of capacitor B, the detection unit is turned off.

[0012] In a further improvement, the first control unit includes a power switch Q43, resistors R7 and R8. Resistors R7 and R8 are connected in series, with one end connected to the output optocoupler KS1 and the other end grounded, leading to a second neutral point. The gate (G) of power switch Q43 is connected to the second neutral point, the drain (D) of power switch Q43 is connected to the power supply and the first neutral point, and the source (S) of power switch Q43 is connected to the first drive unit. The second control unit includes a power switch Q2, resistors R19 and R20. Resistors R19 and R20 are connected in series, with one end connected to the output optocoupler KS2 and the other end grounded, leading to a third neutral point. The gate (G) of power switch Q2 is connected to the third neutral point, the drain (D) of power switch Q2 is connected to the power supply and the first neutral point, and the source (S) of power switch Q2 is connected to the second drive unit.

[0013] Further improvements include: the first set of drive units includes a drive chip U75, a first PWM module, and a diode D8; the second set of drive units includes a drive chip U76, a second PWM module, and a diode D7; pin 1 of both the first PWM module and drive chip U75 is connected to the source (s) terminal of power switch Q43; pin 2 of drive chip U75 is connected to the first PWM module to input a high-level signal; pin 4 of drive chip U75 is grounded; pin 7 of drive chip U75 is connected to the first switching unit; pin 6 of drive chip U75 is the VS output and is connected to the first switching unit; and pin 8 of drive chip U75 is the V output. Pin B is connected to the cathode of diode D8, and the anode of diode D8 is connected to pin 1 of driver chip U75; pin 1 of the second PWM module and driver chip U76 are both connected to the source of power switch Q2; pin 2 of driver chip U76 is connected to the second PWM module to input a high-level signal; pin 4 of driver chip U76 is grounded; pin 7 of driver chip U76 is connected to the second switching unit; pin 6 of driver chip U76 is the VS output and is connected to the second switching unit; pin 8 of driver chip U76 is VB and is connected to the cathode of diode D7; the anode of diode D7 is connected to pin 1 of driver chip U76.

[0014] In a further improvement, the first switching unit includes a power switch Q20 and a diode D11, and the second switching unit includes a power switch Q19 and a diode D10. The gate (G) of power switch Q20 is connected to pin 7 of driver chip U75, the drain (D) of power switch Q20 is connected to BUS+, and the source (S) of power switch Q20 is connected to pin 6 of driver chip U75 and pin 1 of the inductor. The gate (G) of power switch Q19 is connected to pin 7 of driver chip U76, the drain (D) of power switch Q19 is connected to BUS_M, and the source (S) of power switch Q19 is connected to pin 6 of driver chip U76 and pin 2 of the inductor. Pin 5 of the inductor is connected to BUS_M, and pin 6 is grounded. The anode of diode D11 is connected to pin 2 of the inductor, and the cathode of diode D11 is connected to BUS_M. The anode of diode D10 is connected to pin 1 of the inductor, and the cathode of diode D10 is connected to BUS+.

[0015] In a further improvement, the main power supply unit also includes capacitor C97, capacitor C98, and a second resistor string. The second resistor string consists of multiple resistors R6 connected in series. The multiple second resistor strings are connected in parallel to the capacitor group A, and the multiple second resistor strings are connected in parallel to the capacitor group B. One end of capacitor C97 is connected to the main capacitor BUS+, and one end of capacitor C98 is connected to the main capacitor BUS-. The neutral point of capacitors C97 and C98 connected in series is grounded.

[0016] The beneficial effects achieved by this utility model are as follows:

[0017] This invention provides a novel inductive voltage equalization circuit for photovoltaic grid-connected inverters. This circuit offers high equalization accuracy and operates on an inductive energy transfer process. It features low energy consumption, high efficiency, and no heat generation. Due to its electromagnetic conversion characteristics, it can be applied in harsh environments. When there is a voltage difference between the two main capacitors, the capacitor with the higher voltage will transfer charge to the capacitor with the lower voltage, thus achieving active equalization during the charging process. Attached Figure Description

[0018] Figure 1 This is a flowchart of photovoltaic grid connection in existing technology.

[0019] Figure 2 This is a structural block diagram of the inductor voltage equalization circuit of the photovoltaic grid-connected inverter in this utility model.

[0020] Figure 3 This is a circuit diagram of the inductor voltage equalization circuit of the photovoltaic grid-connected inverter in this utility model.

[0021] Figure 4 This is a circuit diagram of the main power supply unit in this utility model.

[0022] Figure 5 This is a circuit diagram of the sampling unit in this utility model.

[0023] Figure 6 This is a circuit diagram of the detection unit in this utility model.

[0024] Figure 7 This is a circuit diagram of the control unit in this utility model.

[0025] Figure 8 This is a circuit diagram of the driving unit in this utility model.

[0026] Figure 9 This is a circuit diagram of the equalization unit in this utility model.

[0027] Figure 10 This is a circuit diagram of the voltage divider unit, equalization unit, drive unit, and control unit in this utility model. Detailed Implementation

[0028] Before describing the technical solutions of the embodiments of this application, the technical scenarios of the embodiments of this application will first be described in conjunction with the accompanying drawings.

[0029] This utility model provides an inductor voltage equalization circuit for a photovoltaic grid-connected inverter. Its input terminal is a photovoltaic string. The photovoltaic string sequentially passes through a boost circuit, a voltage equalization circuit, and an inverter circuit to output AC power, which is then connected to the mains grid circuit. The boost circuit, voltage equalization circuit, and inverter circuit are connected via a BUS line. Figures 2-3As shown, the voltage equalization circuit is an inductive voltage equalization circuit, and includes a main power supply unit, a sampling unit, a detection unit, a control unit, a drive unit, and an equalization unit. The main power supply unit includes capacitors A and B. The sampling unit collects the voltages of capacitors A and B respectively and detects which group of capacitors has a higher voltage through the detection unit. If there is a voltage difference between the two groups of capacitors, the control unit drives the drive unit, the drive unit turns on the equalization unit, and the equalization unit actively equalizes the voltages of capacitors A and B.

[0030] The voltage difference threshold of the inductor voltage equalization circuit is set to 1.2V, which is the internal loss voltage of the optocoupler in the following text.

[0031] like Figure 4 As shown, group A consists of multiple capacitors C1 connected in parallel, and group B consists of multiple capacitors C2 connected in parallel. One end of the capacitors in group A is connected to the main capacitor BUS+, and one end of the capacitors in group B is connected to the main capacitor BUS-. The capacitors in group A and group B are connected in series and a neutral point BUS_M is drawn out.

[0032] like Figure 10 As shown, the photovoltaic grid-connected inverter inductor voltage equalization circuit also includes a voltage divider unit. One end of the voltage divider unit is connected to the main capacitor BUS+ and the other end is grounded. The voltage divider unit includes a first resistor string, a Zener diode D9 and a capacitor C86. The first resistor string is composed of multiple resistors R1 connected in series. The Zener diode D9 is connected in parallel with the capacitor C86 and then connected in series with the first resistor string to lead out the first neutral point. The control unit is connected to the first neutral point.

[0033] like Figure 5 As shown, the sampling unit includes sampling resistors R2, R3, R4, and R5. Multiple sampling resistors R2 are connected in series to the main capacitor BUS+ and output BUS+_V. Multiple sampling resistors R3 are connected in series to the main capacitor BUS_M and output BUS+_M. Multiple sampling resistors R4 are connected in series to the main capacitor BUS_M and output BUS-_M. Multiple sampling resistors R5 are connected in series to the main capacitor BUS- and output BUS-_V.

[0034] like Figure 6 As shown, the detection unit includes optocoupler U105 and optocoupler U106. Pin 1 of optocoupler U105 is connected to BUS+_M, and pin 2 of optocoupler U105 is connected to BUS+_V and BUS-_V. Pin 1 of optocoupler U106 is connected to BUS+_V and BUS-_V, and pin 2 of optocoupler U106 is connected to BUS-_M. Pins 4 of both optocoupler U105 and optocoupler U106 are connected to the power supply. Pin 3 of optocoupler U105 outputs optocoupler KS2, and pins 3 of optocoupler U106 output optocoupler KS1.

[0035] like Figure 2-10As shown, the control unit includes a first group of control units and a second group of control units; the drive unit includes a first group of drive units and a second group of drive units; and the equalization unit includes a first switching unit, a second switching unit, and an inductor. When the voltage of capacitor A is higher than the voltage of capacitor B, optocoupler U106 is turned on and sends a signal to the first group of control units. The voltage divider unit supplies power to the first group of drive units through the first group of control units, and the first group of drive units turns on the first switching unit and charges capacitor B through the inductor. When the voltage of capacitor B is higher than the voltage of capacitor A, optocoupler U105 is turned on and sends a signal to the second group of control units. The voltage divider unit supplies power to the second group of drive units through the second group of control units, and the second group of drive units turns on the second switching unit and charges capacitor A through the inductor. When the voltage of capacitor A is balanced with the voltage of capacitor B, the detection unit is turned off.

[0036] like Figure 7 As shown, the first control unit includes a power switch Q43, resistors R7 and R8. Resistors R7 and R8 are connected in series, with one end connected to the output optocoupler KS1 and the other end grounded and leading to the second neutral point. The gate (G) of power switch Q43 is connected to the second neutral point, the drain (D) of power switch Q43 is connected to the power supply and the first neutral point, and the source (S) of power switch Q43 is connected to the first drive unit. The second control unit includes a power switch Q2, resistors R19 and R20. Resistors R19 and R20 are connected in series, with one end connected to the output optocoupler KS2 and the other end grounded and leading to the third neutral point. The gate (G) of power switch Q2 is connected to the third neutral point, the drain (D) of power switch Q2 is connected to the power supply and the first neutral point, and the source (S) of power switch Q2 is connected to the second drive unit.

[0037] like Figure 8As shown, the first group of drive units includes a drive chip U75, a first PWM module, and a diode D8; the second group of drive units includes a drive chip U76, a second PWM module, and a diode D7. Pin 1 of both the first PWM module and the drive chip U75 is connected to the source (s) terminal of the power switch Q43. Pin 2 of the drive chip U75 is connected to the first PWM module to input a high-level signal. Pin 4 of the drive chip U75 is grounded. Pin 7 of the drive chip U75 is connected to the first switching unit. Pin 6 of the drive chip U75 is the VS output and is connected to the first switching unit. Pin 8 of the drive chip U75 is the VB output and is connected to... The cathode of diode D8 is connected to pin 1 of driver chip U75, and the anode of diode D8 is connected to pin 1 of driver chip U75. The second PWM module and pin 1 of driver chip U76 are both connected to the source of power switch Q2. Pin 2 of driver chip U76 is connected to the second PWM module to input a high-level signal. Pin 4 of driver chip U76 is grounded. Pin 7 of driver chip U76 is connected to the second switching unit. Pin 6 of driver chip U76 is the VS output and is connected to the second switching unit. Pin 8 of driver chip U76 is VB and is connected to the cathode of diode D7. The anode of diode D7 is connected to pin 1 of driver chip U76.

[0038] Wherein, VS is the high-side floating ground terminal, and VB is the high-side floating power supply; floating means that the voltage reference point of the power supply is not the earth, but the floating ground, and the floating power supply and the floating ground are an independent system relative to the earth. The first PWM module and the second PWM module are respectively responsible for providing high-level signals to the driver chip U75 and the driver chip U76, thereby turning on the first switching unit and the second switching unit respectively.

[0039] like Figure 9 As shown, the first switching unit includes a power switch Q20 and a diode D11, and the second switching unit includes a power switch Q19 and a diode D10. The gate (G) of power switch Q20 is connected to pin 7 of driver chip U75, the drain (D) of power switch Q20 is connected to BUS+, and the source (S) of power switch Q20 is connected to pin 6 of driver chip U75 and pin 1 of inductor. The gate (G) of power switch Q19 is connected to pin 7 of driver chip U76, the drain (D) of power switch Q19 is connected to BUS_M, and the source (S) of power switch Q19 is connected to pin 6 of driver chip U76 and pin 2 of inductor. Pin 5 of inductor is connected to BUS_M, and pin 6 is grounded. The anode of diode D11 is connected to pin 2 of inductor, and the cathode of diode D11 is connected to BUS_M. The anode of diode D10 is connected to pin 1 of inductor, and the cathode of diode D10 is connected to BUS+.

[0040] Among them, diodes D10 and D11 are rectifier diodes, which convert the high-frequency AC generated by the inductor coil into DC; the voltage divider unit converts the higher voltage and current into lower voltage and lower current, and forms a power supply with a step-down voltage of 12V after being connected in series with Zener diode D9. Zener diode D9 supplies power to driver chip U75, the first PWM module, driver chip U76, and the second PWM module; the power supply of the detection unit is preferably a 12V positive power supply.

[0041] The working principle of the inductor voltage equalization circuit in this embodiment is as follows: When the voltage of capacitor A is higher than that of capacitor B, optocoupler U106 will conduct power to the output optocoupler KS1, thereby turning on power switch Q43. The driver chip is responsible for providing drive signals to the power switch. When driver chip U75 receives a high-level signal from the first PWM module, power switch Q20 turns on. Due to electromagnetism, a high-frequency magnetic field is generated on the A side of inductor, and due to magnetoelectricity, a high-frequency alternating current is generated on the B side. After rectification by diode D11, it becomes DC to charge capacitor B; the reverse is also true.

[0042] The inductive voltage equalization circuit in this embodiment has high balancing accuracy. The entire process is an inductive energy transfer process, characterized by low energy consumption, high efficiency, and no heat generation. Due to the characteristics of electromagnetic conversion, it can be applied in harsh environments. When there is a voltage difference between the two main capacitors, the capacitor with the higher voltage will transfer charge to the capacitor with the lower voltage, thus achieving active balancing during the charging process.

[0043] like Figure 4 As shown, the main power supply unit also includes capacitor C97, capacitor C98, and a second resistor string. The second resistor string consists of multiple resistors R6 connected in series. The multiple second resistor strings are connected in parallel to capacitor group A and capacitor group B. One end of capacitor C97 is connected to the main capacitor BUS+, and one end of capacitor C98 is connected to the main capacitor BUS-. The neutral point of capacitors C97 and C98 connected in series is grounded.

[0044] Among them, capacitors C97 and C98 are both safety-certified Y capacitors. Connected in series, their neutral point is grounded. Their function is to eliminate interference and optimize power quality. Multiple second resistors are connected in parallel to capacitors in groups A and B, respectively, with the two sides in series. Their function is to balance the capacitor banks and quickly eliminate the charge across the capacitor banks after power failure, increasing the stability and safety of the equipment.

[0045] The power switch in this embodiment can be any one or more of the following combinations: relay, insulated gate bipolar transistor (IGBT), metal oxide semiconductor field-effect transistor (MOSFET, hereinafter referred to as MOS transistor), silicon carbide field-effect transistor (sIC MOSFET), etc., and this application embodiment does not make specific limitations.

[0046] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any utility model or the scope of the claims, but rather as descriptions of features that can embody specific embodiments of a particular utility model. Specific features described in this specification within the context of independent embodiments may also be implemented in combination with a single embodiment. Conversely, various features described within the context of a single embodiment may also be implemented independently in multiple embodiments, or in any suitable sub-combination. Furthermore, while features may be described above as acting in combination, and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and the claimed combination may be redirected to a sub-combination or a variation thereof.

[0047] In certain situations, multitasking and parallel processing can be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments.

[0048] Specific implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the activities described in the claims can be performed in a different order and still achieve the desired result. As an example, the processes described in the drawings do not necessarily require a specific order or sequence to be shown in order to achieve the desired result. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

1. A photovoltaic grid-connected inverter inductor voltage equalization circuit, wherein the input terminal is a photovoltaic string, the photovoltaic string sequentially passes through a boost circuit, a voltage equalization circuit, and an inverter circuit to output AC power and connect to the mains grid circuit, the boost circuit, the voltage equalization circuit, and the inverter circuit are connected via a BUS line, characterized in that, The voltage equalization circuit is an inductive voltage equalization circuit, and includes a main power supply unit, a sampling unit, a detection unit, a control unit, a driving unit, and an equalization unit. The main power supply unit includes a group of capacitors A and a group of capacitors B. The sampling unit collects the voltage of the group of capacitors A and the group of capacitors B respectively, and the detection unit detects which group of capacitors has a higher voltage. If there is a voltage difference between the two groups of capacitors, the control unit drives the driving unit, the driving unit turns on the equalization unit, and the equalization unit actively equalizes the voltage of the group of capacitors A and the group of capacitors B. It also includes a voltage divider unit, one end of which is connected to the main capacitor BUS+ and the other end is grounded; The control unit includes a first group of control units and a second group of control units; the drive unit includes a first group of drive units and a second group of drive units; and the equalization unit includes a first switching unit, a second switching unit, and an inductor. When the voltage of capacitor A is higher than the voltage of capacitor B, optocoupler U106 is turned on and sends a signal to the first control unit. The voltage divider unit supplies power to the first drive unit through the first control unit. The first drive unit turns on the first switch unit and charges capacitor B through the inductor. When the voltage of capacitor B is higher than the voltage of capacitor A, optocoupler U105 is turned on and sends a signal to the second control unit. The voltage divider unit supplies power to the second drive unit through the second control unit. The second drive unit turns on the second switch unit and charges capacitor A through the inductor. The detection unit is turned off when the voltage of capacitor group A is balanced with the voltage of capacitor group B.

2. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 1, characterized in that, The A group of capacitors consists of multiple capacitors C1 connected in parallel, and the B group of capacitors consists of multiple capacitors C2 connected in parallel. One end of the A group of capacitors is connected to the main capacitor BUS+, and one end of the B group of capacitors is connected to the main capacitor BUS-. The A group of capacitors and the B group of capacitors are connected in series and lead out to the neutral point BUS_M.

3. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 2, characterized in that, The voltage divider unit includes a first resistor string, a Zener diode D9, and a capacitor C86. The first resistor string consists of multiple resistors R1 connected in series. The Zener diode D9 is connected in parallel with the capacitor C86 and then connected in series with the first resistor string to form a first neutral point. The control unit is connected to the first neutral point.

4. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 3, characterized in that, The sampling unit includes sampling resistors R2, R3, R4, and R5. Multiple sampling resistors R2 are connected in series to the main capacitor BUS+ and output BUS+_V. Multiple sampling resistors R3 are connected in series to the main capacitor BUS_M and output BUS+_M. Multiple sampling resistors R4 are connected in series to the main capacitor BUS_M and output BUS-_M. Multiple sampling resistors R5 are connected in series to the main capacitor BUS- and output BUS-_V.

5. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 4, characterized in that, The detection unit includes optocoupler U105 and optocoupler U106. Pin 1 of optocoupler U105 is connected to BUS+_M, and pin 2 of optocoupler U105 is connected to BUS+_V and BUS-_V. Pin 1 of optocoupler U106 is connected to BUS+_V and BUS-_V, and pin 2 of optocoupler U106 is connected to BUS-_M. Pins 4 of both optocoupler U105 and optocoupler U106 are connected to the power supply. Pin 3 of optocoupler U105 outputs optocoupler KS2, and pins 3 of optocoupler U106 output optocoupler KS1.

6. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 1, characterized in that, The first group of control units includes a power switch Q43, a resistor R7 and a resistor R8. Resistors R7 and R8 are connected in series, one end of which is connected to the output optocoupler KS1 and the other end is grounded and led out to the second neutral point. The gate of the power switch Q43 is connected to the second neutral point, the drain of the power switch Q43 is connected to the power supply and the first neutral point, and the source of the power switch Q43 is connected to the first group of drive units. The second set of control units includes a power switch Q2, a resistor R19, and a resistor R20. Resistors R19 and R20 are connected in series, with one end connected to the output optocoupler KS2 and the other end grounded and led out to the third neutral point. The gate (G) of the power switch Q2 is connected to the third neutral point, the drain (D) of the power switch Q2 is connected to the power supply and the first neutral point, and the source (S) of the power switch Q2 is connected to the second set of drive units.

7. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 6, characterized in that, The first group of drive units includes a drive chip U75, a first PWM module and a diode D8; the second group of drive units includes a drive chip U76, a second PWM module and a diode D7. Pin 1 of the first PWM module and the driver chip U75 are both connected to the source (S) of the power switch Q43. Pin 2 of the driver chip U75 is connected to the first PWM module to input a high-level signal. Pin 4 of the driver chip U75 is grounded. Pin 7 of the driver chip U75 is connected to the first switching unit. Pin 6 of the driver chip U75 is the VS output and is connected to the first switching unit. Pin 8 of the driver chip U75 is the VB output and is connected to the cathode of diode D8. The anode of diode D8 is connected to pin 1 of the driver chip U75. The second PWM module and pin 1 of the driver chip U76 are both connected to the source (S) of the power switch Q2. Pin 2 of the driver chip U76 is connected to the second PWM module to input a high-level signal. Pin 4 of the driver chip U76 is grounded. Pin 7 of the driver chip U76 is connected to the second switching unit. Pin 6 of the driver chip U76 is the VS output and is connected to the second switching unit. Pin 8 of the driver chip U76 is the VB output and is connected to the cathode of diode D7. The anode of diode D7 is connected to pin 1 of the driver chip U76.

8. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 7, characterized in that, The first switching unit includes a power switch Q20 and a diode D11. The second switching unit includes a power switch Q19 and a diode D10. The gate (G) of power switch Q20 is connected to pin 7 of driver chip U75, the drain (D) of power switch Q20 is connected to BUS+, and the source (S) of power switch Q20 is connected to pin 6 of driver chip U75 and pin 1 of the inductor. The gate (G) of power switch Q19 is connected to pin 7 of driver chip U76, the drain (D) of power switch Q19 is connected to BUS_M, and the source (S) of power switch Q19 is connected to pin 6 of driver chip U76 and pin 2 of the inductor. Pin 5 of the inductor is connected to BUS_M, and pin 6 is grounded. The anode of diode D11 is connected to pin 2 of the inductor, and the cathode of diode D11 is connected to BUS_M. The anode of diode D10 is connected to pin 1 of the inductor, and the cathode of diode D10 is connected to BUS+.

9. The photovoltaic grid-connected inverter inductor voltage equalization circuit as described in claim 2, characterized in that, The main power supply unit also includes capacitor C97, capacitor C98, and a second resistor string. The second resistor string consists of multiple resistors R6 connected in series, multiple second resistor strings are connected in parallel to the A group of capacitors, and multiple second resistor strings are connected in parallel to the B group of capacitors. One end of capacitor C97 is connected to the main capacitor BUS+, and one end of capacitor C98 is connected to the main capacitor BUS-. The neutral point of capacitors C97 and C98 connected in series is grounded.

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