Semiconductor device structure and filter

Abstract

The utility model provides a semiconductor device structure and a filter, and the semiconductor device structure comprises a substrate which comprises a Bump region provided with a metal electrode and a non-Bump region of other regions connected with the Bump region; the laminated film is arranged on one side of the substrate and sequentially comprises a high-acoustic-resistance layer, a low-acoustic-resistance layer and a piezoelectric film from bottom to top, and the piezoelectric film covers part of the low-acoustic-resistance layer located in the non-Bump area; and the wiring electrode covers at least part of the low-acoustic-resistance layer in the Bump region, extends to one side, far away from the substrate, of the piezoelectric film and covers part of the piezoelectric film. The wiring electrode covers a part of the low-acoustic-resistance layer in the Bump region, extends to one side, far away from the substrate, of the piezoelectric film and covers a part of the piezoelectric film, so that the wiring electrode can be in direct contact with the low-acoustic-resistance layer, the binding force is enhanced, the problem of layering of the wiring electrode and the insulating layer in the preparation process is solved, and the production efficiency is improved. And the condition of partial electric leakage when the wiring electrode is combined with the substrate can be avoided.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a semiconductor device structure and a filter. Background Technology

[0002] Thin-film filters remove the piezoelectric film, low acoustic impedance layer, and high acoustic impedance layer from the bump region substrate through an etching process. Then, the groove and ramp regions are filled with insulating material. Subsequent packaging processes often use film lamination or spin coating to prepare the packaging layer, and the bump structure is formed in the opening region through an electroplating process.

[0003] However, during the fabrication of the encapsulation layer of thin-film filters, the stress of the encapsulation material itself can easily lead to delamination at the contact point between the wiring electrodes and the insulating layer. Utility Model Content

[0004] The problem solved by this invention is that current filters are prone to delamination between the wiring electrodes and the insulating layer during the manufacturing process.

[0005] To address the above problems, this utility model provides a semiconductor device structure, the semiconductor device structure comprising:

[0006] A substrate, wherein the substrate includes a bump region on which metal electrodes are disposed and a non-bump region of other regions connected to the bump region;

[0007] A laminated film disposed on one side of the substrate, the laminated film comprising, from bottom to top, a high acoustic resistance layer, a low acoustic resistance layer and a piezoelectric film, the piezoelectric film covering a portion of the low acoustic resistance layer located in the non-bump region;

[0008] Wiring electrode, the wiring electrode covering at least a portion of the low acoustic impedance layer located in the bump region, and extending to the side of the piezoelectric film away from the substrate and covering a portion of the piezoelectric film.

[0009] Optionally, the semiconductor device structure further includes:

[0010] An insulating layer is located between the wiring electrode and the piezoelectric film, wherein the insulating layer covers a portion of the low acoustic impedance layer located in the non-bump region and extends to the side of the piezoelectric film away from the substrate and covers a portion of the piezoelectric film.

[0011] Technical benefits: By covering the low acoustic impedance layer and the piezoelectric film with an insulating layer, the problem of ramp-up of wiring electrodes in subsequent processes can be solved. It also avoids the situation of wire breakage when the wiring electrodes are directly placed on the low acoustic impedance layer and the piezoelectric film. In addition, by covering part of the piezoelectric film with an insulating layer, the interface peeling between the piezoelectric film and the low acoustic impedance layer can be avoided.

[0012] Optionally, the insulating layer extends from the upper surface of the low acoustic impedance layer along the sidewall of the piezoelectric film to the upper surface of the piezoelectric film, and the side of the insulating layer that contacts the wiring electrode is a first inclined surface.

[0013] Technical Effects: By extending the insulating layer along the sidewall of the piezoelectric film to its upper surface, the insulating layer fills the step formed between the piezoelectric film and the low acoustic impedance layer, preventing gaps or connection breaks between the piezoelectric film and the wiring electrode, thus enhancing the bonding force between the wiring electrode and the piezoelectric film. Furthermore, by designing the side of the insulating layer in contact with the wiring electrode as a first inclined surface, the wiring electrode can grow more smoothly along this inclined surface, further reducing the likelihood of wire breakage during the fabrication process, thereby optimizing the reliability of the semiconductor device structure.

[0014] Optionally, in the non-bump region, the wiring electrode extends from the upper surface of the low acoustic impedance layer along the sidewall of the insulating layer to the upper surface of the insulating layer and the upper surface of the piezoelectric film.

[0015] Technical effect: By placing the wiring electrodes on the insulating layer, the problem of wiring electrode ramping is solved, and the situation of wire breakage during the forming process is improved.

[0016] Optionally, the side of the wiring electrode away from the insulating layer is a second inclined surface.

[0017] Technical effect: By setting this side as a second inclined surface, tensile stress can be reduced.

[0018] Optionally, along a direction perpendicular to the low acoustic resistance layer, the length of the contact area between the wiring electrode and the low acoustic resistance layer is greater than the length of the contact area between the insulating layer and the low acoustic resistance layer.

[0019] Technical effect: By setting it up in this way, the tilt angle between the first tilted surface and the second tilted surface can be less than 90°, thereby achieving a smooth transition of the wiring electrodes.

[0020] Optionally, the thickness of the low acoustic resistance layer in the bump region is less than or equal to the thickness of the low acoustic resistance layer in the region where the piezoelectric thin film is disposed.

[0021] Technical benefits: It can avoid the situation where the piezoelectric film is not completely etched.

[0022] Optionally, the semiconductor device structure further includes a packaging layer disposed on the side of the wiring electrode away from the substrate, wherein an opening penetrating the packaging layer is provided in the bump region, the opening being used to provide the metal electrode for connection with the wiring electrode.

[0023] Optionally, the side of the piezoelectric film that contacts the wiring electrode is an inclined surface.

[0024] Technical effect: By setting the side of the piezoelectric film that contacts the wiring electrode as an inclined surface, the problem of the wiring electrode climbing is solved, and the situation of wire breakage during the forming process is improved.

[0025] This application also provides a filter, which includes the semiconductor device structure described in any of the above embodiments.

[0026] The semiconductor device structure provided by this utility model includes a substrate, a multilayer film, and wiring electrodes. By covering a portion of the low acoustic impedance layer located in the bump region with the wiring electrodes and extending them to the side of the piezoelectric film away from the substrate and covering a portion of the piezoelectric film, the wiring electrodes can be in direct contact with the low acoustic impedance layer, enhancing the bonding force and solving the problem of delamination between the wiring electrodes and the insulating layer during the fabrication process. It can also avoid partial leakage when the wiring electrodes are bonded to the substrate. In addition, covering a portion of the piezoelectric film with the wiring electrodes can also achieve electrical connection between the piezoelectric film and the metal electrode. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the semiconductor device structure provided in the embodiments of this application;

[0028] Figure 2 This is another schematic diagram of the semiconductor device structure provided in the embodiments of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 100. Semiconductor device structure; 10. Substrate; 20. Laminated film; 30. Wiring electrode; 40. Insulating layer; 50. Encapsulation layer; A. Bump region;

[0031] 210, piezoelectric film; 220, low acoustic resistance layer; 230, high acoustic resistance layer; 510, opening. Detailed Implementation

[0032] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below.

[0033] Please see Figure 1 , Figure 1This is a schematic diagram of the semiconductor device structure provided in an embodiment of this application. The embodiment of this application provides a semiconductor device structure 100, which includes a substrate 10, a multilayer film 20 disposed on one side of the substrate 10, and wiring electrodes 30. The substrate 10 includes a bump region A with metal electrodes and non-bump regions connected to the bump region A. The multilayer film 20, from bottom to top, includes a high acoustic resistance layer 230, a low acoustic resistance layer 220, and a piezoelectric film 210. The piezoelectric film 210 covers a portion of the low acoustic resistance layer 220 located in the non-bump region. The wiring electrodes 30 cover at least a portion of the low acoustic resistance layer 220 located in the bump region A and extend to the side of the piezoelectric film 210 away from the substrate 10, covering a portion of the piezoelectric film 210. By covering a portion of the low acoustic impedance layer 220 located in the bump region A with the wiring electrode 30, and extending it to the side of the piezoelectric film 210 away from the substrate 10 and covering a portion of the piezoelectric film 210, the wiring electrode 30 can be in direct contact with the low acoustic impedance layer 220, enhancing the bonding force and solving the problem of delamination between the wiring electrode 30 and the insulating layer 40 during the fabrication process. It can also avoid partial leakage when the wiring electrode 30 is bonded to the substrate 10. In addition, by covering a portion of the piezoelectric film 210 with the wiring electrode 30, electrical connection between the piezoelectric film 210 and the metal electrode can be achieved.

[0034] The low acoustic resistance layer 220 and the high acoustic resistance layer 230 are disposed in the bump region A and the non-bump region. The high acoustic resistance layer 230 is a film in which the sound speed of the propagating bulk wave is higher than the sound speed of the elastic wave propagating in the piezoelectric film 210. The low acoustic resistance layer 220 is a film in which the sound speed of the propagating bulk wave is lower than the sound speed of the elastic wave propagating in the piezoelectric film 210. By providing the high acoustic resistance layer 230 and the low acoustic resistance layer 220 on one side of the piezoelectric film 210, the energy of the utilized elastic wave can be effectively confined to the portion where the piezoelectric film 210 and the high acoustic resistance layer 230 and the low acoustic resistance layer 220 are stacked, thereby improving the quality factor Q.

[0035] It should be noted that the wiring electrode 30 covering at least a portion of the low acoustic impedance layer 220 located in the bump region A can be understood as: the wiring electrode 30 covering the low acoustic impedance layer 220 located in the bump region A, or the wiring electrode 30 covering a portion of the low acoustic impedance layer 220 located in the bump region A. It is understood that the specific arrangement of the wiring electrode 30 in the bump region A can be configured according to actual conditions and is not limited here.

[0036] The piezoelectric film 210 is provided with multiple interdigitated electrodes. The wiring electrode 30 covers part of the piezoelectric film 210, so that the multiple interdigitated electrodes are electrically connected through the wiring electrode 30.

[0037] The piezoelectric film 210 includes side surfaces connected to an upper surface and a lower surface. In some embodiments, the side surface of the piezoelectric film 210 contacts the wiring electrode 30, and this side surface is an inclined surface, such as... Figure 2 As shown, by setting the side of the piezoelectric film 210 that contacts the wiring electrode 30 as an inclined surface, the problem of the wiring electrode 30 climbing is helped to be solved, and the situation of wire breakage during the formation process of the wiring electrode 30 is improved. In some other embodiments, the semiconductor device structure 100 also includes an insulating layer 40, the side of the piezoelectric film 210 contacts the insulating layer 40, and this side is a vertical surface, such as... Figure 1 As shown, by setting the side of the piezoelectric film in contact with the insulating layer 40 as a vertical surface, it is beneficial to reduce the processing difficulty of etching the piezoelectric film. In some other embodiments, the side of the piezoelectric film 210 contacts the insulating layer 40, and this side is an inclined surface. By setting the side of the piezoelectric film 210 in contact with the insulating layer 40 as an inclined surface, it is beneficial to set the side of the insulating layer in contact with the wiring electrode as an inclined surface, thereby solving the climbing problem of the wiring electrode 30 and improving the situation of wire breakage of the wiring electrode 30 during the formation process.

[0038] Please continue reading. Figure 1 An insulating layer 40 is located between the wiring electrode 30 and the piezoelectric film 210. The insulating layer 40 covers a portion of the low acoustic resistance layer 220 located in the non-bump region and extends to the side of the piezoelectric film 210 away from the substrate 10, covering a portion of the piezoelectric film 210. By covering the low acoustic resistance layer 220 and the piezoelectric film 210 with the insulating layer 40, the problem of ramp-up in the wiring electrode 30 during subsequent processes can be solved. It also avoids the possibility of wire breakage when the wiring electrode 30 is directly placed on the low acoustic resistance layer 220 and the piezoelectric film 210. Furthermore, by covering a portion of the piezoelectric film 210 with the insulating layer 40, interface delamination between the piezoelectric film 210 and the low acoustic resistance layer 220 can be avoided.

[0039] In some embodiments, the insulating layer 40 extends from the upper surface of the low acoustic impedance layer 220 along the sidewall of the piezoelectric film 210 to the upper surface of the piezoelectric film 210, and the side of the insulating layer 40 that contacts the wiring electrode 30 is a first inclined surface. By extending the insulating layer 40 along the sidewall of the piezoelectric film 210 to the upper surface of the piezoelectric film 210, the piezoelectric film 210 and the wiring electrode 30 can be seamlessly connected through the insulating layer 40, avoiding gaps or connection breaks between the piezoelectric film 210 and the wiring electrode 30 due to the steps formed between the piezoelectric film 210 and the low acoustic impedance layer 220, thus enhancing the bonding force between the wiring electrode 30 and the piezoelectric film 210. In addition, by setting the side of the insulating layer 40 that contacts the wiring electrode 30 as a first inclined surface, the wiring electrode 30 can grow better along the first inclined surface, further improving the situation of wire breakage during the formation process of the wiring electrode 30, thereby optimizing the reliability of the semiconductor device structure 100.

[0040] It is important to note that the angle formed between the first inclined surface of the insulating layer 40 and the upper surface of the low acoustic resistance layer 220 is less than 90°. This design ensures that the corners of the wiring electrode 30 have a smooth transition, making it less prone to cracking at the corners. The corner can be understood as the connection area between the portion of the wiring electrode 30 located in the low acoustic resistance layer 220 and the portion located in the insulating layer 40.

[0041] In some embodiments, the angle formed between the first inclined surface of the insulating layer 40 and the upper surface of the low acoustic impedance layer 220 can be, for example, 80°, 60°, 45°, 30°, etc. The specific value can be set according to the actual situation, and no specific limitation is made here.

[0042] In the non-bump area, the wiring electrode 30 extends from the upper surface of the low acoustic impedance layer 220 along the sidewall of the insulating layer 40 to the upper surface of the insulating layer 40 and the upper surface of the piezoelectric film 210. By setting the wiring electrode 30 on the insulating layer 40, the problem of the wiring electrode 30 climbing is solved, and the situation of the wiring electrode 30 breaking during the forming process is improved.

[0043] It is understandable that the side of the wiring electrode 30 away from the insulating layer 40 is the second inclined surface. By setting the second inclined surface, the situation of wire breakage of the wiring electrode 30 can be further improved, and by setting this side as the second inclined surface, tensile stress can be reduced.

[0044] In some embodiments, the first inclined surface is parallel to the second inclined surface.

[0045] In this configuration, along the direction perpendicular to the low acoustic resistance layer 220, the length of the contact area between the wiring electrode 30 and the low acoustic resistance layer 220 is greater than the length of the contact area between the insulating layer 40 and the low acoustic resistance layer 220. This arrangement allows the tilt angle between the first and second tilted surfaces to be less than 90°, thereby achieving a smooth transition for the wiring electrode 30.

[0046] It is understandable that the thickness of the low acoustic resistance layer 220 in the bump region is less than or equal to the thickness of the low acoustic resistance layer 220 in the region where the piezoelectric film 210 is disposed. That is, before the wiring electrode 30 and the insulating layer 40 are disposed, the piezoelectric film 210 in the area where the wiring electrode 30 and the insulating layer 40 contact the low acoustic resistance layer 220 is etched. In order to avoid the piezoelectric film 210 being incompletely etched, part of the low acoustic resistance layer 220 is etched, thereby forming that the thickness of the low acoustic resistance layer 220 in the bump region is less than or equal to the thickness of the low acoustic resistance layer 220 in the region where the piezoelectric film 210 is disposed.

[0047] The semiconductor device structure 100 also includes a packaging layer 50, which is disposed on the side of the wiring electrode 30 away from the substrate. An opening 510 is provided in the bump region A, penetrating the packaging layer 50. The opening 510 is used to place a metal electrode to connect with the wiring electrode 30.

[0048] In some embodiments, the substrate 10 is made of silicon, the wiring electrode 30 is made of PAD, and the insulating layer 40 is made of PI. Specific configurations can be made according to actual conditions, and no specific limitations are imposed here.

[0049] The material of the piezoelectric film 210 includes any one of LiTaO3, LiNbO3, ZnO, AlN, or PZT.

[0050] The high acoustic resistance layer 230 is made of any of the following materials: aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, DLC film, silicon, sapphire, lithium tantalate, lithium niobate, quartz and other piezoelectric materials, alumina, zirconium oxide, cordierite, andalusite, talc, forsterite and other ceramics, magnesium oxide, diamond, etc.

[0051] The material of the low acoustic impedance layer 220 includes any one of silicon oxide, glass, silicon oxynitride, tantalum oxide, or a compound in which fluorine, carbon, or boron has been added.

[0052] This application also provides a filter, which includes the semiconductor device structure 100 in any of the above embodiments. The specific details of the semiconductor device structure 100 are described above and will not be repeated here.

[0053] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor device structure, characterized in that, The semiconductor device structure includes: A substrate, wherein the substrate includes a bump region on which metal electrodes are disposed and a non-bump region of other regions connected to the bump region; A laminated film disposed on one side of the substrate, the laminated film comprising, from bottom to top, a high acoustic resistance layer, a low acoustic resistance layer and a piezoelectric film, the piezoelectric film covering a portion of the low acoustic resistance layer located in the non-bump region; Wiring electrode, the wiring electrode covering at least a portion of the low acoustic impedance layer located in the bump region, and extending to the side of the piezoelectric film away from the substrate and covering a portion of the piezoelectric film.

2. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure also includes: An insulating layer is located between the wiring electrode and the piezoelectric film, wherein the insulating layer covers a portion of the low acoustic impedance layer located in the non-bump region and extends to the side of the piezoelectric film away from the substrate and covers a portion of the piezoelectric film.

3. The semiconductor device structure according to claim 2, characterized in that, The insulating layer extends from the upper surface of the low acoustic impedance layer along the sidewall of the piezoelectric film to the upper surface of the piezoelectric film, and the side of the insulating layer that contacts the wiring electrode is a first inclined surface.

4. The semiconductor device structure according to claim 3, characterized in that, In the non-bump region, the wiring electrode extends from the upper surface of the low acoustic impedance layer along the sidewall of the insulating layer to the upper surface of the insulating layer and the upper surface of the piezoelectric film.

5. The semiconductor device structure according to claim 4, characterized in that, The side of the wiring electrode away from the insulating layer is a second inclined surface.

6. The semiconductor device structure according to any one of claims 2 to 5, characterized in that, Along a direction perpendicular to the low acoustic resistance layer, the length of the contact area between the wiring electrode and the low acoustic resistance layer is greater than the length of the contact area between the insulating layer and the low acoustic resistance layer.

7. The semiconductor device structure according to any one of claims 1 to 5, characterized in that, The thickness of the low acoustic resistance layer in the bump region is less than or equal to the thickness of the low acoustic resistance layer in the region where the piezoelectric thin film is disposed.

8. The semiconductor device structure according to any one of claims 1 to 4, characterized in that, The semiconductor device structure further includes a packaging layer disposed on the side of the wiring electrode away from the substrate, wherein an opening penetrating the packaging layer is provided in the bump region, the opening being used to provide the metal electrode for connection with the wiring electrode.

9. The semiconductor device structure according to claim 1, characterized in that, The side of the piezoelectric film that contacts the wiring electrode is an inclined surface.

10. A filter, characterized in that, The filter comprises the semiconductor device structure described in any one of claims 1 to 9.

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