Voltage and current rapid acquisition digital control circuit

Abstract

The utility model discloses a voltage and current rapid acquisition digital control circuit, which comprises a multi-channel digital-to-analog conversion circuit, and a voltage photoelectric isolation acquisition circuit and a current rapid acquisition circuit which are connected with the multi-channel digital-to-analog conversion circuit, and the multi-channel digital-to-analog conversion circuit comprises a multi-channel ADC chip. The output end of the multi-channel ADC chip is connected with an FPGA processor, and the multi-channel ADC chip is used for converting the analog quantity of accessed voltage and current signals into digital quantity data and transmitting the digital quantity data to the FPGA processor in a bus mode. According to the utility model, the photoelectric isolator whose maximum delay time from input to output does not exceed 3.3 [mu] s can be used to realize signal photoelectric isolation amplification, the differential amplification filter circuit is connected in parallel with a 1nF capacitor to give consideration to both signal filtering stability and capacitor charging rapidity, and the ADC conversion chip whose resolution is 16bit and capable of parallel acquisition is selected. And multi-channel high-precision and rapid parallel analog-to-digital conversion is realized.

Description

Technical Field

[0001] This utility model relates to the field of digital control circuits, specifically a digital control circuit for rapid voltage and current acquisition. Background Technology

[0002] With the increasing demand for speed brought about by digital control of converters, the requirements for analog signal acquisition opto-isolation design and multi-channel high-precision parallel digital-to-analog conversion circuit design are becoming more and more stringent. In some digital control power supply systems, the actual need for simultaneous high-speed and high-precision acquisition of multiple analog signals is met by the time-consuming serial gating of multiplexers. Low-resolution external or built-in ADC processing chips can never meet the requirements of high-precision control. The circuits often have serious filtering interference and slow charging time, and cannot meet the requirements of fast and high-precision control systems. Utility Model Content

[0003] The purpose of this invention is to provide a digital control circuit for rapid acquisition of voltage and current, so as to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model provides the following technical solution: a digital control circuit for rapid voltage and current acquisition, comprising a multi-channel digital-to-analog converter circuit, and a voltage opto-isolated acquisition circuit and a rapid current acquisition circuit connected to the multi-channel digital-to-analog converter circuit. The input terminals of the voltage opto-isolated acquisition circuit and the rapid current acquisition circuit are connected to a power supply. The voltage opto-isolated acquisition circuit is used to acquire voltage signals, and the voltage opto-isolated acquisition circuit includes a voltage divider circuit, an opto-isolator, and a differential output circuit. The input port of the opto-isolator is connected to a capacitor component for common-mode interference filtering, and the output terminal of the opto-isolator is connected to the differential output circuit.

[0005] The fast current acquisition circuit is used to acquire current signals. The fast current acquisition circuit includes a front-stage follower circuit and a rear-stage follower circuit. The input terminal of the front-stage follower circuit is connected to a second RC filter circuit, and the output terminal of the rear-stage follower circuit is connected to a third RC filter capacitor. The output terminals of the second RC filter circuit and the third RC filter circuit are connected to a multi-channel digital-to-analog converter circuit.

[0006] The multi-channel analog-to-digital converter circuit includes a multi-channel ADC chip. The output of the multi-channel ADC chip is connected to an FPGA processor. The multi-channel ADC chip is used to convert the analog voltage and current signals into digital data and then transmit them to the FPGA processor via a bus.

[0007] Furthermore, the differential output circuit includes a differential amplifier, a resistor R11 connected to ground at the input of the differential amplifier, and a resistor R12 connected to the feedback of the differential amplifier. Both resistor R12 and resistor R11 are connected in parallel with capacitors.

[0008] Furthermore, the output of the differential amplifier is connected to a first RC filter circuit, the output of which is connected to a multi-channel ADC chip. The first RC filter circuit includes a resistor R13 and a filter capacitor C8, and the filter capacitor C8 is a 1000pF capacitor.

[0009] Furthermore, the pre-amplifier follower circuit includes a first amplifier, and the post-amplifier follower circuit includes a second amplifier. The non-inverting input of the second amplifier is connected to the output of the first amplifier through a resistor R20. The non-inverting input of the second amplifier is connected in parallel with a resistor R21 and a capacitor C11, and the inverting input of the second amplifier is connected in parallel with a resistor R22 and a capacitor C12.

[0010] Furthermore, the filter capacitor values ​​in the second and third RC filter circuits are 80-4800pF.

[0011] The beneficial effects of this utility model are as follows: This utility model has a signal scaling opto-isolation circuit and a multi-channel parallel input ADC circuit. It can use an opto-isolator with a maximum input-to-output delay time of no more than 3.3μs to achieve signal opto-isolation amplification. The differential amplification filter circuit uses a 1nF capacitor in parallel to balance signal filtering stability and capacitor charging speed. It also selects an ADC conversion chip with a resolution of 16bit and parallel acquisition capability to achieve multi-channel high-precision and fast parallel analog-to-digital conversion, solving the requirement of digital control power conversion function for fast and high-precision signal acquisition control. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the principle of this utility model;

[0013] Figure 2 This is a circuit diagram of the voltage photoelectric isolation acquisition circuit of this utility model;

[0014] Figure 3 This is a circuit diagram for the rapid current acquisition of this utility model.

[0015] In the diagram: 1 Power supply, 2 Voltage opto-isolation acquisition circuit, 21 Opto-isolator, 22 Differential amplifier, 3 Current fast acquisition circuit, 31 First amplifier, 32 Second amplifier, 4 Multi-channel digital-to-analog converter circuit, 41 Multi-channel ADC chip, 5 FPGA processor. Detailed Implementation

[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0017] Please see Figure 1-3 This invention provides a technical solution for a digital control circuit for rapid voltage and current acquisition. The circuit includes a multi-channel digital-to-analog converter (DAC) circuit 4, and a voltage opto-isolated acquisition circuit 2 and a current rapid acquisition circuit 3 connected to the DAC circuit 4. The input terminals of the voltage opto-isolated acquisition circuit 2 and the current rapid acquisition circuit 3 are connected to a power supply 1. The voltage opto-isolated acquisition circuit 2 is used to acquire voltage signals and includes a voltage divider circuit, an opto-isolator 21, and a differential output circuit. The input port of the opto-isolator 21 is connected to a capacitor bank for common-mode interference filtering. The output of the opto-isolator 21 is connected to a differential output circuit. The differential output circuit includes a differential amplifier 22, a resistor R11 connected to ground at the input of the differential amplifier 22, and a resistor R12 connected to the feedback of the differential amplifier 22. Both the resistor R12 and the resistor R11 are connected in parallel with capacitors. The output of the differential amplifier 22 is connected to a first RC filter circuit. The output of the first RC filter circuit is connected to a multi-channel ADC chip 41. The first RC filter circuit includes a resistor R13 and a filter capacitor C8. The filter capacitor C8 is, but is not limited to, a 1000pF capacitor.

[0018] It should be noted that the voltage divider circuit consists of resistors R1, R2, R3, R5, R4, diode D1, capacitor C1, resistors R6, R7, R8, capacitors C2 and C3. The operating principle of this voltage opto-isolated acquisition circuit 2 is as follows: Power supply 1 uses, but is not limited to, a 270V high-voltage power supply; the 270V high-voltage power supply is divided by the voltage divider circuit, and the resistors used in the voltage divider circuit have an accuracy of 0.1% to improve the voltage division accuracy. Capacitors C2 and C3 used at the input port of opto-isolator 21 use 0.01μF ceramic capacitors for common-mode interference filtering; the opto-isolator 21 uses, but is not limited to, a 270V high-voltage power supply. For the linear opto-isolator, the input signal frequency bandwidth of opto-isolator 21 is 100KHz, the maximum input-to-output delay time does not exceed 3.3μs, and the amplification factor of opto-isolator 21 is twelve times. Finally, the differential signal output of opto-isolator 21 is sent to the differential amplifier circuit. In the differential amplifier circuit, the input resistor R12 and the ground resistor R11 are both connected in parallel with a 1nF capacitor, which not only improves the stability of the open-loop circuit, but also the charging time of the capacitor is in the nanosecond range. The first RC filter circuit at the output of the differential output circuit has a filter capacitor of 1000pF. Through calculation, it can be found that the time from signal input to circuit signal output is no more than 5μs.

[0019] In this embodiment, the aforementioned fast current acquisition circuit 3 is used to acquire current signals. The fast current acquisition circuit 3 includes a pre-stage follower circuit and a post-stage follower circuit. The input terminal of the pre-stage follower circuit is connected to a second RC filter circuit, and the output terminal of the post-stage follower circuit is connected to a third RC filter capacitor. The output terminals of the second and third RC filter circuits are connected to the multi-channel digital-to-analog converter circuit 4. The pre-stage follower circuit includes a first amplifier 31, and the post-stage follower circuit includes a second amplifier 32. The non-inverting input terminal of the second amplifier 32 is connected to the output terminal of the first amplifier 31 through a resistor R20. A resistor R21 and a capacitor C11 are connected in parallel to the non-inverting input terminal of the second amplifier 32, and a resistor R22 and a capacitor C12 are connected in parallel to the inverting input terminal of the second amplifier 32. The filter capacitor values ​​in the second and third RC filter circuits are 80-4800pF.

[0020] It should be noted that the second RC filter circuit includes resistors R14, R15, R16, R17, capacitor C9, and resistor R18. The output terminal of resistor R15 is connected to resistor R17, and the output terminal of resistor R17 is connected to the non-inverting input terminal of the first amplifier 31. A diode D2 is connected between resistors R14 and R15. The capacitor C9 is, but is not limited to, a 4700pF capacitor. The third RC filter circuit includes resistors R19, R21, and R2... 2. Resistor R23 and capacitor C13. Resistor R22 is connected to the inverting input terminal of the second amplifier 32 and serves as a feedback resistor. Resistor R21 is connected to the non-inverting input terminal of the second amplifier 32 and serves as a voltage divider resistor. Capacitor C12 is connected in parallel across resistor R22, and capacitor C11 is connected in parallel across resistor R21. Both capacitors C11 and C12 mentioned are 100pF capacitors. The acquisition time of this fast current acquisition circuit 3 is no more than six μs.

[0021] In this embodiment, the multi-channel digital-to-analog converter circuit includes a multi-channel ADC chip. The output of the multi-channel ADC chip is connected to an FPGA processor. The multi-channel ADC chip is used to convert the input analog voltage and current signals into digital data and then transmit them to the FPGA processor via a bus. The multi-channel ADC chip has a resolution of 16 bits, and the maximum conversion time is no more than 4 μs. In this multi-channel high-resolution digital-to-analog converter circuit, the voltage and current signals acquired by the voltage opto-isolated acquisition circuit 2 and the current fast acquisition circuit 3 are sent to the multi-channel ADC chip 41 and followed by a tracking circuit. The circuit provides buffering and anti-interference functions, and the RC capacitor in this circuit is 100pF, with an acquisition time of approximately 10ns. The maximum time for the analog-to-digital conversion of the multiple voltage signals processed by the follower circuit to the multi-channel ADC chip 41 is no more than 4μs. After processing by the ADC, the analog signals are converted into digital data and transmitted to the FPGA processor 5 via a bus. After the voltage and current signal acquisition and processing circuits and the multi-channel ADC chip 41, the time for the multiple key analog signals to be sent to the FPGA is no more than 10μs, which meets the requirement of 26.6μs for fast control calculation and control output within one cycle of the system.

[0022] The above embodiments only illustrate preferred embodiments of the present utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present utility model, and these all fall within the protection scope of the present utility model. In the present utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part. Although embodiments of the present utility model have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present utility model. The scope of the present utility model is defined by the appended claims and their equivalents.

Claims

1. A digital control circuit for rapid acquisition of voltage and current, characterized in that: The device includes a multi-channel digital-to-analog converter circuit, a voltage opto-isolated acquisition circuit and a current fast acquisition circuit connected to the multi-channel digital-to-analog converter circuit. The input terminals of the voltage opto-isolated acquisition circuit and the current fast acquisition circuit are connected to a power supply. The voltage opto-isolated acquisition circuit is used to acquire voltage signals. The voltage opto-isolated acquisition circuit includes a voltage divider circuit, an opto-isolator and a differential output circuit. The input port of the opto-isolator is connected to a capacitor component for common-mode interference filtering. The output terminal of the opto-isolator is connected to the differential output circuit. The fast current acquisition circuit is used to acquire current signals. The fast current acquisition circuit includes a front-stage follower circuit and a rear-stage follower circuit. The input terminal of the front-stage follower circuit is connected to a second RC filter circuit, and the output terminal of the rear-stage follower circuit is connected to a third RC filter capacitor. The output terminals of the second RC filter circuit and the third RC filter circuit are connected to a multi-channel digital-to-analog converter circuit. The multi-channel analog-to-digital converter circuit includes a multi-channel ADC chip. The output of the multi-channel ADC chip is connected to an FPGA processor. The multi-channel ADC chip is used to convert the analog voltage and current signals into digital data and then transmit them to the FPGA processor via a bus.

2. The voltage and current rapid acquisition digital control circuit according to claim 1, characterized in that: The differential output circuit includes a differential amplifier, a resistor R11 connected to ground at the input of the differential amplifier, and a resistor R12 connected to the feedback of the differential amplifier. Both resistor R12 and resistor R11 are connected in parallel with capacitors.

3. The voltage and current rapid acquisition digital control circuit according to claim 2, characterized in that: The output of the differential amplifier is connected to a first RC filter circuit, the output of which is connected to a multi-channel ADC chip. The first RC filter circuit includes a resistor R13 and a filter capacitor C8, and the filter capacitor C8 is a 1000pF capacitor.

4. The voltage and current rapid acquisition digital control circuit according to claim 1, characterized in that: The preamplifier circuit includes a first amplifier, and the postamplifier circuit includes a second amplifier. The non-inverting input of the second amplifier is connected to the output of the first amplifier through a resistor R20. The non-inverting input of the second amplifier is connected in parallel with a resistor R21 and a capacitor C11, and the inverting input of the second amplifier is connected in parallel with a resistor R22 and a capacitor C12.

5. The voltage and current rapid acquisition digital control circuit according to claim 1, characterized in that: The filter capacitor values ​​in the second and third RC filter circuits are 80-4800pF.

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